Add Luckfox Pico 86Panel Support (#274)
* project/cfg/BoardConfig_IPC/overlay : Add Luckfox Pico 86Panel overlay files Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/source/kernel/arch/arm/boot/dts : Add Luckfox Pico 86Panel device tree files Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC : Add Luckfox Pico 86Panel BoardConfig files Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/build.sh : Add the lunch menu item of Luckfox Pico 86Panel Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/source/kernel/arch/arm/configs : Add Goodix driver module configuration for RV1106 Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/tools/board/buildroot/luckfox_pico_w_defconfig : Add rsync command for Luckfox Pico Buildroot system Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-ubuntu-config : Add rysnc command for Luckfox Pico Ubuntu system Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-config/etc/init.d : Add MIC initialization script to improve default recording quality Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/tools/board/buildroot/busybox_patch : Add patches to enable Chinese display support in the terminal and allow the reboot command to accept parameters Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/Makefile : Automatically apply BusyBox patches when building the Buildroot image Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/source/kernel/arch/arm/kernel/setup.c : Make the kernel retrieve the unique CPU serial number Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-config/usr/bin/luckfox-config : Fix errors and add support for eMMC rootfs backup Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/source/kernel/arch/arm/boot/dts : Make Luckfox Pico Ultra and Luckfox Pico Pi default to using i2c4 for CSI cameras Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-ubuntu-ultra/usr/bin/wifi_bt_init.sh : Enable wireless module initialization support for Ubuntu on Luckfox Pico 86Panel and Luckfox Pico Pi Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC : Add executable permission to the BoardConfig scripts Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * sysdrv/source/uboot : Resolve the issue of fast boot failure on certain eMMC models Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC/luckfox-rv1106-tb-emmc-post.sh : Resolve the issue of file system initialization failure during eMMC fast boot Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/build.sh : Fix the issue of submodule switch failure Signed-off-by: luckfox-eng29 <eng29@luckfox.com> * project/app/rkipc/rkipc/src : Make sure that changes to rkipc.ini can be applied and take effect after modification Signed-off-by: eng29 <eng29@luckfox.com> * project/cfg/BoardConfig_IPC : Discontinue support for Ubuntu Signed-off-by: eng29 <eng29@luckfox.com> * project/build.sh : Discontinue support for Ubuntu Signed-off-by: eng29 <eng29@luckfox.com> * sysdrv/Makefile : Discontinue support for Ubuntu Signed-off-by: eng29 <eng29@luckfox.com> * README.md : Update description README_CN.md : Update description Signed-off-by: eng29 <eng29@luckfox.com> * . : Delete the Ubuntu rootfs submodule Signed-off-by: eng29 <eng29@luckfox.com> * sysdrv/drv_ko/wifi/aic8800dc : Update the aic8800dc driver Signed-off-by: eng29 <eng29@luckfox.com> --------- Signed-off-by: luckfox-eng29 <eng29@luckfox.com> Signed-off-by: eng29 <eng29@luckfox.com>
This commit is contained in:
@@ -83,5 +83,5 @@ clean:
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cd aic8800_bsp/;make clean;cd ..
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cd aic8800_fdrv/;make clean;cd ..
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cd aic8800_btlpm/;make clean;cd ..
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rm -rf modules.order Module.symvers .tmp_versions/
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rm -rf modules.order Module.symvers .modules.order.cmd .Module.symvers.cmd .tmp_versions/
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@@ -28,9 +28,11 @@ CONFIG_FORCE_DPD_CALIB = y
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CONFIG_LOFT_CALIB = n
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CONFIG_EXT_FEM_8800DCDW = n
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CONFIG_RESV_MEM_SUPPORT ?= y
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CONFIG_AMSDU_RX = n
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CONFIG_AMSDU_RX = y
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CONFIG_IRQ_FALL ?= n
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CONFIG_SDIO_BT = n
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CONFIG_RADAR_OR_IR_DETECT =n
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CONFIG_FOR_IPCAM = n
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ifeq ($(CONFIG_EXT_FEM_8800DCDW), y)
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CONFIG_DPD = n
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@@ -57,6 +59,9 @@ ccflags-$(CONFIG_RESV_MEM_SUPPORT) += -DCONFIG_RESV_MEM_SUPPORT
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ccflags-$(CONFIG_AMSDU_RX) += -DCONFIG_AMSDU_RX
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ccflags-$(CONFIG_IRQ_FALL) += -DCONFIG_IRQ_FALL
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ccflags-$(CONFIG_SDIO_BT) += -DCONFIG_SDIO_BT
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ccflags-$(CONFIG_RADAR_OR_IR_DETECT) += -DCONFIG_RADAR_OR_IR_DETECT
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ccflags-$(CONFIG_FOR_IPCAM) += -DCONFIG_FOR_IPCAM
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obj-m := $(MODULE_NAME).o
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$(MODULE_NAME)-y := \
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@@ -126,6 +131,8 @@ MODDESTDIR ?= /lib/modules/$(KVER)/kernel/drivers/net/wireless/
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ARCH ?= x86_64
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CROSS_COMPILE ?=
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endif
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ccflags-y += -Wno-unused-function
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###########################################
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all: modules
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@@ -6,101 +6,118 @@ extern int adap_test;
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typedef u32 (*array2_tbl_t)[2];
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#define AIC_PATCH_MAGIG_NUM 0x48435450 // "PTCH"
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#define AIC_PATCH_MAGIG_NUM_2 0x50544348 // "HCTP"
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#define AIC_PATCH_BLOCK_MAX 4
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#define AIC_PATCH_MAGIG_NUM 0x48435450 // "PTCH"
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#define AIC_PATCH_MAGIG_NUM_2 0x50544348 // "HCTP"
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#define AIC_PATCH_BLOCK_MAX 4
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typedef struct {
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uint32_t magic_num;
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uint32_t pair_start;
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uint32_t magic_num_2;
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uint32_t pair_count;
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uint32_t block_dst[AIC_PATCH_BLOCK_MAX];
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uint32_t block_src[AIC_PATCH_BLOCK_MAX];
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uint32_t block_size[AIC_PATCH_BLOCK_MAX]; // word count
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uint32_t magic_num;
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uint32_t pair_start;
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uint32_t magic_num_2;
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uint32_t pair_count;
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uint32_t block_dst[AIC_PATCH_BLOCK_MAX];
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uint32_t block_src[AIC_PATCH_BLOCK_MAX];
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uint32_t block_size[AIC_PATCH_BLOCK_MAX]; // word count
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} aic_patch_t;
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#define AIC_PATCH_OFST(mem) ((size_t) &((aic_patch_t *)0)->mem)
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#define AIC_PATCH_OFST(mem) ((size_t) & ((aic_patch_t *)0)->mem)
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#define AIC_PATCH_ADDR(mem) ((u32)(aic_patch_str_base + AIC_PATCH_OFST(mem)))
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u32 aicbsp_syscfg_tbl_8800d80[][2] = {
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};
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u32 aicbsp_syscfg_tbl_8800d80[][2] = {};
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int aicbsp_system_config_8800d80(struct aic_sdio_dev *sdiodev)
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{
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int syscfg_num = sizeof(aicbsp_syscfg_tbl_8800d80) / sizeof(u32) / 2;
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int ret, cnt;
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for (cnt = 0; cnt < syscfg_num; cnt++) {
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ret = rwnx_send_dbg_mem_write_req(sdiodev, aicbsp_syscfg_tbl_8800d80[cnt][0], aicbsp_syscfg_tbl_8800d80[cnt][1]);
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ret = rwnx_send_dbg_mem_write_req(
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sdiodev, aicbsp_syscfg_tbl_8800d80[cnt][0],
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aicbsp_syscfg_tbl_8800d80[cnt][1]);
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if (ret) {
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printk("%x write fail: %d\n", aicbsp_syscfg_tbl_8800d80[cnt][0], ret);
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printk("%x write fail: %d\n",
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aicbsp_syscfg_tbl_8800d80[cnt][0], ret);
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return ret;
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}
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}
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return 0;
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}
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u32 adaptivity_patch_tbl_8800d80[][2] = {
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{0x000C, 0x0000320A}, //linkloss_thd
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{0x009C, 0x00000000}, //ac_param_conf
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{0x0168, 0x00010000}, //tx_adaptivity_en
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{ 0x000C, 0x0000320A }, //linkloss_thd
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{ 0x009C, 0x00000000 }, //ac_param_conf
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{ 0x0168, 0x00010000 }, //tx_adaptivity_en
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};
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#define USER_CHAN_MAX_TXPWR_EN_FLAG (0x01U << 1)
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#define USER_TX_USE_ANA_F_FLAG (0x01U << 2)
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#define USER_PWROFST_COVER_CALIB_FLAG 0x01U
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#define USER_CHAN_MAX_TXPWR_EN_FLAG (0x01U << 1)
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#define USER_TX_USE_ANA_F_FLAG (0x01U << 2)
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#define USER_APM_PRBRSP_OFFLOAD_DISABLE_FLAG (0x01U << 3)
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#define CFG_USER_CHAN_MAX_TXPWR_EN 0
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#define CFG_USER_TX_USE_ANA_F 0
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#define CFG_PWROFST_COVER_CALIB 1
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#define CFG_USER_CHAN_MAX_TXPWR_EN 1
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#define CFG_USER_TX_USE_ANA_F 0
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#define CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE 0
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#define CFG_USER_EXT_FLAGS_EN (CFG_USER_CHAN_MAX_TXPWR_EN || CFG_USER_TX_USE_ANA_F)
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#define CFG_USER_EXT_FLAGS_EN \
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(CFG_PWROFST_COVER_CALIB || CFG_USER_CHAN_MAX_TXPWR_EN || \
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CFG_USER_TX_USE_ANA_F || CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE)
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u32 patch_tbl_8800d80[][2] = {
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#ifdef USE_5G
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{0x00b4, 0xf3010001},
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#else
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{0x00b4, 0xf3010000},
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#endif
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#ifdef USE_5G
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{ 0x00b4, 0xf3010001 },
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#else
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{ 0x00b4, 0xf3010000 },
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#endif
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#if defined(CONFIG_AMSDU_RX)
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{0x170, 0x0100000a}
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{ 0x170, 0x0100000a },
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#endif
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#ifdef CONFIG_IRQ_FALL
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{0x00000170, 0x0000010a}, //irqf
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{ 0x00000170, 0x0000010a }, //irqf
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#endif
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#if CFG_USER_EXT_FLAGS_EN
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{0x0188, 0x00000001
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#if CFG_USER_CHAN_MAX_TXPWR_EN
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| USER_CHAN_MAX_TXPWR_EN_FLAG
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#endif
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#if CFG_USER_TX_USE_ANA_F
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| USER_TX_USE_ANA_F_FLAG
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#endif
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}, // user_ext_flags
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#endif
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#if CFG_USER_EXT_FLAGS_EN
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{ 0x0188, 0x00000000
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#if CFG_PWROFST_COVER_CALIB
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| USER_PWROFST_COVER_CALIB_FLAG
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#endif
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#if CFG_USER_CHAN_MAX_TXPWR_EN
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| USER_CHAN_MAX_TXPWR_EN_FLAG
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#endif
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#if CFG_USER_TX_USE_ANA_F
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| USER_TX_USE_ANA_F_FLAG
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#endif
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#if CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE
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| USER_APM_PRBRSP_OFFLOAD_DISABLE_FLAG
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#endif
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}, // user_ext_flags
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#endif
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#ifdef CONFIG_RADAR_OR_IR_DETECT
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{ 0x019c, 0x00000100 }, //enable radar detect
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#endif
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};
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#ifdef CONFIG_OOB
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// for 8800d40/d80 map data1 isr to gpiob1
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u32 gpio_cfg_tbl_8800d40d80[][2] = {
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{0x40504084, 0x00000006},
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{0x40500040, 0x00000000},
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{0x40100030, 0x00000001},
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{0x40241020, 0x00000001},
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{0x40240030, 0x00000004},
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{0x40240020, 0x03020700},
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{ 0x40504084, 0x00000006 }, { 0x40500040, 0x00000000 },
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{ 0x40100030, 0x00000001 }, { 0x40241020, 0x00000001 },
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{ 0x40240030, 0x00000004 }, { 0x40240020, 0x03020700 },
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};
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#endif
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int aicwifi_sys_config_8800d80(struct aic_sdio_dev *sdiodev)
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{
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#ifdef CONFIG_OOB
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int ret, cnt;
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int ret, cnt;
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int gpiocfg_num = sizeof(gpio_cfg_tbl_8800d40d80) / sizeof(u32) / 2;
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for (cnt = 0; cnt < gpiocfg_num; cnt++) {
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ret = rwnx_send_dbg_mem_write_req(sdiodev, gpio_cfg_tbl_8800d40d80[cnt][0], gpio_cfg_tbl_8800d40d80[cnt][1]);
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ret = rwnx_send_dbg_mem_write_req(
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sdiodev, gpio_cfg_tbl_8800d40d80[cnt][0],
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gpio_cfg_tbl_8800d40d80[cnt][1]);
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if (ret) {
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printk("%x write fail: %d\n", gpio_cfg_tbl_8800d40d80[cnt][0], ret);
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printk("%x write fail: %d\n",
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gpio_cfg_tbl_8800d40d80[cnt][0], ret);
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return ret;
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}
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}
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@@ -109,19 +126,19 @@ int aicwifi_sys_config_8800d80(struct aic_sdio_dev *sdiodev)
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return 0;
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}
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#define NEW_PATCH_BUFFER_MAP 1
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#define NEW_PATCH_BUFFER_MAP 1
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int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
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{
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const u32 rd_patch_addr = RAM_FMAC_FW_ADDR + 0x0198;
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u32 aic_patch_addr;
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u32 config_base, aic_patch_str_base;
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#if (NEW_PATCH_BUFFER_MAP)
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#if (NEW_PATCH_BUFFER_MAP)
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u32 patch_buff_addr, patch_buff_base, rd_version_addr, rd_version_val;
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#endif
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#endif
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uint32_t start_addr = 0x0016F800;
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u32 patch_addr = start_addr;
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u32 patch_cnt = sizeof(patch_tbl_8800d80)/sizeof(u32)/2;
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u32 patch_cnt = sizeof(patch_tbl_8800d80) / sizeof(u32) / 2;
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struct dbg_mem_read_cfm rd_patch_addr_cfm;
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int ret = 0;
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int cnt = 0;
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@@ -129,13 +146,15 @@ int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
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int adap_patch_cnt = 0;
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if (adap_test) {
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printk("%s for adaptivity test \r\n", __func__);
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adap_patch_cnt = sizeof(adaptivity_patch_tbl_8800d80)/sizeof(u32)/2;
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printk("%s for adaptivity test \r\n", __func__);
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adap_patch_cnt =
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sizeof(adaptivity_patch_tbl_8800d80) / sizeof(u32) / 2;
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}
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aic_patch_addr = rd_patch_addr + 8;
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ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_patch_addr, &rd_patch_addr_cfm);
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ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_patch_addr,
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&rd_patch_addr_cfm);
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if (ret) {
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printk("patch rd fail\n");
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return ret;
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@@ -143,16 +162,18 @@ int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
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config_base = rd_patch_addr_cfm.memdata;
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ret = rwnx_send_dbg_mem_read_req(sdiodev, aic_patch_addr, &rd_patch_addr_cfm);
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ret = rwnx_send_dbg_mem_read_req(sdiodev, aic_patch_addr,
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&rd_patch_addr_cfm);
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if (ret) {
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printk("patch str rd fail\n");
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return ret;
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}
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aic_patch_str_base = rd_patch_addr_cfm.memdata;
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#if (NEW_PATCH_BUFFER_MAP)
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#if (NEW_PATCH_BUFFER_MAP)
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rd_version_addr = RAM_FMAC_FW_ADDR + 0x01C;
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if ((ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_version_addr, &rd_patch_addr_cfm))) {
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if ((ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_version_addr,
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&rd_patch_addr_cfm))) {
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printk("version val[0x%x] rd fail: %d\n", rd_version_addr, ret);
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return ret;
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}
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@@ -161,7 +182,8 @@ int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
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sdiodev->fw_version_uint = rd_version_val;
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if (rd_version_val > 0x06090100) {
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patch_buff_addr = rd_patch_addr + 12;
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ret = rwnx_send_dbg_mem_read_req(sdiodev, patch_buff_addr, &rd_patch_addr_cfm);
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ret = rwnx_send_dbg_mem_read_req(sdiodev, patch_buff_addr,
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&rd_patch_addr_cfm);
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if (ret) {
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printk("patch buf rd fail\n");
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return ret;
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@@ -169,84 +191,104 @@ int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
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patch_buff_base = rd_patch_addr_cfm.memdata;
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patch_addr = start_addr = patch_buff_base;
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}
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#endif
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#endif
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num), AIC_PATCH_MAGIG_NUM);
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num),
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AIC_PATCH_MAGIG_NUM);
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if (ret) {
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printk("0x%x write fail\n", AIC_PATCH_ADDR(magic_num));
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num_2), AIC_PATCH_MAGIG_NUM_2);
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num_2),
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AIC_PATCH_MAGIG_NUM_2);
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if (ret) {
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printk("0x%x write fail\n", AIC_PATCH_ADDR(magic_num_2));
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_start), patch_addr);
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_start),
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patch_addr);
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if (ret) {
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printk("0x%x write fail\n", AIC_PATCH_ADDR(pair_start));
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return ret;
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}
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|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_count), patch_cnt + adap_patch_cnt);
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_count),
|
||||
patch_cnt + adap_patch_cnt);
|
||||
if (ret) {
|
||||
printk("0x%x write fail\n", AIC_PATCH_ADDR(pair_count));
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (cnt = 0; cnt < patch_cnt; cnt++) {
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt, patch_tbl_8800d80[cnt][0]+config_base);
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr + 8 * cnt,
|
||||
patch_tbl_8800d80[cnt][0] +
|
||||
config_base);
|
||||
if (ret) {
|
||||
printk("%x write fail\n", start_addr+8*cnt);
|
||||
printk("%x write fail\n", start_addr + 8 * cnt);
|
||||
return ret;
|
||||
}
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt+4, patch_tbl_8800d80[cnt][1]);
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev,
|
||||
start_addr + 8 * cnt + 4,
|
||||
patch_tbl_8800d80[cnt][1]);
|
||||
if (ret) {
|
||||
printk("%x write fail\n", start_addr+8*cnt+4);
|
||||
printk("%x write fail\n", start_addr + 8 * cnt + 4);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (adap_test){
|
||||
if (adap_test) {
|
||||
int tmp_cnt = patch_cnt + adap_patch_cnt;
|
||||
for (cnt = patch_cnt; cnt < tmp_cnt; cnt++) {
|
||||
int tbl_idx = cnt - patch_cnt;
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt, adaptivity_patch_tbl_8800d80[tbl_idx][0]+config_base);
|
||||
if(ret) {
|
||||
printk("%x write fail\n", start_addr+8*cnt);
|
||||
ret = rwnx_send_dbg_mem_write_req(
|
||||
sdiodev, start_addr + 8 * cnt,
|
||||
adaptivity_patch_tbl_8800d80[tbl_idx][0] +
|
||||
config_base);
|
||||
if (ret) {
|
||||
printk("%x write fail\n", start_addr + 8 * cnt);
|
||||
return ret;
|
||||
}
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt+4, adaptivity_patch_tbl_8800d80[tbl_idx][1]);
|
||||
if(ret) {
|
||||
printk("%x write fail\n", start_addr+8*cnt+4);
|
||||
ret = rwnx_send_dbg_mem_write_req(
|
||||
sdiodev, start_addr + 8 * cnt + 4,
|
||||
adaptivity_patch_tbl_8800d80[tbl_idx][1]);
|
||||
if (ret) {
|
||||
printk("%x write fail\n",
|
||||
start_addr + 8 * cnt + 4);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[0]), 0);
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev,
|
||||
AIC_PATCH_ADDR(block_size[0]), 0);
|
||||
if (ret) {
|
||||
printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[0]), ret);
|
||||
printk("block_size[0x%x] write fail: %d\n",
|
||||
AIC_PATCH_ADDR(block_size[0]), ret);
|
||||
return ret;
|
||||
}
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[1]), 0);
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev,
|
||||
AIC_PATCH_ADDR(block_size[1]), 0);
|
||||
if (ret) {
|
||||
printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[1]), ret);
|
||||
printk("block_size[0x%x] write fail: %d\n",
|
||||
AIC_PATCH_ADDR(block_size[1]), ret);
|
||||
return ret;
|
||||
}
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[2]), 0);
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev,
|
||||
AIC_PATCH_ADDR(block_size[2]), 0);
|
||||
if (ret) {
|
||||
printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[2]), ret);
|
||||
printk("block_size[0x%x] write fail: %d\n",
|
||||
AIC_PATCH_ADDR(block_size[2]), ret);
|
||||
return ret;
|
||||
}
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[3]), 0);
|
||||
ret = rwnx_send_dbg_mem_write_req(sdiodev,
|
||||
AIC_PATCH_ADDR(block_size[3]), 0);
|
||||
if (ret) {
|
||||
printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[3]), ret);
|
||||
printk("block_size[0x%x] write fail: %d\n",
|
||||
AIC_PATCH_ADDR(block_size[3]), ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -17,8 +17,4 @@ int aicbsp_system_config_8800d80(struct aic_sdio_dev *sdiodev);
|
||||
int aicwifi_sys_config_8800d80(struct aic_sdio_dev *sdiodev);
|
||||
int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -18,23 +18,26 @@ extern u8 chip_sub_id;
|
||||
extern u8 chip_mcu_id;
|
||||
#define FW_PATH_MAX_LEN 200
|
||||
|
||||
void aicwf_patch_config_8800dc(struct aic_sdio_dev *rwnx_hw);
|
||||
void aicwf_patch_config_8800dc(struct aic_sdio_dev *rwnx_hw);
|
||||
void system_config_8800dc(struct aic_sdio_dev *rwnx_hw);
|
||||
int aicwf_misc_ram_init_8800dc(struct aic_sdio_dev *sdiodev);
|
||||
|
||||
#ifdef CONFIG_DPD
|
||||
int aicwf_dpd_calib_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_t *dpd_res);
|
||||
int aicwf_dpd_result_apply_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_t *dpd_res);
|
||||
int aicwf_dpd_calib_8800dc(struct aic_sdio_dev *sdiodev,
|
||||
rf_misc_ram_lite_t *dpd_res);
|
||||
int aicwf_dpd_result_apply_8800dc(struct aic_sdio_dev *sdiodev,
|
||||
rf_misc_ram_lite_t *dpd_res);
|
||||
#ifndef CONFIG_FORCE_DPD_CALIB
|
||||
int aicwf_dpd_result_load_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_t *dpd_res);
|
||||
int aicwf_dpd_result_load_8800dc(struct aic_sdio_dev *sdiodev,
|
||||
rf_misc_ram_lite_t *dpd_res);
|
||||
int aicwf_dpd_result_write_8800dc(void *buf, int buf_len);
|
||||
#endif/* !CONFIG_FORCE_DPD_CALIB */
|
||||
#endif /* !CONFIG_FORCE_DPD_CALIB */
|
||||
#endif
|
||||
#ifdef CONFIG_LOFT_CALIB
|
||||
int aicwf_loft_calib_8800dc(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_loft_calib_8800dc(struct aic_sdio_dev *sdiodev,
|
||||
rf_misc_ram_lite_t *loft_res);
|
||||
int aicwf_loft_result_apply_8800dc(struct aic_sdio_dev *sdiodev,
|
||||
rf_misc_ram_lite_t *loft_res);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -16,76 +16,69 @@
|
||||
#include <linux/module.h>
|
||||
#include "aic_bsp_export.h"
|
||||
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS 3000//500//300
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS 6000 //500//300
|
||||
|
||||
#define RWNX_CMD_FLAG_NONBLOCK BIT(0)
|
||||
#define RWNX_CMD_FLAG_REQ_CFM BIT(1)
|
||||
#define RWNX_CMD_FLAG_WAIT_PUSH BIT(2)
|
||||
#define RWNX_CMD_FLAG_WAIT_ACK BIT(3)
|
||||
#define RWNX_CMD_FLAG_WAIT_CFM BIT(4)
|
||||
#define RWNX_CMD_FLAG_DONE BIT(5)
|
||||
#define RWNX_CMD_FLAG_NONBLOCK BIT(0)
|
||||
#define RWNX_CMD_FLAG_REQ_CFM BIT(1)
|
||||
#define RWNX_CMD_FLAG_WAIT_PUSH BIT(2)
|
||||
#define RWNX_CMD_FLAG_WAIT_ACK BIT(3)
|
||||
#define RWNX_CMD_FLAG_WAIT_CFM BIT(4)
|
||||
#define RWNX_CMD_FLAG_DONE BIT(5)
|
||||
/* ATM IPC design makes it possible to get the CFM before the ACK,
|
||||
* otherwise this could have simply been a state enum */
|
||||
#define RWNX_CMD_WAIT_COMPLETE(flags) \
|
||||
#define RWNX_CMD_WAIT_COMPLETE(flags) \
|
||||
(!(flags & (RWNX_CMD_FLAG_WAIT_ACK | RWNX_CMD_FLAG_WAIT_CFM)))
|
||||
|
||||
#define RWNX_CMD_MAX_QUEUED 8
|
||||
#define RWNX_CMD_MAX_QUEUED 8
|
||||
|
||||
#define IPC_E2A_MSG_PARAM_SIZE 256
|
||||
|
||||
#define RWNX_FN_ENTRY_STR ">>> %s()\n", __func__
|
||||
|
||||
/* message levels */
|
||||
#define LOGERROR 0x0001
|
||||
#define LOGINFO 0x0002
|
||||
#define LOGTRACE 0x0004
|
||||
#define LOGDEBUG 0x0008
|
||||
#define LOGDATA 0x0010
|
||||
#define LOGERROR 0x0001
|
||||
#define LOGINFO 0x0002
|
||||
#define LOGTRACE 0x0004
|
||||
#define LOGDEBUG 0x0008
|
||||
#define LOGDATA 0x0010
|
||||
|
||||
extern int aicwf_dbg_level_bsp;
|
||||
|
||||
#define AICWF_LOG "AICWFDBG("
|
||||
#define AICWF_LOG "AICWFDBG("
|
||||
|
||||
#ifdef DEBUG
|
||||
#define AICWFDBG(level, args, arg...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level_bsp & level) { \
|
||||
printk(AICWF_LOG#level")\t" args, ##arg); \
|
||||
} \
|
||||
} while (0)
|
||||
#define AICWFDBG(level, args, arg...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level_bsp & level) { \
|
||||
printk(AICWF_LOG #level ")\t" args, ##arg); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define RWNX_DBG(fmt, ...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level_bsp & LOGTRACE) { \
|
||||
printk(AICWF_LOG"LOGTRACE)\t"fmt , ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
#define RWNX_DBG(fmt, ...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level_bsp & LOGTRACE) { \
|
||||
printk(AICWF_LOG "LOGTRACE)\t" fmt, ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#else
|
||||
|
||||
#define AICWFDBG(level, args, arg...)
|
||||
#define RWNX_DBG(fmt, ...)
|
||||
|
||||
#endif
|
||||
/// Message structure for MSGs from Emb to App
|
||||
struct ipc_e2a_msg {
|
||||
u16 id; ///< Message id.
|
||||
u16 id; ///< Message id.
|
||||
u16 dummy_dest_id;
|
||||
u16 dummy_src_id;
|
||||
u16 param_len; ///< Parameter embedded struct length.
|
||||
u32 pattern; ///< Used to stamp a valid MSG buffer
|
||||
u32 param[IPC_E2A_MSG_PARAM_SIZE]; ///< Parameter embedded struct. Must be word-aligned.
|
||||
u16 param_len; ///< Parameter embedded struct length.
|
||||
u32 pattern; ///< Used to stamp a valid MSG buffer
|
||||
u32 param[IPC_E2A_MSG_PARAM_SIZE]; ///< Parameter embedded struct. Must be word-aligned.
|
||||
};
|
||||
|
||||
typedef u16 lmac_msg_id_t;
|
||||
typedef u16 lmac_task_id_t;
|
||||
|
||||
struct lmac_msg {
|
||||
lmac_msg_id_t id; ///< Message id.
|
||||
lmac_task_id_t dest_id; ///< Destination kernel identifier.
|
||||
lmac_task_id_t src_id; ///< Source kernel identifier.
|
||||
u16 param_len; ///< Parameter embedded struct length.
|
||||
u32 param[]; ///< Parameter embedded struct. Must be word-aligned.
|
||||
lmac_msg_id_t id; ///< Message id.
|
||||
lmac_task_id_t dest_id; ///< Destination kernel identifier.
|
||||
lmac_task_id_t src_id; ///< Source kernel identifier.
|
||||
u16 param_len; ///< Parameter embedded struct length.
|
||||
u32 param[]; ///< Parameter embedded struct. Must be word-aligned.
|
||||
};
|
||||
|
||||
#define rwnx_cmd_e2amsg ipc_e2a_msg
|
||||
@@ -95,8 +88,8 @@ struct lmac_msg {
|
||||
|
||||
static inline void put_u16(u8 *buf, u16 data)
|
||||
{
|
||||
buf[0] = (u8)(data&0x00ff);
|
||||
buf[1] = (u8)((data >> 8)&0x00ff);
|
||||
buf[0] = (u8)(data & 0x00ff);
|
||||
buf[1] = (u8)((data >> 8) & 0x00ff);
|
||||
}
|
||||
|
||||
enum rwnx_cmd_mgr_state {
|
||||
@@ -132,9 +125,10 @@ struct rwnx_cmd_mgr {
|
||||
|
||||
struct list_head cmds;
|
||||
|
||||
int (*queue)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*llind)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*msgind)(struct rwnx_cmd_mgr *, struct rwnx_cmd_e2amsg *, msg_cb_fct);
|
||||
int (*queue)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*llind)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*msgind)(struct rwnx_cmd_mgr *, struct rwnx_cmd_e2amsg *,
|
||||
msg_cb_fct);
|
||||
void (*print)(struct rwnx_cmd_mgr *);
|
||||
void (*drain)(struct rwnx_cmd_mgr *);
|
||||
|
||||
@@ -144,11 +138,12 @@ struct rwnx_cmd_mgr {
|
||||
|
||||
void rwnx_cmd_mgr_init(struct rwnx_cmd_mgr *cmd_mgr);
|
||||
void rwnx_cmd_mgr_deinit(struct rwnx_cmd_mgr *cmd_mgr);
|
||||
int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd);
|
||||
int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr,
|
||||
struct rwnx_cmd *cmd);
|
||||
void rwnx_set_cmd_tx(void *dev, struct lmac_msg *msg, uint len);
|
||||
|
||||
enum {
|
||||
TASK_NONE = (u8) -1,
|
||||
TASK_NONE = (u8)-1,
|
||||
|
||||
// MAC Management task.
|
||||
TASK_MM = 0,
|
||||
@@ -182,7 +177,7 @@ enum {
|
||||
|
||||
#define LMAC_FIRST_MSG(task) ((lmac_msg_id_t)((task) << 10))
|
||||
#define DRV_TASK_ID 100
|
||||
#define MSG_I(msg) ((msg) & ((1<<10)-1))
|
||||
#define MSG_I(msg) ((msg) & ((1 << 10) - 1))
|
||||
#define MSG_T(msg) ((lmac_task_id_t)((msg) >> 10))
|
||||
|
||||
enum dbg_msg_tag {
|
||||
@@ -238,25 +233,23 @@ enum dbg_msg_tag {
|
||||
DBG_GPIO_WRITE_REQ,
|
||||
DBG_GPIO_WRITE_CFM,
|
||||
|
||||
|
||||
/// Max number of Debug messages
|
||||
DBG_MAX,
|
||||
};
|
||||
|
||||
#if !defined(CONFIG_M2D_OTA_LZMA_SUPPORT)
|
||||
#define FW_M2D_OTA_NAME "m2d_ota.bin"
|
||||
#define FW_M2D_OTA_NAME "m2d_ota.bin"
|
||||
#else
|
||||
#define FW_M2D_OTA_NAME "m2d_ota_lzma.bin"
|
||||
#define FW_M2D_OTA_NAME "m2d_ota_lzma.bin"
|
||||
#endif
|
||||
|
||||
enum {
|
||||
HOST_START_APP_AUTO = 1,
|
||||
HOST_START_APP_CUSTOM,
|
||||
HOST_START_APP_FNCALL = 4,
|
||||
HOST_START_APP_DUMMY = 5,
|
||||
HOST_START_APP_DUMMY = 5,
|
||||
};
|
||||
|
||||
|
||||
struct dbg_mem_block_write_req {
|
||||
u32 memaddr;
|
||||
u32 memsize;
|
||||
@@ -317,10 +310,9 @@ struct dbg_start_app_cfm {
|
||||
|
||||
int aicwf_plat_patch_load_8800dc(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_plat_rftest_load_8800dc(struct aic_sdio_dev *sdiodev);
|
||||
#ifdef CONFIG_DPD
|
||||
int aicwf_misc_ram_valid_check_8800dc(struct aic_sdio_dev *sdiodev, int *valid_out);
|
||||
#endif
|
||||
#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
|
||||
int aicwf_misc_ram_valid_check_8800dc(struct aic_sdio_dev *sdiodev,
|
||||
int *valid_out);
|
||||
int aicwf_plat_calib_load_8800dc(struct aic_sdio_dev *sdiodev);
|
||||
#endif
|
||||
|
||||
@@ -328,113 +320,128 @@ int rwnx_load_firmware(u32 **fw_buf, const char *name, struct device *device);
|
||||
int aicwf_patch_table_load(struct aic_sdio_dev *rwnx_hw, char *filename);
|
||||
|
||||
int rwnx_send_dbg_mem_read_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
|
||||
struct dbg_mem_read_cfm *cfm);
|
||||
int rwnx_send_dbg_mem_block_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
|
||||
u32 mem_size, u32 *mem_data);
|
||||
int rwnx_send_dbg_mem_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr, u32 mem_data);
|
||||
struct dbg_mem_read_cfm *cfm);
|
||||
int rwnx_send_dbg_mem_block_write_req(struct aic_sdio_dev *sdiodev,
|
||||
u32 mem_addr, u32 mem_size,
|
||||
u32 *mem_data);
|
||||
int rwnx_send_dbg_mem_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
|
||||
u32 mem_data);
|
||||
int rwnx_send_dbg_mem_mask_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
|
||||
u32 mem_mask, u32 mem_data);
|
||||
int rwnx_send_dbg_start_app_req(struct aic_sdio_dev *sdiodev, u32 boot_addr, u32 boot_type, struct dbg_start_app_cfm *start_app_cfm);
|
||||
u32 mem_mask, u32 mem_data);
|
||||
int rwnx_send_dbg_start_app_req(struct aic_sdio_dev *sdiodev, u32 boot_addr,
|
||||
u32 boot_type,
|
||||
struct dbg_start_app_cfm *start_app_cfm);
|
||||
|
||||
int rwnx_plat_bin_fw_upload_android(struct aic_sdio_dev *sdiodev, u32 fw_addr, const char *filename);
|
||||
int rwnx_plat_bin_fw_upload_android(struct aic_sdio_dev *sdiodev, u32 fw_addr,
|
||||
const char *filename);
|
||||
|
||||
void rwnx_rx_handle_msg(struct aic_sdio_dev *sdiodev, struct ipc_e2a_msg *msg);
|
||||
int aicbsp_platform_init(struct aic_sdio_dev *sdiodev);
|
||||
void aicbsp_platform_deinit(struct aic_sdio_dev *sdiodev);
|
||||
int aicbsp_driver_fw_init(struct aic_sdio_dev *sdiodev);
|
||||
#if (defined(CONFIG_DPD) && !defined(CONFIG_FORCE_DPD_CALIB))
|
||||
int is_file_exist(char* name);
|
||||
int is_file_exist(char *name);
|
||||
#endif
|
||||
int aicbsp_resv_mem_init(void);
|
||||
int aicbsp_resv_mem_deinit(void);
|
||||
|
||||
#define AICBSP_FW_PATH CONFIG_AIC_FW_PATH
|
||||
#define AICBSP_FW_PATH_MAX 200
|
||||
#define AICBSP_FW_PATH CONFIG_AIC_FW_PATH
|
||||
#define AICBSP_FW_PATH_MAX 200
|
||||
|
||||
#define RAM_FMAC_FW_ADDR 0x00120000
|
||||
#define FW_RAM_ADID_BASE_ADDR 0x00161928
|
||||
#define FW_RAM_ADID_BASE_ADDR_U03 0x00161928
|
||||
#define FW_RAM_PATCH_BASE_ADDR 0x00100000
|
||||
#define RAM_8800DC_U01_ADID_ADDR 0x00101788
|
||||
#define RAM_8800DC_U02_ADID_ADDR 0x001017d8
|
||||
#define RAM_8800DC_FW_PATCH_ADDR 0x00184000
|
||||
#define FW_RESET_START_ADDR 0x40500128
|
||||
#define FW_RESET_START_VAL 0x40
|
||||
#define FW_ADID_FLAG_ADDR 0x40500150
|
||||
#define FW_ADID_FLAG_VAL 0x01
|
||||
#define FW_RAM_ADID_BASE_ADDR_8800D80 0x002017E0
|
||||
#define FW_RAM_PATCH_BASE_ADDR_8800D80 0x0020B2B0
|
||||
#define FW_RAM_ADID_BASE_ADDR_8800D80_U02 0x00201940
|
||||
#define FW_RAM_PATCH_BASE_ADDR_8800D80_U02 0x0020b43c
|
||||
|
||||
#define AICBT_PT_TAG "AICBT_PT_TAG"
|
||||
#define RAM_FMAC_FW_ADDR 0x00120000
|
||||
#define RAM_FMAC_FW_PATCH_ADDR 0x00190000
|
||||
#define FW_RAM_ADID_BASE_ADDR 0x00161928
|
||||
#define FW_RAM_ADID_BASE_ADDR_U03 0x00161928
|
||||
#define FW_RAM_PATCH_BASE_ADDR 0x00100000
|
||||
#define RAM_8800DC_U01_ADID_ADDR 0x00101788
|
||||
#define RAM_8800DC_U02_ADID_ADDR 0x001017d8
|
||||
#define RAM_8800DC_FW_PATCH_ADDR 0x00184000
|
||||
#define FW_RESET_START_ADDR 0x40500128
|
||||
#define FW_RESET_START_VAL 0x40
|
||||
#define FW_ADID_FLAG_ADDR 0x40500150
|
||||
#define FW_ADID_FLAG_VAL 0x01
|
||||
#define FW_RAM_ADID_BASE_ADDR_8800D80 0x002017E0
|
||||
#define FW_RAM_PATCH_BASE_ADDR_8800D80 0x0020B2B0
|
||||
#define FW_RAM_ADID_BASE_ADDR_8800D80_U02 0x00201940
|
||||
#define FW_RAM_PATCH_BASE_ADDR_8800D80_U02 0x0020b43c
|
||||
|
||||
#define AICBT_PT_TAG "AICBT_PT_TAG"
|
||||
|
||||
/*****************************************************************************
|
||||
* Addresses within RWNX_ADDR_CPU
|
||||
*****************************************************************************/
|
||||
#define RAM_LMAC_FW_ADDR 0x00150000
|
||||
#define RAM_LMAC_FW_ADDR 0x00150000
|
||||
|
||||
#define ROM_FMAC_FW_ADDR 0x00010000
|
||||
#define ROM_FMAC_PATCH_ADDR 0x00180000
|
||||
#define ROM_FMAC_FW_ADDR 0x00010000
|
||||
#define ROM_FMAC_PATCH_ADDR 0x00180000
|
||||
|
||||
#define RWNX_MAC_CALIB_BASE_NAME_8800DC "fmacfw_calib_8800dc"
|
||||
#define RWNX_MAC_CALIB_NAME_8800DC_U02 RWNX_MAC_CALIB_BASE_NAME_8800DC"_u02.bin"
|
||||
#define RAM_FMAC_FW_PATCH_NAME "fmacfw_patch.bin"
|
||||
#define RWNX_MAC_CALIB_BASE_NAME_8800DC "fmacfw_calib_8800dc"
|
||||
#define RWNX_MAC_CALIB_NAME_8800DC_U02 \
|
||||
RWNX_MAC_CALIB_BASE_NAME_8800DC "_u02.bin"
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
#define RWNX_MAC_CALIB_NAME_8800DC_H_U02 RWNX_MAC_CALIB_BASE_NAME_8800DC"_hbt_u02.bin"
|
||||
#define RWNX_MAC_CALIB_NAME_8800DC_H_U02 \
|
||||
RWNX_MAC_CALIB_BASE_NAME_8800DC "_hbt_u02.bin"
|
||||
#else
|
||||
#define RWNX_MAC_CALIB_NAME_8800DC_H_U02 RWNX_MAC_CALIB_BASE_NAME_8800DC"_h_u02.bin"
|
||||
#define RWNX_MAC_CALIB_NAME_8800DC_H_U02 \
|
||||
RWNX_MAC_CALIB_BASE_NAME_8800DC "_h_u02.bin"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
|
||||
#define ROM_FMAC_CALIB_ADDR 0x00130000
|
||||
#define ROM_FMAC_CALIB_ADDR 0x00130000
|
||||
#endif
|
||||
#ifdef CONFIG_DPD
|
||||
#ifndef CONFIG_FORCE_DPD_CALIB
|
||||
#define FW_DPDRESULT_NAME_8800DC "aic_dpdresult_lite_8800dc.bin"
|
||||
#define FW_DPDRESULT_NAME_8800DC "aic_dpdresult_lite_8800dc.bin"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define RWNX_MAC_FW_RF_BASE_NAME_8800DC "lmacfw_rf_8800dc.bin"
|
||||
#define RWNX_MAC_FW_RF_BASE_NAME_8800DC "lmacfw_rf_8800dc.bin"
|
||||
|
||||
#ifdef CONFIG_FOR_IPCOM
|
||||
#define RWNX_MAC_PATCH_BASE_NAME_8800DC "fmacfw_patch_8800dc_ipc"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC RWNX_MAC_PATCH_BASE_NAME_8800DC".bin"
|
||||
#define RWNX_MAC_PATCH_BASE_NAME_8800DC "fmacfw_patch_8800dc_ipc"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC RWNX_MAC_PATCH_BASE_NAME_8800DC ".bin"
|
||||
#else
|
||||
#define RWNX_MAC_PATCH_BASE_NAME_8800DC "fmacfw_patch_8800dc"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC RWNX_MAC_PATCH_BASE_NAME_8800DC".bin"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_u02.bin"
|
||||
#define RWNX_MAC_PATCH_BASE_NAME_8800DC "fmacfw_patch_8800dc"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC RWNX_MAC_PATCH_BASE_NAME_8800DC ".bin"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC_U02 \
|
||||
RWNX_MAC_PATCH_BASE_NAME_8800DC "_u02.bin"
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC_H_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_hbt_u02.bin"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC_H_U02 \
|
||||
RWNX_MAC_PATCH_BASE_NAME_8800DC "_hbt_u02.bin"
|
||||
#else
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC_H_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_h_u02.bin"
|
||||
#define RWNX_MAC_PATCH_NAME2_8800DC_H_U02 \
|
||||
RWNX_MAC_PATCH_BASE_NAME_8800DC "_h_u02.bin"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define RWNX_MAC_PATCH_TABLE_NAME_8800DC "fmacfw_patch_tbl_8800dc"
|
||||
#define RWNX_MAC_PATCH_TABLE_8800DC RWNX_MAC_PATCH_TABLE_NAME_8800DC ".bin"
|
||||
#define RWNX_MAC_PATCH_TABLE_8800DC_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_u02.bin"
|
||||
#define RWNX_MAC_PATCH_TABLE_8800DC_U02 \
|
||||
RWNX_MAC_PATCH_TABLE_NAME_8800DC "_u02.bin"
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
#define RWNX_MAC_PATCH_TABLE_8800DC_H_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_hbt_u02.bin"
|
||||
#define RWNX_MAC_PATCH_TABLE_8800DC_H_U02 \
|
||||
RWNX_MAC_PATCH_TABLE_NAME_8800DC "_hbt_u02.bin"
|
||||
#else
|
||||
#define RWNX_MAC_PATCH_TABLE_8800DC_H_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_h_u02.bin"
|
||||
#define RWNX_MAC_PATCH_TABLE_8800DC_H_U02 \
|
||||
RWNX_MAC_PATCH_TABLE_NAME_8800DC "_h_u02.bin"
|
||||
#endif
|
||||
|
||||
#define RWNX_MAC_RF_PATCH_BASE_NAME_8800DC "fmacfw_rf_patch_8800dc"
|
||||
#define RWNX_MAC_RF_PATCH_NAME_8800DC RWNX_MAC_RF_PATCH_BASE_NAME_8800DC".bin"
|
||||
#define FW_USERCONFIG_NAME_8800DC "aic_userconfig_8800dc.txt"
|
||||
#define RWNX_MAC_RF_PATCH_BASE_NAME_8800DC "fmacfw_rf_patch_8800dc"
|
||||
#define RWNX_MAC_RF_PATCH_NAME_8800DC RWNX_MAC_RF_PATCH_BASE_NAME_8800DC ".bin"
|
||||
#define FW_USERCONFIG_NAME_8800DC "aic_userconfig_8800dc.txt"
|
||||
|
||||
enum {
|
||||
FW_NORMAL_MODE = 0,
|
||||
FW_RFTEST_MODE = 1,
|
||||
FW_BLE_SCAN_WAKEUP_MODE = 2,
|
||||
FW_M2D_OTA_MODE = 3,
|
||||
FW_DPDCALIB_MODE = 4,
|
||||
FW_BLE_SCAN_AD_FILTER_MODE = 5,
|
||||
FW_NORMAL_MODE = 0,
|
||||
FW_RFTEST_MODE = 1,
|
||||
FW_BLE_SCAN_WAKEUP_MODE = 2,
|
||||
FW_M2D_OTA_MODE = 3,
|
||||
FW_DPDCALIB_MODE = 4,
|
||||
FW_BLE_SCAN_AD_FILTER_MODE = 5,
|
||||
};
|
||||
|
||||
enum aicbt_patch_table_type {
|
||||
AICBT_PT_INF = 0x00,
|
||||
AICBT_PT_INF = 0x00,
|
||||
AICBT_PT_TRAP = 0x1,
|
||||
AICBT_PT_B4,
|
||||
AICBT_PT_BTMODE,
|
||||
@@ -454,13 +461,13 @@ enum aicbt_btport_type {
|
||||
* efuse valid and vendor_info will be invalid, even has beed set valid
|
||||
*/
|
||||
enum aicbt_btmode_type {
|
||||
AICBT_BTMODE_BT_ONLY_SW = 0x0, // bt only mode with switch
|
||||
AICBT_BTMODE_BT_WIFI_COMBO, // wifi/bt combo mode
|
||||
AICBT_BTMODE_BT_ONLY, // bt only mode without switch
|
||||
AICBT_BTMODE_BT_ONLY_TEST, // bt only test mode
|
||||
AICBT_BTMODE_BT_WIFI_COMBO_TEST, // wifi/bt combo test mode
|
||||
AICBT_BTMODE_BT_ONLY_COANT, // bt only mode with no external switch
|
||||
AICBT_MODE_NULL = 0xFF, // invalid value
|
||||
AICBT_BTMODE_BT_ONLY_SW = 0x0, // bt only mode with switch
|
||||
AICBT_BTMODE_BT_WIFI_COMBO, // wifi/bt combo mode
|
||||
AICBT_BTMODE_BT_ONLY, // bt only mode without switch
|
||||
AICBT_BTMODE_BT_ONLY_TEST, // bt only test mode
|
||||
AICBT_BTMODE_BT_WIFI_COMBO_TEST, // wifi/bt combo test mode
|
||||
AICBT_BTMODE_BT_ONLY_COANT, // bt only mode with no external switch
|
||||
AICBT_MODE_NULL = 0xFF, // invalid value
|
||||
};
|
||||
|
||||
/* uart_baud
|
||||
@@ -468,15 +475,15 @@ enum aicbt_btmode_type {
|
||||
* otherwise meaningless
|
||||
*/
|
||||
enum aicbt_uart_baud_type {
|
||||
AICBT_UART_BAUD_115200 = 115200,
|
||||
AICBT_UART_BAUD_921600 = 921600,
|
||||
AICBT_UART_BAUD_1_5M = 1500000,
|
||||
AICBT_UART_BAUD_3_25M = 3250000,
|
||||
AICBT_UART_BAUD_115200 = 115200,
|
||||
AICBT_UART_BAUD_921600 = 921600,
|
||||
AICBT_UART_BAUD_1_5M = 1500000,
|
||||
AICBT_UART_BAUD_3_25M = 3250000,
|
||||
};
|
||||
|
||||
enum aicbt_uart_flowctrl_type {
|
||||
AICBT_UART_FLOWCTRL_DISABLE = 0x0, // uart without flow ctrl
|
||||
AICBT_UART_FLOWCTRL_ENABLE, // uart with flow ctrl
|
||||
AICBT_UART_FLOWCTRL_DISABLE = 0x0, // uart without flow ctrl
|
||||
AICBT_UART_FLOWCTRL_ENABLE, // uart with flow ctrl
|
||||
};
|
||||
|
||||
enum aicbsp_cpmode_type {
|
||||
@@ -492,48 +499,50 @@ enum chip_rev {
|
||||
CHIP_REV_U04 = 7,
|
||||
};
|
||||
|
||||
#define AIC_M2D_OTA_INFO_ADDR 0x88000020
|
||||
#define AIC_M2D_OTA_DATA_ADDR 0x88000040
|
||||
#define AIC_M2D_OTA_INFO_ADDR 0x88000020
|
||||
#define AIC_M2D_OTA_DATA_ADDR 0x88000040
|
||||
#if !defined(CONFIG_M2D_OTA_LZMA_SUPPORT)
|
||||
#define AIC_M2D_OTA_FLASH_ADDR 0x08004000
|
||||
#define AIC_M2D_OTA_FLASH_ADDR 0x08004000
|
||||
#define AIC_M2D_OTA_CODE_START_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x0188)
|
||||
#define AIC_M2D_OTA_VER_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x018C)
|
||||
#define AIC_M2D_OTA_VER_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x018C)
|
||||
#else
|
||||
#define AIC_M2D_OTA_FLASH_ADDR 0x08005000
|
||||
#define AIC_M2D_OTA_FLASH_ADDR 0x08005000
|
||||
#define AIC_M2D_OTA_CODE_START_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x1188)
|
||||
#define AIC_M2D_OTA_VER_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x0010)
|
||||
#define AIC_M2D_OTA_VER_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x0010)
|
||||
#endif
|
||||
///aic bt tx pwr lvl :lsb->msb: first byte, min pwr lvl; second byte, max pwr lvl;
|
||||
///pwr lvl:20(min), 30 , 40 , 50 , 60(max)
|
||||
#define AICBT_TXPWR_LVL 0x00006020
|
||||
#define AICBT_TXPWR_LVL_8800dc 0x00006f2f
|
||||
#define AICBT_TXPWR_LVL_8800d80 0x00006f2f
|
||||
#define AICBT_TXPWR_LVL 0x00006020
|
||||
#define AICBT_TXPWR_LVL_8800dc 0x00006f2f
|
||||
#define AICBT_TXPWR_LVL_8800d80 0x00006f2f
|
||||
#define AICBT_TXPWR_LVL_8800d80x2 0x00006f2f
|
||||
|
||||
#define AICBSP_HWINFO_DEFAULT (-1)
|
||||
#define AICBSP_CPMODE_DEFAULT AICBSP_CPMODE_WORK
|
||||
#define AICBSP_FWLOG_EN_DEFAULT 0
|
||||
#define AICBSP_HWINFO_DEFAULT (-1)
|
||||
#define AICBSP_CPMODE_DEFAULT AICBSP_CPMODE_WORK
|
||||
#define AICBSP_FWLOG_EN_DEFAULT 0
|
||||
|
||||
#define AICBT_BTMODE_DEFAULT_8800d80 AICBT_BTMODE_BT_ONLY_COANT
|
||||
#define AICBT_BTMODE_DEFAULT AICBT_BTMODE_BT_ONLY_SW
|
||||
#define AICBT_BTMODE_DEFAULT_8800d80x2 AICBT_BTMODE_BT_ONLY_COANT
|
||||
#define AICBT_BTMODE_DEFAULT_8800d80 AICBT_BTMODE_BT_ONLY_COANT
|
||||
#define AICBT_BTMODE_DEFAULT AICBT_BTMODE_BT_ONLY_SW
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
#define AICBT_BTPORT_DEFAULT AICBT_BTPORT_MB
|
||||
#define AICBT_BTPORT_DEFAULT AICBT_BTPORT_MB
|
||||
#else
|
||||
#define AICBT_BTPORT_DEFAULT AICBT_BTPORT_UART
|
||||
#define AICBT_BTPORT_DEFAULT AICBT_BTPORT_UART
|
||||
#endif
|
||||
#define AICBT_UART_BAUD_DEFAULT AICBT_UART_BAUD_1_5M
|
||||
#define AICBT_UART_FC_DEFAULT AICBT_UART_FLOWCTRL_ENABLE
|
||||
#define AICBT_LPM_ENABLE_DEFAULT 0
|
||||
#define AICBT_TXPWR_LVL_DEFAULT AICBT_TXPWR_LVL
|
||||
#define AICBT_TXPWR_LVL_DEFAULT_8800dc AICBT_TXPWR_LVL_8800dc
|
||||
#define AICBT_UART_BAUD_DEFAULT AICBT_UART_BAUD_1_5M
|
||||
#define AICBT_UART_FC_DEFAULT AICBT_UART_FLOWCTRL_ENABLE
|
||||
#define AICBT_LPM_ENABLE_DEFAULT 0
|
||||
#define AICBT_TXPWR_LVL_DEFAULT AICBT_TXPWR_LVL
|
||||
#define AICBT_TXPWR_LVL_DEFAULT_8800dc AICBT_TXPWR_LVL_8800dc
|
||||
#define AICBT_TXPWR_LVL_DEFAULT_8800d80 AICBT_TXPWR_LVL_8800d80
|
||||
#define AICBT_TXPWR_LVL_DEFAULT_8800d80x2 AICBT_TXPWR_LVL_8800d80x2
|
||||
|
||||
|
||||
#define FEATURE_SDIO_CLOCK 50000000 // 0: default, other: target clock rate
|
||||
#define FEATURE_SDIO_CLOCK_V3 150000000 // 0: default, other: target clock rate
|
||||
#define FEATURE_SDIO_PHASE 2 // 0: default, 2: 180°
|
||||
#define FEATURE_SDIO_CLOCK 50000000 // 0: default, other: target clock rate
|
||||
#define FEATURE_SDIO_CLOCK_V3 150000000 // 0: default, other: target clock rate
|
||||
#define FEATURE_SDIO_PHASE 2 // 0: default, 2: 180°
|
||||
|
||||
struct aicbt_patch_table {
|
||||
char *name;
|
||||
char *name;
|
||||
uint32_t type;
|
||||
uint32_t *data;
|
||||
uint32_t len;
|
||||
@@ -550,15 +559,21 @@ struct aicbt_info_t {
|
||||
};
|
||||
|
||||
struct aicbt_patch_info_t {
|
||||
uint32_t info_len;
|
||||
uint32_t adid_addrinf;
|
||||
uint32_t info_len;
|
||||
//base len start
|
||||
uint32_t adid_addrinf;
|
||||
uint32_t addr_adid;
|
||||
uint32_t patch_addrinf;
|
||||
uint32_t patch_addrinf;
|
||||
uint32_t addr_patch;
|
||||
uint32_t reset_addr;
|
||||
uint32_t reset_val;
|
||||
uint32_t adid_flag_addr;
|
||||
uint32_t adid_flag;
|
||||
//base len end
|
||||
//ext patch nb
|
||||
uint32_t ext_patch_nb_addr;
|
||||
uint32_t ext_patch_nb;
|
||||
uint32_t *ext_patch_param;
|
||||
};
|
||||
|
||||
struct aicbsp_firmware {
|
||||
@@ -567,6 +582,7 @@ struct aicbsp_firmware {
|
||||
const char *bt_patch;
|
||||
const char *bt_table;
|
||||
const char *wl_fw;
|
||||
const char *bt_ext_patch;
|
||||
};
|
||||
|
||||
struct aicbsp_info_t {
|
||||
@@ -589,5 +605,6 @@ extern const struct aicbsp_firmware fw_8800dc_h_u02[];
|
||||
extern const struct aicbsp_firmware fw_8800d80_u01[];
|
||||
extern const struct aicbsp_firmware fw_8800d80_u02[];
|
||||
extern const struct aicbsp_firmware fw_8800d80_h_u02[];
|
||||
extern const struct aicbsp_firmware fw_8800d80x2[];
|
||||
|
||||
#endif
|
||||
|
||||
@@ -24,39 +24,45 @@ struct skb_buff_pool {
|
||||
};
|
||||
|
||||
struct aicbsp_feature_t {
|
||||
int hwinfo;
|
||||
int hwinfo;
|
||||
uint32_t sdio_clock;
|
||||
uint8_t sdio_phase;
|
||||
bool fwlog_en;
|
||||
uint8_t irqf;
|
||||
uint8_t sdio_phase;
|
||||
bool fwlog_en;
|
||||
uint8_t irqf;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DPD
|
||||
#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
|
||||
typedef struct {
|
||||
uint32_t bit_mask[3];
|
||||
uint32_t reserved;
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t dpd_11b[96];
|
||||
uint32_t dpd_low[96];
|
||||
uint32_t idac_11b[48];
|
||||
uint32_t idac_high[48];
|
||||
uint32_t idac_low[48];
|
||||
uint32_t loft_res[18];
|
||||
uint32_t rx_iqim_res[16];
|
||||
uint32_t bit_mask[3];
|
||||
uint32_t reserved;
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t dpd_11b[96];
|
||||
uint32_t dpd_low[96];
|
||||
uint32_t idac_11b[48];
|
||||
uint32_t idac_high[48];
|
||||
uint32_t idac_low[48];
|
||||
uint32_t loft_res[18];
|
||||
uint32_t rx_iqim_res[16];
|
||||
} rf_misc_ram_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t bit_mask[4];
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t loft_res[18];
|
||||
uint32_t bit_mask[4];
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t loft_res[18];
|
||||
} rf_misc_ram_lite_t;
|
||||
|
||||
#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
|
||||
#define DPD_RESULT_SIZE_8800DC sizeof(rf_misc_ram_lite_t)
|
||||
#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
|
||||
#define DPD_RESULT_SIZE_8800DC sizeof(rf_misc_ram_lite_t)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DPD
|
||||
extern rf_misc_ram_lite_t dpd_res;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LOFT_CALIB
|
||||
extern rf_misc_ram_lite_t loft_res_local;
|
||||
#endif
|
||||
|
||||
int aicbsp_set_subsys(int, int);
|
||||
int aicbsp_get_feature(struct aicbsp_feature_t *feature, char *fw_path);
|
||||
struct sk_buff *aicbsp_resv_mem_alloc_skb(unsigned int length, uint32_t id);
|
||||
|
||||
@@ -9,88 +9,79 @@
|
||||
#include "rwnx_version_gen.h"
|
||||
#include "aicwf_txq_prealloc.h"
|
||||
|
||||
#define DRV_DESCRIPTION "AIC BSP"
|
||||
#define DRV_COPYRIGHT "Copyright(c) 2015-2020 AICSemi"
|
||||
#define DRV_AUTHOR "AICSemi"
|
||||
#define DRV_VERS_MOD "1.0"
|
||||
|
||||
#define DRV_DESCRIPTION "AIC BSP"
|
||||
#define DRV_COPYRIGHT "Copyright(c) 2015-2020 AICSemi"
|
||||
#define DRV_AUTHOR "AICSemi"
|
||||
#define DRV_VERS_MOD "1.0"
|
||||
int aicwf_dbg_level_bsp = LOGERROR | LOGINFO | LOGDEBUG | LOGTRACE;
|
||||
|
||||
int aicwf_dbg_level_bsp = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE;
|
||||
struct semaphore aicbsp_probe_semaphore;
|
||||
|
||||
static struct platform_device *aicbsp_pdev;
|
||||
|
||||
const struct aicbsp_firmware *aicbsp_firmware_list = fw_u02;
|
||||
|
||||
const struct aicbsp_firmware fw_u02[] = {
|
||||
[AICBSP_CPMODE_WORK] = {
|
||||
.desc = "normal work mode(sdio u02)",
|
||||
.bt_adid = "fw_adid.bin",
|
||||
.bt_patch = "fw_patch.bin",
|
||||
.bt_table = "fw_patch_table.bin",
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
.wl_fw = "fmacfwbt.bin"
|
||||
#else
|
||||
.wl_fw = "fmacfw.bin"
|
||||
#endif
|
||||
},
|
||||
[AICBSP_CPMODE_TEST] = {
|
||||
.desc = "rf test mode(sdio u02)",
|
||||
.bt_adid = "fw_adid.bin",
|
||||
.bt_patch = "fw_patch.bin",
|
||||
.bt_table = "fw_patch_table.bin",
|
||||
.wl_fw = "fmacfw_rf.bin"
|
||||
[AICBSP_CPMODE_WORK] = { .desc = "normal work mode(sdio u02)",
|
||||
.bt_adid = "fw_adid.bin",
|
||||
.bt_patch = "fw_patch.bin",
|
||||
.bt_table = "fw_patch_table.bin",
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
.wl_fw = "fmacfwbt.bin"
|
||||
#else
|
||||
.wl_fw = "fmacfw.bin"
|
||||
#endif
|
||||
},
|
||||
[AICBSP_CPMODE_TEST] = { .desc = "rf test mode(sdio u02)",
|
||||
.bt_adid = "fw_adid.bin",
|
||||
.bt_patch = "fw_patch.bin",
|
||||
.bt_table = "fw_patch_table.bin",
|
||||
.wl_fw = "fmacfw_rf.bin" },
|
||||
};
|
||||
|
||||
const struct aicbsp_firmware fw_u03[] = {
|
||||
[AICBSP_CPMODE_WORK] = {
|
||||
.desc = "normal work mode(sdio u03/u04)",
|
||||
.bt_adid = "fw_adid_u03.bin",
|
||||
.bt_patch = "fw_patch_u03.bin",
|
||||
.bt_table = "fw_patch_table_u03.bin",
|
||||
#ifdef CONFIG_MCU_MESSAGE
|
||||
.wl_fw = "fmacfw_8800m_custmsg.bin"
|
||||
#elif defined(CONFIG_SDIO_BT)
|
||||
.wl_fw = "fmacfwbt.bin"
|
||||
#else
|
||||
.wl_fw = "fmacfw.bin"
|
||||
#endif
|
||||
[AICBSP_CPMODE_WORK] = { .desc = "normal work mode(sdio u03/u04)",
|
||||
.bt_adid = "fw_adid_u03.bin",
|
||||
.bt_patch = "fw_patch_u03.bin",
|
||||
.bt_table = "fw_patch_table_u03.bin",
|
||||
#ifdef CONFIG_MCU_MESSAGE
|
||||
.wl_fw = "fmacfw_8800m_custmsg.bin"
|
||||
#elif defined(CONFIG_SDIO_BT)
|
||||
.wl_fw = "fmacfwbt.bin"
|
||||
#else
|
||||
.wl_fw = "fmacfw.bin"
|
||||
#endif
|
||||
},
|
||||
|
||||
[AICBSP_CPMODE_TEST] = {
|
||||
.desc = "rf test mode(sdio u03/u04)",
|
||||
.bt_adid = "fw_adid_u03.bin",
|
||||
.bt_patch = "fw_patch_u03.bin",
|
||||
.bt_table = "fw_patch_table_u03.bin",
|
||||
.wl_fw = "fmacfw_rf.bin"
|
||||
},
|
||||
[AICBSP_CPMODE_TEST] = { .desc = "rf test mode(sdio u03/u04)",
|
||||
.bt_adid = "fw_adid_u03.bin",
|
||||
.bt_patch = "fw_patch_u03.bin",
|
||||
.bt_table = "fw_patch_table_u03.bin",
|
||||
.wl_fw = "fmacfw_rf.bin" },
|
||||
};
|
||||
|
||||
const struct aicbsp_firmware fw_8800dc_u01[] = {
|
||||
[AICBSP_CPMODE_WORK] = {
|
||||
.desc = "normal work mode(sdio u01)",
|
||||
.bt_adid = "fw_adid_8800dc.bin",
|
||||
.bt_patch = "fw_patch_8800dc.bin",
|
||||
.bt_table = "fw_patch_table_8800dc.bin",
|
||||
.wl_fw = "fmacfw_8800dc.bin"
|
||||
},
|
||||
[AICBSP_CPMODE_WORK] = { .desc = "normal work mode(sdio u01)",
|
||||
.bt_adid = "fw_adid_8800dc.bin",
|
||||
.bt_patch = "fw_patch_8800dc.bin",
|
||||
.bt_table = "fw_patch_table_8800dc.bin",
|
||||
.wl_fw = "fmacfw_8800dc.bin" },
|
||||
|
||||
[AICBSP_CPMODE_TEST] = {
|
||||
.desc = "rf test mode(sdio u01)",
|
||||
.bt_adid = "fw_adid_8800dc.bin",
|
||||
.bt_patch = "fw_patch_8800dc.bin",
|
||||
.bt_table = "fw_patch_table_8800dc.bin",
|
||||
.wl_fw = "fmacfw_rf_8800dc.bin"
|
||||
},
|
||||
[AICBSP_CPMODE_TEST] = { .desc = "rf test mode(sdio u01)",
|
||||
.bt_adid = "fw_adid_8800dc.bin",
|
||||
.bt_patch = "fw_patch_8800dc.bin",
|
||||
.bt_table = "fw_patch_table_8800dc.bin",
|
||||
.wl_fw = "fmacfw_rf_8800dc.bin" },
|
||||
};
|
||||
|
||||
|
||||
const struct aicbsp_firmware fw_8800dc_u02[] = {
|
||||
[AICBSP_CPMODE_WORK] = {
|
||||
.desc = "normal work mode(8800dc sdio u02)",
|
||||
.bt_adid = "fw_adid_8800dc_u02.bin",
|
||||
.bt_patch = "fw_patch_8800dc_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800dc_u02.bin",
|
||||
.bt_ext_patch = "fw_patch_8800dc_u02_ext",
|
||||
.wl_fw = "fmacfw_patch_8800dc_u02.bin"
|
||||
},
|
||||
|
||||
@@ -99,6 +90,7 @@ const struct aicbsp_firmware fw_8800dc_u02[] = {
|
||||
.bt_adid = "fw_adid_8800dc_u02.bin",
|
||||
.bt_patch = "fw_patch_8800dc_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800dc_u02.bin",
|
||||
.bt_ext_patch = "fw_patch_8800dc_u02_ext",
|
||||
.wl_fw = "lmacfw_rf_8800dc.bin" //u01,u02 lmacfw load same bin
|
||||
},
|
||||
};
|
||||
@@ -109,6 +101,7 @@ const struct aicbsp_firmware fw_8800dc_h_u02[] = {
|
||||
.bt_adid = "fw_adid_8800dc_u02h.bin",
|
||||
.bt_patch = "fw_patch_8800dc_u02h.bin",
|
||||
.bt_table = "fw_patch_table_8800dc_u02h.bin",
|
||||
.bt_ext_patch = "fw_patch_8800dc_u02h_ext",
|
||||
.wl_fw = "fmacfw_patch_8800dc_h_u02.bin"
|
||||
},
|
||||
|
||||
@@ -117,82 +110,98 @@ const struct aicbsp_firmware fw_8800dc_h_u02[] = {
|
||||
.bt_adid = "fw_adid_8800dc_u02h.bin",
|
||||
.bt_patch = "fw_patch_8800dc_u02h.bin",
|
||||
.bt_table = "fw_patch_table_8800dc_u02h.bin",
|
||||
.bt_ext_patch = "fw_patch_8800dc_u02h_ext",
|
||||
.wl_fw = "lmacfw_rf_8800dc.bin" //u01,u02 lmacfw load same bin
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
const struct aicbsp_firmware fw_8800d80_u01[] = {
|
||||
[AICBSP_CPMODE_WORK] = {
|
||||
.desc = "normal work mode(8800d80 sdio u01)",
|
||||
.bt_adid = "fw_adid_8800d80.bin",
|
||||
.bt_patch = "fw_patch_8800d80.bin",
|
||||
.bt_table = "fw_patch_table_8800d80.bin",
|
||||
.wl_fw = "fmacfw_8800d80.bin"
|
||||
},
|
||||
[AICBSP_CPMODE_WORK] = { .desc = "normal work mode(8800d80 sdio u01)",
|
||||
.bt_adid = "fw_adid_8800d80.bin",
|
||||
.bt_patch = "fw_patch_8800d80.bin",
|
||||
.bt_table = "fw_patch_table_8800d80.bin",
|
||||
.wl_fw = "fmacfw_8800d80.bin" },
|
||||
|
||||
[AICBSP_CPMODE_TEST] = {
|
||||
.desc = "rf test mode(8800d80 sdio u01)",
|
||||
.bt_adid = "fw_adid_8800d80.bin",
|
||||
.bt_patch = "fw_patch_8800d80.bin",
|
||||
.bt_table = "fw_patch_table_8800d80.bin",
|
||||
.wl_fw = "lmacfw_rf_8800d80.bin"
|
||||
},
|
||||
[AICBSP_CPMODE_TEST] = { .desc = "rf test mode(8800d80 sdio u01)",
|
||||
.bt_adid = "fw_adid_8800d80.bin",
|
||||
.bt_patch = "fw_patch_8800d80.bin",
|
||||
.bt_table = "fw_patch_table_8800d80.bin",
|
||||
.wl_fw = "lmacfw_rf_8800d80.bin" },
|
||||
};
|
||||
|
||||
const struct aicbsp_firmware fw_8800d80_u02[] = {
|
||||
[AICBSP_CPMODE_WORK] = {
|
||||
.desc = "normal work mode(8800d80 sdio u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
.wl_fw = "fmacfwbt_8800d80_u02.bin"
|
||||
#else
|
||||
.wl_fw = "fmacfw_8800d80_u02.bin"
|
||||
#endif
|
||||
},
|
||||
[AICBSP_CPMODE_WORK] = { .desc = "normal work mode(8800d80 sdio u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
#if defined CONFIG_SDIO_BT
|
||||
.wl_fw = "fmacfwbt_8800d80_u02.bin",
|
||||
#elif defined CONFIG_FOR_IPCAM
|
||||
.wl_fw = "fmacfw_8800d80_u02_ipc.bin",
|
||||
#else
|
||||
.wl_fw = "fmacfw_8800d80_u02.bin",
|
||||
#endif
|
||||
.bt_ext_patch = "fw_patch_8800d80_u02_ext" },
|
||||
|
||||
[AICBSP_CPMODE_TEST] = {
|
||||
.desc = "rf test mode(8800d80 sdio u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
.wl_fw = "lmacfw_rf_8800d80_u02.bin"
|
||||
},
|
||||
[AICBSP_CPMODE_TEST] = { .desc = "rf test mode(8800d80 sdio u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
.wl_fw = "lmacfw_rf_8800d80_u02.bin",
|
||||
.bt_ext_patch = "fw_patch_8800d80_u02_ext" },
|
||||
};
|
||||
|
||||
const struct aicbsp_firmware fw_8800d80_h_u02[] = {
|
||||
[AICBSP_CPMODE_WORK] = {
|
||||
.desc = "normal work mode(8800d80 sdio h_u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
.wl_fw = "fmacfwbt_8800d80_h_u02.bin"
|
||||
#else
|
||||
.wl_fw = "fmacfw_8800d80_h_u02.bin"
|
||||
#endif
|
||||
},
|
||||
[AICBSP_CPMODE_WORK] = { .desc = "normal work mode(8800d80 sdio h_u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
#if defined CONFIG_SDIO_BT
|
||||
.wl_fw = "fmacfwbt_8800d80_h_u02.bin",
|
||||
#elif defined CONFIG_FOR_IPCAM
|
||||
.wl_fw = "fmacfw_8800d80_h_u02_ipc.bin",
|
||||
#else
|
||||
.wl_fw = "fmacfw_8800d80_h_u02.bin",
|
||||
#endif
|
||||
.bt_ext_patch = "fw_patch_8800d80_u02_ext" },
|
||||
|
||||
[AICBSP_CPMODE_TEST] = {
|
||||
.desc = "rf test mode(8800d80 sdio u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
.wl_fw = "lmacfw_rf_8800d80_u02.bin"
|
||||
},
|
||||
[AICBSP_CPMODE_TEST] = { .desc = "rf test mode(8800d80 sdio u02)",
|
||||
.bt_adid = "fw_adid_8800d80_u02.bin",
|
||||
.bt_patch = "fw_patch_8800d80_u02.bin",
|
||||
.bt_table = "fw_patch_table_8800d80_u02.bin",
|
||||
.wl_fw = "lmacfw_rf_8800d80_u02.bin",
|
||||
.bt_ext_patch = "fw_patch_8800d80_u02_ext" },
|
||||
};
|
||||
|
||||
const struct aicbsp_firmware fw_8800d80x2[] = {
|
||||
[AICBSP_CPMODE_WORK] = { .desc = "normal work mode(8800d80x2 sdio)",
|
||||
.bt_adid = "fw_adid_8800d80x2_u05.bin",
|
||||
.bt_patch = "fw_patch_8800d80x2_u05.bin",
|
||||
.bt_table = "fw_patch_table_8800d80x2_u05.bin",
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
.wl_fw = "fmacfwbt_8800d80_h_u02.bin",
|
||||
#else
|
||||
.wl_fw = "fmacfw_8800d80x2.bin",
|
||||
#endif
|
||||
.bt_ext_patch = "fw_patch_8800d80x2_u05_ext" },
|
||||
|
||||
[AICBSP_CPMODE_TEST] = { .desc = "rf test mode(8800d80x2 sdio)",
|
||||
.bt_adid = "fw_adid_8800d80x2_u05.bin",
|
||||
.bt_patch = "fw_patch_8800d80x2_u05.bin",
|
||||
.bt_table = "fw_patch_table_8800d80x2_u05.bin",
|
||||
.wl_fw = "lmacfw_rf_8800d80x2.bin",
|
||||
.bt_ext_patch = "fw_patch_8800d80x2_u05_ext" },
|
||||
};
|
||||
|
||||
struct aicbsp_info_t aicbsp_info = {
|
||||
.hwinfo_r = AICBSP_HWINFO_DEFAULT,
|
||||
.hwinfo = AICBSP_HWINFO_DEFAULT,
|
||||
.cpmode = AICBSP_CPMODE_DEFAULT,
|
||||
.hwinfo = AICBSP_HWINFO_DEFAULT,
|
||||
.cpmode = AICBSP_CPMODE_DEFAULT,
|
||||
.fwlog_en = AICBSP_FWLOG_EN_DEFAULT,
|
||||
#ifdef CONFIG_IRQ_FALL
|
||||
.irqf = 1,
|
||||
.irqf = 1,
|
||||
#else
|
||||
.irqf = 0,
|
||||
.irqf = 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -207,8 +216,8 @@ static struct platform_driver aicbsp_driver = {
|
||||
//.remove = aicbsp_remove,
|
||||
};
|
||||
|
||||
static ssize_t cpmode_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t cpmode_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
ssize_t count = 0;
|
||||
uint8_t i = 0;
|
||||
@@ -217,19 +226,25 @@ static ssize_t cpmode_show(struct device *dev,
|
||||
|
||||
for (i = 0; i < AICBSP_CPMODE_MAX; i++) {
|
||||
if (aicbsp_firmware_list[i].desc)
|
||||
count += sprintf(&buf[count], " %2d: %s\n", i, aicbsp_firmware_list[i].desc);
|
||||
count += sprintf(&buf[count], " %2d: %s\n", i,
|
||||
aicbsp_firmware_list[i].desc);
|
||||
}
|
||||
|
||||
count += sprintf(&buf[count], "Current: %d, firmware info:\n", aicbsp_info.cpmode);
|
||||
count += sprintf(&buf[count], " BT ADID : %s\n", aicbsp_firmware_list[aicbsp_info.cpmode].bt_adid);
|
||||
count += sprintf(&buf[count], " BT PATCH: %s\n", aicbsp_firmware_list[aicbsp_info.cpmode].bt_patch);
|
||||
count += sprintf(&buf[count], " BT TABLE: %s\n", aicbsp_firmware_list[aicbsp_info.cpmode].bt_table);
|
||||
count += sprintf(&buf[count], " WIFI FW : %s\n", aicbsp_firmware_list[aicbsp_info.cpmode].wl_fw);
|
||||
count += sprintf(&buf[count], "Current: %d, firmware info:\n",
|
||||
aicbsp_info.cpmode);
|
||||
count += sprintf(&buf[count], " BT ADID : %s\n",
|
||||
aicbsp_firmware_list[aicbsp_info.cpmode].bt_adid);
|
||||
count += sprintf(&buf[count], " BT PATCH: %s\n",
|
||||
aicbsp_firmware_list[aicbsp_info.cpmode].bt_patch);
|
||||
count += sprintf(&buf[count], " BT TABLE: %s\n",
|
||||
aicbsp_firmware_list[aicbsp_info.cpmode].bt_table);
|
||||
count += sprintf(&buf[count], " WIFI FW : %s\n",
|
||||
aicbsp_firmware_list[aicbsp_info.cpmode].wl_fw);
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t cpmode_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
static ssize_t cpmode_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
unsigned long val;
|
||||
int err = kstrtoul(buf, 0, &val);
|
||||
@@ -242,13 +257,14 @@ static ssize_t cpmode_store(struct device *dev,
|
||||
}
|
||||
|
||||
aicbsp_info.cpmode = val;
|
||||
printk("%s, set mode to: %lu[%s] done\n", __func__, val, aicbsp_firmware_list[val].desc);
|
||||
printk("%s, set mode to: %lu[%s] done\n", __func__, val,
|
||||
aicbsp_firmware_list[val].desc);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t hwinfo_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t hwinfo_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
ssize_t count = 0;
|
||||
|
||||
@@ -260,20 +276,23 @@ static ssize_t hwinfo_show(struct device *dev,
|
||||
|
||||
count += sprintf(&buf[count], "hwinfo read: ");
|
||||
if (aicbsp_info.hwinfo_r < 0)
|
||||
count += sprintf(&buf[count], "%d(not avalible), ", aicbsp_info.hwinfo_r);
|
||||
count += sprintf(&buf[count], "%d(not avalible), ",
|
||||
aicbsp_info.hwinfo_r);
|
||||
else
|
||||
count += sprintf(&buf[count], "0x%02X, ", aicbsp_info.hwinfo_r);
|
||||
|
||||
if (aicbsp_info.hwinfo < 0)
|
||||
count += sprintf(&buf[count], "set: %d(not avalible)\n", aicbsp_info.hwinfo);
|
||||
count += sprintf(&buf[count], "set: %d(not avalible)\n",
|
||||
aicbsp_info.hwinfo);
|
||||
else
|
||||
count += sprintf(&buf[count], "set: 0x%02X\n", aicbsp_info.hwinfo);
|
||||
count += sprintf(&buf[count], "set: 0x%02X\n",
|
||||
aicbsp_info.hwinfo);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t hwinfo_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
static ssize_t hwinfo_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
long val;
|
||||
int err = kstrtol(buf, 0, &val);
|
||||
@@ -292,19 +311,19 @@ static ssize_t hwinfo_store(struct device *dev,
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t fwdebug_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t fwdebug_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
ssize_t count = 0;
|
||||
|
||||
count += sprintf(&buf[count], "fw log status: %s\n",
|
||||
aicbsp_info.fwlog_en ? "on" : "off");
|
||||
aicbsp_info.fwlog_en ? "on" : "off");
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t fwdebug_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
static ssize_t fwdebug_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
long val;
|
||||
int err = kstrtol(buf, 0, &val);
|
||||
@@ -323,14 +342,11 @@ static ssize_t fwdebug_store(struct device *dev,
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(cpmode, S_IRUGO | S_IWUSR,
|
||||
cpmode_show, cpmode_store);
|
||||
static DEVICE_ATTR(cpmode, S_IRUGO | S_IWUSR, cpmode_show, cpmode_store);
|
||||
|
||||
static DEVICE_ATTR(hwinfo, S_IRUGO | S_IWUSR,
|
||||
hwinfo_show, hwinfo_store);
|
||||
static DEVICE_ATTR(hwinfo, S_IRUGO | S_IWUSR, hwinfo_show, hwinfo_store);
|
||||
|
||||
static DEVICE_ATTR(fwdebug, S_IRUGO | S_IWUSR,
|
||||
fwdebug_show, fwdebug_store);
|
||||
static DEVICE_ATTR(fwdebug, S_IRUGO | S_IWUSR, fwdebug_show, fwdebug_store);
|
||||
|
||||
static struct attribute *aicbsp_attributes[] = {
|
||||
&dev_attr_cpmode.attr,
|
||||
@@ -340,7 +356,7 @@ static struct attribute *aicbsp_attributes[] = {
|
||||
};
|
||||
|
||||
static struct attribute_group aicbsp_attribute_group = {
|
||||
.name = "aicbsp_info",
|
||||
.name = "aicbsp_info",
|
||||
.attrs = aicbsp_attributes,
|
||||
};
|
||||
|
||||
@@ -349,7 +365,6 @@ int adap_test = 0;
|
||||
module_param(testmode, int, 0660);
|
||||
module_param(adap_test, int, 0660);
|
||||
|
||||
|
||||
static int __init aicbsp_init(void)
|
||||
{
|
||||
int ret;
|
||||
@@ -359,6 +374,9 @@ static int __init aicbsp_init(void)
|
||||
aicbsp_info.cpmode = testmode;
|
||||
|
||||
aicbsp_resv_mem_init();
|
||||
|
||||
sema_init(&aicbsp_probe_semaphore, 0);
|
||||
|
||||
ret = platform_driver_register(&aicbsp_driver);
|
||||
if (ret) {
|
||||
pr_err("register platform driver failed: %d\n", ret);
|
||||
@@ -372,7 +390,8 @@ static int __init aicbsp_init(void)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = sysfs_create_group(&(aicbsp_pdev->dev.kobj), &aicbsp_attribute_group);
|
||||
ret = sysfs_create_group(&(aicbsp_pdev->dev.kobj),
|
||||
&aicbsp_attribute_group);
|
||||
if (ret) {
|
||||
pr_err("register sysfs create group failed!\n");
|
||||
return ret;
|
||||
@@ -391,9 +410,9 @@ extern struct aic_sdio_dev *aicbsp_sdiodev;
|
||||
static void __exit aicbsp_exit(void)
|
||||
{
|
||||
#if defined CONFIG_PLATFORM_ROCKCHIP || defined CONFIG_PLATFORM_ROCKCHIP2
|
||||
if(aicbsp_sdiodev){
|
||||
aicbsp_sdio_exit();
|
||||
}
|
||||
if (aicbsp_sdiodev) {
|
||||
aicbsp_sdio_exit();
|
||||
}
|
||||
#endif
|
||||
sysfs_remove_group(&(aicbsp_pdev->dev.kobj), &aicbsp_attribute_group);
|
||||
platform_device_del(aicbsp_pdev);
|
||||
@@ -401,7 +420,7 @@ static void __exit aicbsp_exit(void)
|
||||
mutex_destroy(&aicbsp_power_lock);
|
||||
aicbsp_resv_mem_deinit();
|
||||
#ifdef CONFIG_PREALLOC_TXQ
|
||||
aicwf_prealloc_txq_free();
|
||||
aicwf_prealloc_txq_free();
|
||||
#endif
|
||||
printk("%s\n", __func__);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -16,75 +16,76 @@
|
||||
#include <linux/semaphore.h>
|
||||
#include "aic_bsp_driver.h"
|
||||
|
||||
#define AICBSP_SDIO_NAME "aicbsp_sdio"
|
||||
#define SDIOWIFI_FUNC_BLOCKSIZE 512
|
||||
#define AICBSP_SDIO_NAME "aicbsp_sdio"
|
||||
#define SDIOWIFI_FUNC_BLOCKSIZE 512
|
||||
|
||||
#define SDIO_VENDOR_ID_AIC 0x8800
|
||||
#define SDIO_DEVICE_ID_AIC 0x0001
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG 0x02
|
||||
#define SDIOWIFI_INTR_CONFIG_REG 0x04
|
||||
#define SDIOWIFI_SLEEP_REG 0x05
|
||||
#define SDIOWIFI_WAKEUP_REG 0x09
|
||||
#define SDIOWIFI_FLOW_CTRL_REG 0x0A
|
||||
#define SDIOWIFI_REGISTER_BLOCK 0x0B
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG 0x11
|
||||
#define SDIOWIFI_BLOCK_CNT_REG 0x12
|
||||
#define SDIOWIFI_FLOWCTRL_MASK_REG 0x7F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR 0x07
|
||||
#define SDIOWIFI_RD_FIFO_ADDR 0x08
|
||||
#define SDIO_VENDOR_ID_AIC 0x8800
|
||||
#define SDIO_DEVICE_ID_AIC 0x0001
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG 0x02
|
||||
#define SDIOWIFI_INTR_CONFIG_REG 0x04
|
||||
#define SDIOWIFI_SLEEP_REG 0x05
|
||||
#define SDIOWIFI_WAKEUP_REG 0x09
|
||||
#define SDIOWIFI_FLOW_CTRL_REG 0x0A
|
||||
#define SDIOWIFI_REGISTER_BLOCK 0x0B
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG 0x11
|
||||
#define SDIOWIFI_BLOCK_CNT_REG 0x12
|
||||
#define SDIOWIFI_FLOWCTRL_MASK_REG 0x7F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR 0x07
|
||||
#define SDIOWIFI_RD_FIFO_ADDR 0x08
|
||||
|
||||
#define SDIOWIFI_INTR_ENABLE_REG_V3 0x00
|
||||
#define SDIOWIFI_INTR_PENDING_REG_V3 0x01
|
||||
#define SDIOWIFI_INTR_TO_DEVICE_REG_V3 0x02
|
||||
#define SDIOWIFI_FLOW_CTRL_Q1_REG_V3 0x03
|
||||
#define SDIOWIFI_MISC_INT_STATUS_REG_V3 0x04
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG_V3 0x05
|
||||
#define SDIOWIFI_BYTEMODE_LEN_MSB_REG_V3 0x06
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG_V3 0x07
|
||||
#define SDIOWIFI_MISC_CTRL_REG_V3 0x08
|
||||
#define SDIOWIFI_FLOW_CTRL_Q2_REG_V3 0x09
|
||||
#define SDIOWIFI_CLK_TEST_RESULT_REG_V3 0x0A
|
||||
#define SDIOWIFI_RD_FIFO_ADDR_V3 0x0F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR_V3 0x10
|
||||
#define SDIOWIFI_INTR_ENABLE_REG_V3 0x00
|
||||
#define SDIOWIFI_INTR_PENDING_REG_V3 0x01
|
||||
#define SDIOWIFI_INTR_TO_DEVICE_REG_V3 0x02
|
||||
#define SDIOWIFI_FLOW_CTRL_Q1_REG_V3 0x03
|
||||
#define SDIOWIFI_MISC_INT_STATUS_REG_V3 0x04
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG_V3 0x05
|
||||
#define SDIOWIFI_BYTEMODE_LEN_MSB_REG_V3 0x06
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG_V3 0x07
|
||||
#define SDIOWIFI_MISC_CTRL_REG_V3 0x08
|
||||
#define SDIOWIFI_FLOW_CTRL_Q2_REG_V3 0x09
|
||||
#define SDIOWIFI_CLK_TEST_RESULT_REG_V3 0x0A
|
||||
#define SDIOWIFI_RD_FIFO_ADDR_V3 0x0F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR_V3 0x10
|
||||
|
||||
#define SDIOCLK_FREE_RUNNING_BIT (1 << 6)
|
||||
#define SDIOCLK_FREE_RUNNING_BIT (1 << 6)
|
||||
|
||||
#define SDIOWIFI_PWR_CTRL_INTERVAL 30
|
||||
#define FLOW_CTRL_RETRY_COUNT 50
|
||||
#define BUFFER_SIZE 1536
|
||||
#define TAIL_LEN 4
|
||||
#define TXQLEN (2048*4)
|
||||
#define SDIOWIFI_PWR_CTRL_INTERVAL 30
|
||||
#define FLOW_CTRL_RETRY_COUNT 50
|
||||
#define BUFFER_SIZE 1536
|
||||
#define TAIL_LEN 4
|
||||
#define TXQLEN (2048 * 4)
|
||||
|
||||
#define SDIO_SLEEP_ST 0
|
||||
#define SDIO_ACTIVE_ST 1
|
||||
#define SDIO_SLEEP_ST 0
|
||||
#define SDIO_ACTIVE_ST 1
|
||||
|
||||
typedef enum {
|
||||
SDIO_TYPE_DATA = 0X00,
|
||||
SDIO_TYPE_CFG = 0X10,
|
||||
SDIO_TYPE_CFG_CMD_RSP = 0X11,
|
||||
SDIO_TYPE_DATA = 0X00,
|
||||
SDIO_TYPE_CFG = 0X10,
|
||||
SDIO_TYPE_CFG_CMD_RSP = 0X11,
|
||||
SDIO_TYPE_CFG_DATA_CFM = 0X12
|
||||
} sdio_type;
|
||||
|
||||
enum AICWF_IC{
|
||||
PRODUCT_ID_AIC8801 = 0,
|
||||
enum AICWF_IC {
|
||||
PRODUCT_ID_AIC8801 = 0,
|
||||
PRODUCT_ID_AIC8800DC,
|
||||
PRODUCT_ID_AIC8800DW,
|
||||
PRODUCT_ID_AIC8800D80
|
||||
PRODUCT_ID_AIC8800D80,
|
||||
PRODUCT_ID_AIC8800D80X2
|
||||
};
|
||||
|
||||
struct aic_sdio_reg {
|
||||
u8 bytemode_len_reg;
|
||||
u8 intr_config_reg;
|
||||
u8 sleep_reg;
|
||||
u8 wakeup_reg;
|
||||
u8 flow_ctrl_reg;
|
||||
u8 flowctrl_mask_reg;
|
||||
u8 register_block;
|
||||
u8 bytemode_enable_reg;
|
||||
u8 block_cnt_reg;
|
||||
u8 misc_int_status_reg;
|
||||
u8 rd_fifo_addr;
|
||||
u8 wr_fifo_addr;
|
||||
u8 bytemode_len_reg;
|
||||
u8 intr_config_reg;
|
||||
u8 sleep_reg;
|
||||
u8 wakeup_reg;
|
||||
u8 flow_ctrl_reg;
|
||||
u8 flowctrl_mask_reg;
|
||||
u8 register_block;
|
||||
u8 bytemode_enable_reg;
|
||||
u8 block_cnt_reg;
|
||||
u8 misc_int_status_reg;
|
||||
u8 rd_fifo_addr;
|
||||
u8 wr_fifo_addr;
|
||||
};
|
||||
|
||||
struct aic_sdio_dev {
|
||||
@@ -109,8 +110,8 @@ struct aic_sdio_dev {
|
||||
#endif
|
||||
u16 chipid;
|
||||
u32 fw_version_uint;
|
||||
struct aic_sdio_reg sdio_reg;
|
||||
void (*sdio_hal_irqhandler) (struct sdio_func *func);
|
||||
struct aic_sdio_reg sdio_reg;
|
||||
void (*sdio_hal_irqhandler)(struct sdio_func *func);
|
||||
};
|
||||
|
||||
void *aicbsp_get_drvdata(void *args);
|
||||
@@ -119,19 +120,20 @@ void aicwf_sdio_hal_irqhandler(struct sdio_func *func);
|
||||
void aicwf_sdio_hal_irqhandler_func2(struct sdio_func *func);
|
||||
#if defined(CONFIG_SDIO_PWRCTRL)
|
||||
void aicwf_sdio_pwrctl_timer(struct aic_sdio_dev *sdiodev, uint duration);
|
||||
int aicwf_sdio_pwr_stctl(struct aic_sdio_dev *sdiodev, uint target);
|
||||
int aicwf_sdio_pwr_stctl(struct aic_sdio_dev *sdiodev, uint target);
|
||||
#endif
|
||||
void aicwf_sdio_reg_init(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_sdio_func_init(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_sdiov3_func_init(struct aic_sdio_dev *sdiodev);
|
||||
void aicwf_sdio_func_deinit(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_sdio_flow_ctrl(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_sdio_recv_pkt(struct aic_sdio_dev *sdiodev, struct sk_buff *skbbuf, u32 size, u8 msg);
|
||||
int aicwf_sdio_recv_pkt(struct aic_sdio_dev *sdiodev, struct sk_buff *skbbuf,
|
||||
u32 size, u8 msg);
|
||||
int aicwf_sdio_send_pkt(struct aic_sdio_dev *sdiodev, u8 *buf, uint count);
|
||||
void *aicwf_sdio_bus_init(struct aic_sdio_dev *sdiodev);
|
||||
void aicwf_sdio_release(struct aic_sdio_dev *sdiodev);
|
||||
void aicbsp_sdio_exit(void);
|
||||
int aicbsp_sdio_init(void);
|
||||
int aicbsp_sdio_init(void);
|
||||
void aicbsp_sdio_release(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_sdio_txpkt(struct aic_sdio_dev *sdiodev, struct sk_buff *pkt);
|
||||
int aicwf_sdio_bustx_thread(void *data);
|
||||
|
||||
@@ -40,24 +40,27 @@ int aicwf_bus_init(uint bus_hdrlen, struct device *dev)
|
||||
init_completion(&bus_if->bustx_trgg);
|
||||
init_completion(&bus_if->busrx_trgg);
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
bus_if->bustx_thread = kthread_run(aicwf_sdio_bustx_thread, (void *)bus_if, "aicwf_bustx_thread");
|
||||
bus_if->busrx_thread = kthread_run(aicwf_sdio_busrx_thread, (void *)bus_if->bus_priv.sdio->rx_priv, "aicwf_busrx_thread");
|
||||
#endif
|
||||
|
||||
bus_if->bustx_thread = kthread_run(
|
||||
aicwf_sdio_bustx_thread, (void *)bus_if, "aicwf_bustx_thread");
|
||||
if (IS_ERR(bus_if->bustx_thread)) {
|
||||
bus_if->bustx_thread = NULL;
|
||||
bus_if->bustx_thread = NULL;
|
||||
txrx_err("aicwf_bustx_thread run fail\n");
|
||||
ret = -1;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
bus_if->busrx_thread =
|
||||
kthread_run(aicwf_sdio_busrx_thread,
|
||||
(void *)bus_if->bus_priv.sdio->rx_priv,
|
||||
"aicwf_busrx_thread");
|
||||
if (IS_ERR(bus_if->busrx_thread)) {
|
||||
bus_if->busrx_thread = NULL;
|
||||
bus_if->busrx_thread = NULL;
|
||||
txrx_err("aicwf_bustx_thread run fail\n");
|
||||
ret = -1;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
#endif
|
||||
return ret;
|
||||
fail:
|
||||
aicwf_bus_deinit(dev);
|
||||
@@ -173,15 +176,19 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
data = skb->data;
|
||||
pkt_len = (*skb->data | (*(skb->data + 1) << 8));
|
||||
|
||||
if ((skb->data[2] & SDIO_TYPE_CFG) != SDIO_TYPE_CFG) { // type : data
|
||||
if ((skb->data[2] & SDIO_TYPE_CFG) !=
|
||||
SDIO_TYPE_CFG) { // type : data
|
||||
aggr_len = pkt_len + RX_HWHRD_LEN;
|
||||
|
||||
if (aggr_len & (RX_ALIGNMENT - 1))
|
||||
adjust_len = roundup(aggr_len, RX_ALIGNMENT);
|
||||
adjust_len =
|
||||
roundup(aggr_len, RX_ALIGNMENT);
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
skb_inblock = __dev_alloc_skb(aggr_len + CCMP_OR_WEP_INFO, GFP_KERNEL);//8 is for ccmp mic or wep icv
|
||||
skb_inblock = __dev_alloc_skb(
|
||||
aggr_len + CCMP_OR_WEP_INFO,
|
||||
GFP_KERNEL); //8 is for ccmp mic or wep icv
|
||||
if (skb_inblock == NULL) {
|
||||
txrx_err("no more space!\n");
|
||||
aicwf_dev_skb_free(skb);
|
||||
@@ -190,34 +197,41 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
|
||||
skb_put(skb_inblock, aggr_len);
|
||||
memcpy(skb_inblock->data, data, aggr_len);
|
||||
#if 0
|
||||
#if 0
|
||||
rwnx_rxdataind_aicwf(rx_priv->sdiodev->rwnx_hw, skb_inblock, (void *)rx_priv);
|
||||
#endif
|
||||
#endif
|
||||
skb_pull(skb, adjust_len);
|
||||
} else { // type : config
|
||||
aggr_len = pkt_len;
|
||||
|
||||
if (aggr_len & (RX_ALIGNMENT - 1))
|
||||
adjust_len = roundup(aggr_len, RX_ALIGNMENT);
|
||||
adjust_len =
|
||||
roundup(aggr_len, RX_ALIGNMENT);
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
skb_inblock = __dev_alloc_skb(aggr_len+4, GFP_KERNEL);
|
||||
if (skb_inblock == NULL) {
|
||||
txrx_err("no more space!\n");
|
||||
aicwf_dev_skb_free(skb);
|
||||
return -EBADE;
|
||||
skb_inblock = __dev_alloc_skb(aggr_len + 4,
|
||||
GFP_KERNEL);
|
||||
if (skb_inblock == NULL) {
|
||||
txrx_err("no more space!\n");
|
||||
aicwf_dev_skb_free(skb);
|
||||
return -EBADE;
|
||||
}
|
||||
|
||||
skb_put(skb_inblock, aggr_len+4);
|
||||
memcpy(skb_inblock->data, data, aggr_len+4);
|
||||
if ((*(skb_inblock->data + 2) & 0x7f) == SDIO_TYPE_CFG_CMD_RSP)
|
||||
rwnx_rx_handle_msg(rx_priv->sdiodev, (struct ipc_e2a_msg *)(skb_inblock->data + 4));
|
||||
#if 0
|
||||
skb_put(skb_inblock, aggr_len + 4);
|
||||
memcpy(skb_inblock->data, data, aggr_len + 4);
|
||||
if ((*(skb_inblock->data + 2) & 0x7f) ==
|
||||
SDIO_TYPE_CFG_CMD_RSP)
|
||||
rwnx_rx_handle_msg(
|
||||
rx_priv->sdiodev,
|
||||
(struct ipc_e2a_msg
|
||||
*)(skb_inblock->data +
|
||||
4));
|
||||
#if 0
|
||||
if ((*(skb_inblock->data + 2) & 0x7f) == SDIO_TYPE_CFG_DATA_CFM)
|
||||
aicwf_sdio_host_tx_cfm_handler(&(rx_priv->sdiodev->rwnx_hw->sdio_env), (u32 *)(skb_inblock->data + 4));
|
||||
#endif
|
||||
skb_pull(skb, adjust_len+4);
|
||||
#endif
|
||||
skb_pull(skb, adjust_len + 4);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -234,12 +248,13 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct recv_msdu *aicwf_rxframe_queue_init(struct list_head *q, int qsize)
|
||||
static struct recv_msdu *aicwf_rxframe_queue_init(struct list_head *q,
|
||||
int qsize)
|
||||
{
|
||||
int i;
|
||||
struct recv_msdu *req, *reqs;
|
||||
|
||||
reqs = vmalloc(qsize*sizeof(struct recv_msdu));
|
||||
reqs = vmalloc(qsize * sizeof(struct recv_msdu));
|
||||
if (reqs == NULL)
|
||||
return NULL;
|
||||
|
||||
@@ -268,7 +283,8 @@ struct aicwf_rx_priv *aicwf_rx_init(void *arg)
|
||||
|
||||
INIT_LIST_HEAD(&rx_priv->rxframes_freequeue);
|
||||
spin_lock_init(&rx_priv->freeq_lock);
|
||||
rx_priv->recv_frames = aicwf_rxframe_queue_init(&rx_priv->rxframes_freequeue, MAX_REORD_RXFRAME);
|
||||
rx_priv->recv_frames = aicwf_rxframe_queue_init(
|
||||
&rx_priv->rxframes_freequeue, MAX_REORD_RXFRAME);
|
||||
if (!rx_priv->recv_frames) {
|
||||
txrx_err("no enough buffer for free recv frame queue!\n");
|
||||
kfree(rx_priv);
|
||||
@@ -280,12 +296,11 @@ struct aicwf_rx_priv *aicwf_rx_init(void *arg)
|
||||
return rx_priv;
|
||||
}
|
||||
|
||||
|
||||
static void aicwf_recvframe_queue_deinit(struct list_head *q)
|
||||
{
|
||||
struct recv_msdu *req, *next;
|
||||
|
||||
list_for_each_entry_safe(req, next, q, rxframe_list) {
|
||||
list_for_each_entry_safe (req, next, q, rxframe_list) {
|
||||
list_del_init(&req->rxframe_list);
|
||||
}
|
||||
}
|
||||
@@ -307,12 +322,12 @@ void aicwf_rx_deinit(struct aicwf_rx_priv *rx_priv)
|
||||
//rx_priv = NULL;
|
||||
}
|
||||
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q, struct sk_buff *pkt)
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt)
|
||||
{
|
||||
return aicwf_frame_enq(dev, q, pkt, 0);
|
||||
}
|
||||
|
||||
|
||||
void aicwf_dev_skb_free(struct sk_buff *skb)
|
||||
{
|
||||
if (!skb)
|
||||
@@ -321,7 +336,8 @@ void aicwf_dev_skb_free(struct sk_buff *skb)
|
||||
dev_kfree_skb_any(skb);
|
||||
}
|
||||
|
||||
static struct sk_buff *aicwf_frame_queue_penq(struct frame_queue *pq, int prio, struct sk_buff *p)
|
||||
static struct sk_buff *aicwf_frame_queue_penq(struct frame_queue *pq, int prio,
|
||||
struct sk_buff *p)
|
||||
{
|
||||
struct sk_buff_head *q;
|
||||
|
||||
@@ -345,7 +361,8 @@ void aicwf_frame_queue_flush(struct frame_queue *pq)
|
||||
|
||||
for (prio = 0; prio < pq->num_prio; prio++) {
|
||||
q = &pq->queuelist[prio];
|
||||
skb_queue_walk_safe(q, p, next) {
|
||||
skb_queue_walk_safe(q, p, next)
|
||||
{
|
||||
skb_unlink(p, q);
|
||||
aicwf_dev_skb_free(p);
|
||||
pq->qcnt--;
|
||||
@@ -357,7 +374,9 @@ void aicwf_frame_queue_init(struct frame_queue *pq, int num_prio, int max_len)
|
||||
{
|
||||
int prio;
|
||||
|
||||
memset(pq, 0, offsetof(struct frame_queue, queuelist) + (sizeof(struct sk_buff_head) * num_prio));
|
||||
memset(pq, 0,
|
||||
offsetof(struct frame_queue, queuelist) +
|
||||
(sizeof(struct sk_buff_head) * num_prio));
|
||||
pq->num_prio = (u16)num_prio;
|
||||
pq->qmax = (u16)max_len;
|
||||
|
||||
@@ -366,7 +385,8 @@ void aicwf_frame_queue_init(struct frame_queue *pq, int num_prio, int max_len)
|
||||
}
|
||||
}
|
||||
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq, int *prio_out)
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq,
|
||||
int *prio_out)
|
||||
{
|
||||
int prio;
|
||||
|
||||
@@ -405,7 +425,8 @@ struct sk_buff *aicwf_frame_dequeue(struct frame_queue *pq)
|
||||
if (pq->qcnt == 0)
|
||||
return NULL;
|
||||
|
||||
while ((prio = pq->hi_prio) > 0 && skb_queue_empty(&pq->queuelist[prio]))
|
||||
while ((prio = pq->hi_prio) > 0 &&
|
||||
skb_queue_empty(&pq->queuelist[prio]))
|
||||
pq->hi_prio--;
|
||||
|
||||
q = &pq->queuelist[prio];
|
||||
@@ -430,7 +451,8 @@ static struct sk_buff *aicwf_skb_dequeue_tail(struct frame_queue *pq, int prio)
|
||||
return p;
|
||||
}
|
||||
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q, struct sk_buff *pkt, int prio)
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt, int prio)
|
||||
{
|
||||
struct sk_buff *p = NULL;
|
||||
int prio_modified = -1;
|
||||
@@ -461,5 +483,3 @@ bool aicwf_frame_enq(struct device *dev, struct frame_queue *q, struct sk_buff *
|
||||
|
||||
return p != NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -13,58 +13,61 @@
|
||||
#include <linux/sched.h>
|
||||
#include "aicsdio.h"
|
||||
|
||||
#define CMD_BUF_MAX 1536
|
||||
#define TXPKT_BLOCKSIZE 512
|
||||
#define MAX_AGGR_TXPKT_LEN (1536*4)
|
||||
#define CMD_TX_TIMEOUT 5000
|
||||
#define TX_ALIGNMENT 4
|
||||
#define CMD_BUF_MAX 1536
|
||||
#define TXPKT_BLOCKSIZE 512
|
||||
#define MAX_AGGR_TXPKT_LEN (1536 * 4)
|
||||
#define CMD_TX_TIMEOUT 5000
|
||||
#define TX_ALIGNMENT 4
|
||||
|
||||
#define RX_HWHRD_LEN 60 //58->60 word allined
|
||||
#define CCMP_OR_WEP_INFO 8
|
||||
#define MAX_RXQLEN 2000
|
||||
#define RX_ALIGNMENT 4
|
||||
#define RX_HWHRD_LEN 60 //58->60 word allined
|
||||
#define CCMP_OR_WEP_INFO 8
|
||||
#define MAX_RXQLEN 2000
|
||||
#define RX_ALIGNMENT 4
|
||||
|
||||
#define DEBUG_ERROR_LEVEL 0
|
||||
#define DEBUG_DEBUG_LEVEL 1
|
||||
#define DEBUG_INFO_LEVEL 2
|
||||
#define DEBUG_ERROR_LEVEL 0
|
||||
#define DEBUG_DEBUG_LEVEL 1
|
||||
#define DEBUG_INFO_LEVEL 2
|
||||
|
||||
#define DBG_LEVEL DEBUG_DEBUG_LEVEL
|
||||
#define DBG_LEVEL DEBUG_DEBUG_LEVEL
|
||||
|
||||
#define txrx_err(fmt, ...) pr_err("aicbsp: txrx_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define sdio_err(fmt, ...) pr_err("aicbsp: sdio_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define usb_err(fmt, ...) pr_err("aicbsp: usb_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define txrx_err(fmt, ...) \
|
||||
pr_err("aicbsp: txrx_err:<%s,%d>: " fmt, __func__, __LINE__, \
|
||||
##__VA_ARGS__)
|
||||
#define sdio_err(fmt, ...) \
|
||||
pr_err("aicbsp: sdio_err:<%s,%d>: " fmt, __func__, __LINE__, \
|
||||
##__VA_ARGS__)
|
||||
#define usb_err(fmt, ...) \
|
||||
pr_err("aicbsp: usb_err:<%s,%d>: " fmt, __func__, __LINE__, \
|
||||
##__VA_ARGS__)
|
||||
#if DBG_LEVEL >= DEBUG_DEBUG_LEVEL
|
||||
#define sdio_dbg(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#define usb_dbg(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#define sdio_dbg(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#define usb_dbg(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define sdio_dbg(fmt, ...)
|
||||
#define usb_dbg(fmt, ...)
|
||||
#endif
|
||||
#if DBG_LEVEL >= DEBUG_INFO_LEVEL
|
||||
#define sdio_info(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#define usb_info(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#define sdio_info(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#define usb_info(fmt, ...) printk("aicbsp: " fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define sdio_info(fmt, ...)
|
||||
#define usb_info(fmt, ...)
|
||||
#endif
|
||||
|
||||
enum aicwf_bus_state {
|
||||
BUS_DOWN_ST,
|
||||
BUS_UP_ST
|
||||
};
|
||||
enum aicwf_bus_state { BUS_DOWN_ST, BUS_UP_ST };
|
||||
|
||||
struct aicwf_bus_ops {
|
||||
int (*start) (struct device *dev);
|
||||
void (*stop) (struct device *dev);
|
||||
int (*txdata) (struct device *dev, struct sk_buff *skb);
|
||||
int (*txmsg) (struct device *dev, u8 *msg, uint len);
|
||||
int (*start)(struct device *dev);
|
||||
void (*stop)(struct device *dev);
|
||||
int (*txdata)(struct device *dev, struct sk_buff *skb);
|
||||
int (*txmsg)(struct device *dev, u8 *msg, uint len);
|
||||
};
|
||||
|
||||
struct frame_queue {
|
||||
u16 num_prio;
|
||||
u16 hi_prio;
|
||||
u16 qmax; /* max number of queued frames */
|
||||
u16 qcnt;
|
||||
u16 num_prio;
|
||||
u16 hi_prio;
|
||||
u16 qmax; /* max number of queued frames */
|
||||
u16 qcnt;
|
||||
struct sk_buff_head queuelist[8];
|
||||
};
|
||||
|
||||
@@ -110,12 +113,11 @@ struct aicwf_tx_priv {
|
||||
u8 *tail;
|
||||
};
|
||||
|
||||
|
||||
#define MAX_REORD_RXFRAME 250
|
||||
#define REORDER_UPDATE_TIME 50
|
||||
#define AICWF_REORDER_WINSIZE 64
|
||||
#define SN_LESS(a, b) (((a-b)&0x800) != 0)
|
||||
#define SN_EQUAL(a, b) (a == b)
|
||||
#define MAX_REORD_RXFRAME 250
|
||||
#define REORDER_UPDATE_TIME 50
|
||||
#define AICWF_REORDER_WINSIZE 64
|
||||
#define SN_LESS(a, b) (((a - b) & 0x800) != 0)
|
||||
#define SN_EQUAL(a, b) (a == b)
|
||||
|
||||
struct reord_ctrl {
|
||||
struct aicwf_rx_priv *rx_priv;
|
||||
@@ -135,12 +137,12 @@ struct reord_ctrl_info {
|
||||
};
|
||||
|
||||
struct recv_msdu {
|
||||
struct sk_buff *pkt;
|
||||
u8 tid;
|
||||
u16 seq_num;
|
||||
uint len;
|
||||
u8 *rx_data;
|
||||
//for pending rx reorder list
|
||||
struct sk_buff *pkt;
|
||||
u8 tid;
|
||||
u16 seq_num;
|
||||
uint len;
|
||||
u8 *rx_data;
|
||||
//for pending rx reorder list
|
||||
struct list_head reord_pending_list;
|
||||
//for total frame list, when rxframe from busif, dequeue, when submit frame to net, enqueue
|
||||
struct list_head rxframe_list;
|
||||
@@ -203,12 +205,15 @@ struct aicwf_tx_priv *aicwf_tx_init(void *arg);
|
||||
struct aicwf_rx_priv *aicwf_rx_init(void *arg);
|
||||
void aicwf_frame_queue_init(struct frame_queue *pq, int num_prio, int max_len);
|
||||
void aicwf_frame_queue_flush(struct frame_queue *pq);
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q, struct sk_buff *pkt, int prio);
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q, struct sk_buff *pkt);
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt, int prio);
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt);
|
||||
bool aicwf_is_framequeue_empty(struct frame_queue *pq);
|
||||
void aicwf_frame_tx(void *dev, struct sk_buff *skb);
|
||||
void aicwf_dev_skb_free(struct sk_buff *skb);
|
||||
struct sk_buff *aicwf_frame_dequeue(struct frame_queue *pq);
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq, int *prio_out);
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq,
|
||||
int *prio_out);
|
||||
|
||||
#endif /* _AICWF_TXRXIF_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,3 +1 @@
|
||||
int aicwf_get_firmware_array(char* fw_name, u32 **fw_buf);
|
||||
|
||||
|
||||
int aicwf_get_firmware_array(char *fw_name, u32 **fw_buf);
|
||||
|
||||
@@ -2,10 +2,10 @@
|
||||
#include "aicsdio_txrxif.h"
|
||||
#include "aic_bsp_driver.h"
|
||||
|
||||
struct prealloc_txq{
|
||||
int prealloced;
|
||||
void *txq;
|
||||
size_t size;
|
||||
struct prealloc_txq {
|
||||
int prealloced;
|
||||
void *txq;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
struct prealloc_txq prealloc_txq;
|
||||
@@ -13,50 +13,47 @@ struct prealloc_txq prealloc_txq;
|
||||
|
||||
void *aicwf_prealloc_txq_alloc(size_t size)
|
||||
{
|
||||
BUG_ON(size > MAX_TXQ_SIZE);
|
||||
|
||||
BUG_ON(size > MAX_TXQ_SIZE);
|
||||
//check prealloc_txq.size
|
||||
if ((int)prealloc_txq.size != (int)size) {
|
||||
AICWFDBG(LOGINFO, "%s size is diff will to be kzalloc \r\n",
|
||||
__func__);
|
||||
|
||||
//check prealloc_txq.size
|
||||
if((int)prealloc_txq.size != (int)size)
|
||||
{
|
||||
AICWFDBG(LOGINFO, "%s size is diff will to be kzalloc \r\n", __func__);
|
||||
if (prealloc_txq.txq != NULL) {
|
||||
AICWFDBG(LOGINFO, "%s txq to kfree \r\n", __func__);
|
||||
kfree(prealloc_txq.txq);
|
||||
prealloc_txq.txq = NULL;
|
||||
}
|
||||
|
||||
if(prealloc_txq.txq != NULL)
|
||||
{
|
||||
AICWFDBG(LOGINFO, "%s txq to kfree \r\n", __func__);
|
||||
kfree(prealloc_txq.txq);
|
||||
prealloc_txq.txq = NULL;
|
||||
}
|
||||
|
||||
prealloc_txq.size = size;
|
||||
prealloc_txq.prealloced = 0;
|
||||
}
|
||||
prealloc_txq.size = size;
|
||||
prealloc_txq.prealloced = 0;
|
||||
}
|
||||
|
||||
//check prealloc or not
|
||||
if(!prealloc_txq.prealloced)
|
||||
{
|
||||
prealloc_txq.txq = kzalloc(size, GFP_KERNEL);
|
||||
if(!prealloc_txq.txq){
|
||||
AICWFDBG(LOGERROR, "%s txq kzalloc fail \r\n", __func__);
|
||||
}else{
|
||||
AICWFDBG(LOGINFO, "%s txq kzalloc successful \r\n", __func__);
|
||||
prealloc_txq.prealloced = 1;
|
||||
}
|
||||
}else{
|
||||
AICWFDBG(LOGINFO, "%s txq not need to kzalloc \r\n", __func__);
|
||||
}
|
||||
//check prealloc or not
|
||||
if (!prealloc_txq.prealloced) {
|
||||
prealloc_txq.txq = kzalloc(size, GFP_KERNEL);
|
||||
if (!prealloc_txq.txq) {
|
||||
AICWFDBG(LOGERROR, "%s txq kzalloc fail \r\n",
|
||||
__func__);
|
||||
} else {
|
||||
AICWFDBG(LOGINFO, "%s txq kzalloc successful \r\n",
|
||||
__func__);
|
||||
prealloc_txq.prealloced = 1;
|
||||
}
|
||||
} else {
|
||||
AICWFDBG(LOGINFO, "%s txq not need to kzalloc \r\n", __func__);
|
||||
}
|
||||
|
||||
return prealloc_txq.txq;
|
||||
return prealloc_txq.txq;
|
||||
}
|
||||
void aicwf_prealloc_txq_free(void)
|
||||
{
|
||||
if(prealloc_txq.txq != NULL)
|
||||
{
|
||||
AICWFDBG(LOGINFO, "%s txq to kfree \r\n", __func__);
|
||||
kfree(prealloc_txq.txq);
|
||||
prealloc_txq.txq = NULL;
|
||||
}
|
||||
if (prealloc_txq.txq != NULL) {
|
||||
AICWFDBG(LOGINFO, "%s txq to kfree \r\n", __func__);
|
||||
kfree(prealloc_txq.txq);
|
||||
prealloc_txq.txq = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(aicwf_prealloc_txq_alloc);
|
||||
|
||||
|
||||
@@ -1,4 +1,3 @@
|
||||
|
||||
|
||||
void aicwf_prealloc_txq_free(void);
|
||||
|
||||
|
||||
@@ -1,161 +1,154 @@
|
||||
#include <linux/memory.h>
|
||||
#include "md5.h"
|
||||
|
||||
unsigned char PADDING[]={0x80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
|
||||
|
||||
unsigned char PADDING[] = { 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
|
||||
|
||||
void MD5Init(MD5_CTX *context)
|
||||
{
|
||||
context->count[0] = 0;
|
||||
context->count[1] = 0;
|
||||
context->state[0] = 0x67452301;
|
||||
context->state[1] = 0xEFCDAB89;
|
||||
context->state[2] = 0x98BADCFE;
|
||||
context->state[3] = 0x10325476;
|
||||
context->count[0] = 0;
|
||||
context->count[1] = 0;
|
||||
context->state[0] = 0x67452301;
|
||||
context->state[1] = 0xEFCDAB89;
|
||||
context->state[2] = 0x98BADCFE;
|
||||
context->state[3] = 0x10325476;
|
||||
}
|
||||
void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen)
|
||||
void MD5Update(MD5_CTX *context, unsigned char *input, unsigned int inputlen)
|
||||
{
|
||||
unsigned int i = 0,index = 0,partlen = 0;
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
partlen = 64 - index;
|
||||
context->count[0] += inputlen << 3;
|
||||
if(context->count[0] < (inputlen << 3))
|
||||
context->count[1]++;
|
||||
context->count[1] += inputlen >> 29;
|
||||
|
||||
if(inputlen >= partlen)
|
||||
{
|
||||
memcpy(&context->buffer[index],input,partlen);
|
||||
MD5Transform(context->state,context->buffer);
|
||||
for(i = partlen;i+64 <= inputlen;i+=64)
|
||||
MD5Transform(context->state,&input[i]);
|
||||
index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
i = 0;
|
||||
}
|
||||
memcpy(&context->buffer[index],&input[i],inputlen-i);
|
||||
unsigned int i = 0, index = 0, partlen = 0;
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
partlen = 64 - index;
|
||||
context->count[0] += inputlen << 3;
|
||||
if (context->count[0] < (inputlen << 3))
|
||||
context->count[1]++;
|
||||
context->count[1] += inputlen >> 29;
|
||||
|
||||
if (inputlen >= partlen) {
|
||||
memcpy(&context->buffer[index], input, partlen);
|
||||
MD5Transform(context->state, context->buffer);
|
||||
for (i = partlen; i + 64 <= inputlen; i += 64)
|
||||
MD5Transform(context->state, &input[i]);
|
||||
index = 0;
|
||||
} else {
|
||||
i = 0;
|
||||
}
|
||||
memcpy(&context->buffer[index], &input[i], inputlen - i);
|
||||
}
|
||||
void MD5Final(MD5_CTX *context,unsigned char digest[16])
|
||||
void MD5Final(MD5_CTX *context, unsigned char digest[16])
|
||||
{
|
||||
unsigned int index = 0,padlen = 0;
|
||||
unsigned char bits[8];
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
padlen = (index < 56)?(56-index):(120-index);
|
||||
MD5Encode(bits,context->count,8);
|
||||
MD5Update(context,PADDING,padlen);
|
||||
MD5Update(context,bits,8);
|
||||
MD5Encode(digest,context->state,16);
|
||||
unsigned int index = 0, padlen = 0;
|
||||
unsigned char bits[8];
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
padlen = (index < 56) ? (56 - index) : (120 - index);
|
||||
MD5Encode(bits, context->count, 8);
|
||||
MD5Update(context, PADDING, padlen);
|
||||
MD5Update(context, bits, 8);
|
||||
MD5Encode(digest, context->state, 16);
|
||||
}
|
||||
void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len)
|
||||
void MD5Encode(unsigned char *output, unsigned int *input, unsigned int len)
|
||||
{
|
||||
unsigned int i = 0,j = 0;
|
||||
while(j < len)
|
||||
{
|
||||
output[j] = input[i] & 0xFF;
|
||||
output[j+1] = (input[i] >> 8) & 0xFF;
|
||||
output[j+2] = (input[i] >> 16) & 0xFF;
|
||||
output[j+3] = (input[i] >> 24) & 0xFF;
|
||||
i++;
|
||||
j+=4;
|
||||
}
|
||||
unsigned int i = 0, j = 0;
|
||||
while (j < len) {
|
||||
output[j] = input[i] & 0xFF;
|
||||
output[j + 1] = (input[i] >> 8) & 0xFF;
|
||||
output[j + 2] = (input[i] >> 16) & 0xFF;
|
||||
output[j + 3] = (input[i] >> 24) & 0xFF;
|
||||
i++;
|
||||
j += 4;
|
||||
}
|
||||
}
|
||||
void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len)
|
||||
void MD5Decode(unsigned int *output, unsigned char *input, unsigned int len)
|
||||
{
|
||||
unsigned int i = 0,j = 0;
|
||||
while(j < len)
|
||||
{
|
||||
output[i] = (input[j]) |
|
||||
(input[j+1] << 8) |
|
||||
(input[j+2] << 16) |
|
||||
(input[j+3] << 24);
|
||||
i++;
|
||||
j+=4;
|
||||
}
|
||||
unsigned int i = 0, j = 0;
|
||||
while (j < len) {
|
||||
output[i] = (input[j]) | (input[j + 1] << 8) |
|
||||
(input[j + 2] << 16) | (input[j + 3] << 24);
|
||||
i++;
|
||||
j += 4;
|
||||
}
|
||||
}
|
||||
void MD5Transform(unsigned int state[4],unsigned char block[64])
|
||||
void MD5Transform(unsigned int state[4], unsigned char block[64])
|
||||
{
|
||||
unsigned int a = state[0];
|
||||
unsigned int b = state[1];
|
||||
unsigned int c = state[2];
|
||||
unsigned int d = state[3];
|
||||
unsigned int x[64];
|
||||
MD5Decode(x,block,64);
|
||||
FF(a, b, c, d, x[ 0], 7, 0xd76aa478); /* 1 */
|
||||
FF(d, a, b, c, x[ 1], 12, 0xe8c7b756); /* 2 */
|
||||
FF(c, d, a, b, x[ 2], 17, 0x242070db); /* 3 */
|
||||
FF(b, c, d, a, x[ 3], 22, 0xc1bdceee); /* 4 */
|
||||
FF(a, b, c, d, x[ 4], 7, 0xf57c0faf); /* 5 */
|
||||
FF(d, a, b, c, x[ 5], 12, 0x4787c62a); /* 6 */
|
||||
FF(c, d, a, b, x[ 6], 17, 0xa8304613); /* 7 */
|
||||
FF(b, c, d, a, x[ 7], 22, 0xfd469501); /* 8 */
|
||||
FF(a, b, c, d, x[ 8], 7, 0x698098d8); /* 9 */
|
||||
FF(d, a, b, c, x[ 9], 12, 0x8b44f7af); /* 10 */
|
||||
FF(c, d, a, b, x[10], 17, 0xffff5bb1); /* 11 */
|
||||
FF(b, c, d, a, x[11], 22, 0x895cd7be); /* 12 */
|
||||
FF(a, b, c, d, x[12], 7, 0x6b901122); /* 13 */
|
||||
FF(d, a, b, c, x[13], 12, 0xfd987193); /* 14 */
|
||||
FF(c, d, a, b, x[14], 17, 0xa679438e); /* 15 */
|
||||
FF(b, c, d, a, x[15], 22, 0x49b40821); /* 16 */
|
||||
|
||||
/* Round 2 */
|
||||
GG(a, b, c, d, x[ 1], 5, 0xf61e2562); /* 17 */
|
||||
GG(d, a, b, c, x[ 6], 9, 0xc040b340); /* 18 */
|
||||
GG(c, d, a, b, x[11], 14, 0x265e5a51); /* 19 */
|
||||
GG(b, c, d, a, x[ 0], 20, 0xe9b6c7aa); /* 20 */
|
||||
GG(a, b, c, d, x[ 5], 5, 0xd62f105d); /* 21 */
|
||||
GG(d, a, b, c, x[10], 9, 0x2441453); /* 22 */
|
||||
GG(c, d, a, b, x[15], 14, 0xd8a1e681); /* 23 */
|
||||
GG(b, c, d, a, x[ 4], 20, 0xe7d3fbc8); /* 24 */
|
||||
GG(a, b, c, d, x[ 9], 5, 0x21e1cde6); /* 25 */
|
||||
GG(d, a, b, c, x[14], 9, 0xc33707d6); /* 26 */
|
||||
GG(c, d, a, b, x[ 3], 14, 0xf4d50d87); /* 27 */
|
||||
GG(b, c, d, a, x[ 8], 20, 0x455a14ed); /* 28 */
|
||||
GG(a, b, c, d, x[13], 5, 0xa9e3e905); /* 29 */
|
||||
GG(d, a, b, c, x[ 2], 9, 0xfcefa3f8); /* 30 */
|
||||
GG(c, d, a, b, x[ 7], 14, 0x676f02d9); /* 31 */
|
||||
GG(b, c, d, a, x[12], 20, 0x8d2a4c8a); /* 32 */
|
||||
|
||||
/* Round 3 */
|
||||
HH(a, b, c, d, x[ 5], 4, 0xfffa3942); /* 33 */
|
||||
HH(d, a, b, c, x[ 8], 11, 0x8771f681); /* 34 */
|
||||
HH(c, d, a, b, x[11], 16, 0x6d9d6122); /* 35 */
|
||||
HH(b, c, d, a, x[14], 23, 0xfde5380c); /* 36 */
|
||||
HH(a, b, c, d, x[ 1], 4, 0xa4beea44); /* 37 */
|
||||
HH(d, a, b, c, x[ 4], 11, 0x4bdecfa9); /* 38 */
|
||||
HH(c, d, a, b, x[ 7], 16, 0xf6bb4b60); /* 39 */
|
||||
HH(b, c, d, a, x[10], 23, 0xbebfbc70); /* 40 */
|
||||
HH(a, b, c, d, x[13], 4, 0x289b7ec6); /* 41 */
|
||||
HH(d, a, b, c, x[ 0], 11, 0xeaa127fa); /* 42 */
|
||||
HH(c, d, a, b, x[ 3], 16, 0xd4ef3085); /* 43 */
|
||||
HH(b, c, d, a, x[ 6], 23, 0x4881d05); /* 44 */
|
||||
HH(a, b, c, d, x[ 9], 4, 0xd9d4d039); /* 45 */
|
||||
HH(d, a, b, c, x[12], 11, 0xe6db99e5); /* 46 */
|
||||
HH(c, d, a, b, x[15], 16, 0x1fa27cf8); /* 47 */
|
||||
HH(b, c, d, a, x[ 2], 23, 0xc4ac5665); /* 48 */
|
||||
|
||||
/* Round 4 */
|
||||
II(a, b, c, d, x[ 0], 6, 0xf4292244); /* 49 */
|
||||
II(d, a, b, c, x[ 7], 10, 0x432aff97); /* 50 */
|
||||
II(c, d, a, b, x[14], 15, 0xab9423a7); /* 51 */
|
||||
II(b, c, d, a, x[ 5], 21, 0xfc93a039); /* 52 */
|
||||
II(a, b, c, d, x[12], 6, 0x655b59c3); /* 53 */
|
||||
II(d, a, b, c, x[ 3], 10, 0x8f0ccc92); /* 54 */
|
||||
II(c, d, a, b, x[10], 15, 0xffeff47d); /* 55 */
|
||||
II(b, c, d, a, x[ 1], 21, 0x85845dd1); /* 56 */
|
||||
II(a, b, c, d, x[ 8], 6, 0x6fa87e4f); /* 57 */
|
||||
II(d, a, b, c, x[15], 10, 0xfe2ce6e0); /* 58 */
|
||||
II(c, d, a, b, x[ 6], 15, 0xa3014314); /* 59 */
|
||||
II(b, c, d, a, x[13], 21, 0x4e0811a1); /* 60 */
|
||||
II(a, b, c, d, x[ 4], 6, 0xf7537e82); /* 61 */
|
||||
II(d, a, b, c, x[11], 10, 0xbd3af235); /* 62 */
|
||||
II(c, d, a, b, x[ 2], 15, 0x2ad7d2bb); /* 63 */
|
||||
II(b, c, d, a, x[ 9], 21, 0xeb86d391); /* 64 */
|
||||
state[0] += a;
|
||||
state[1] += b;
|
||||
state[2] += c;
|
||||
state[3] += d;
|
||||
unsigned int a = state[0];
|
||||
unsigned int b = state[1];
|
||||
unsigned int c = state[2];
|
||||
unsigned int d = state[3];
|
||||
unsigned int x[64];
|
||||
MD5Decode(x, block, 64);
|
||||
FF(a, b, c, d, x[0], 7, 0xd76aa478); /* 1 */
|
||||
FF(d, a, b, c, x[1], 12, 0xe8c7b756); /* 2 */
|
||||
FF(c, d, a, b, x[2], 17, 0x242070db); /* 3 */
|
||||
FF(b, c, d, a, x[3], 22, 0xc1bdceee); /* 4 */
|
||||
FF(a, b, c, d, x[4], 7, 0xf57c0faf); /* 5 */
|
||||
FF(d, a, b, c, x[5], 12, 0x4787c62a); /* 6 */
|
||||
FF(c, d, a, b, x[6], 17, 0xa8304613); /* 7 */
|
||||
FF(b, c, d, a, x[7], 22, 0xfd469501); /* 8 */
|
||||
FF(a, b, c, d, x[8], 7, 0x698098d8); /* 9 */
|
||||
FF(d, a, b, c, x[9], 12, 0x8b44f7af); /* 10 */
|
||||
FF(c, d, a, b, x[10], 17, 0xffff5bb1); /* 11 */
|
||||
FF(b, c, d, a, x[11], 22, 0x895cd7be); /* 12 */
|
||||
FF(a, b, c, d, x[12], 7, 0x6b901122); /* 13 */
|
||||
FF(d, a, b, c, x[13], 12, 0xfd987193); /* 14 */
|
||||
FF(c, d, a, b, x[14], 17, 0xa679438e); /* 15 */
|
||||
FF(b, c, d, a, x[15], 22, 0x49b40821); /* 16 */
|
||||
|
||||
/* Round 2 */
|
||||
GG(a, b, c, d, x[1], 5, 0xf61e2562); /* 17 */
|
||||
GG(d, a, b, c, x[6], 9, 0xc040b340); /* 18 */
|
||||
GG(c, d, a, b, x[11], 14, 0x265e5a51); /* 19 */
|
||||
GG(b, c, d, a, x[0], 20, 0xe9b6c7aa); /* 20 */
|
||||
GG(a, b, c, d, x[5], 5, 0xd62f105d); /* 21 */
|
||||
GG(d, a, b, c, x[10], 9, 0x2441453); /* 22 */
|
||||
GG(c, d, a, b, x[15], 14, 0xd8a1e681); /* 23 */
|
||||
GG(b, c, d, a, x[4], 20, 0xe7d3fbc8); /* 24 */
|
||||
GG(a, b, c, d, x[9], 5, 0x21e1cde6); /* 25 */
|
||||
GG(d, a, b, c, x[14], 9, 0xc33707d6); /* 26 */
|
||||
GG(c, d, a, b, x[3], 14, 0xf4d50d87); /* 27 */
|
||||
GG(b, c, d, a, x[8], 20, 0x455a14ed); /* 28 */
|
||||
GG(a, b, c, d, x[13], 5, 0xa9e3e905); /* 29 */
|
||||
GG(d, a, b, c, x[2], 9, 0xfcefa3f8); /* 30 */
|
||||
GG(c, d, a, b, x[7], 14, 0x676f02d9); /* 31 */
|
||||
GG(b, c, d, a, x[12], 20, 0x8d2a4c8a); /* 32 */
|
||||
|
||||
/* Round 3 */
|
||||
HH(a, b, c, d, x[5], 4, 0xfffa3942); /* 33 */
|
||||
HH(d, a, b, c, x[8], 11, 0x8771f681); /* 34 */
|
||||
HH(c, d, a, b, x[11], 16, 0x6d9d6122); /* 35 */
|
||||
HH(b, c, d, a, x[14], 23, 0xfde5380c); /* 36 */
|
||||
HH(a, b, c, d, x[1], 4, 0xa4beea44); /* 37 */
|
||||
HH(d, a, b, c, x[4], 11, 0x4bdecfa9); /* 38 */
|
||||
HH(c, d, a, b, x[7], 16, 0xf6bb4b60); /* 39 */
|
||||
HH(b, c, d, a, x[10], 23, 0xbebfbc70); /* 40 */
|
||||
HH(a, b, c, d, x[13], 4, 0x289b7ec6); /* 41 */
|
||||
HH(d, a, b, c, x[0], 11, 0xeaa127fa); /* 42 */
|
||||
HH(c, d, a, b, x[3], 16, 0xd4ef3085); /* 43 */
|
||||
HH(b, c, d, a, x[6], 23, 0x4881d05); /* 44 */
|
||||
HH(a, b, c, d, x[9], 4, 0xd9d4d039); /* 45 */
|
||||
HH(d, a, b, c, x[12], 11, 0xe6db99e5); /* 46 */
|
||||
HH(c, d, a, b, x[15], 16, 0x1fa27cf8); /* 47 */
|
||||
HH(b, c, d, a, x[2], 23, 0xc4ac5665); /* 48 */
|
||||
|
||||
/* Round 4 */
|
||||
II(a, b, c, d, x[0], 6, 0xf4292244); /* 49 */
|
||||
II(d, a, b, c, x[7], 10, 0x432aff97); /* 50 */
|
||||
II(c, d, a, b, x[14], 15, 0xab9423a7); /* 51 */
|
||||
II(b, c, d, a, x[5], 21, 0xfc93a039); /* 52 */
|
||||
II(a, b, c, d, x[12], 6, 0x655b59c3); /* 53 */
|
||||
II(d, a, b, c, x[3], 10, 0x8f0ccc92); /* 54 */
|
||||
II(c, d, a, b, x[10], 15, 0xffeff47d); /* 55 */
|
||||
II(b, c, d, a, x[1], 21, 0x85845dd1); /* 56 */
|
||||
II(a, b, c, d, x[8], 6, 0x6fa87e4f); /* 57 */
|
||||
II(d, a, b, c, x[15], 10, 0xfe2ce6e0); /* 58 */
|
||||
II(c, d, a, b, x[6], 15, 0xa3014314); /* 59 */
|
||||
II(b, c, d, a, x[13], 21, 0x4e0811a1); /* 60 */
|
||||
II(a, b, c, d, x[4], 6, 0xf7537e82); /* 61 */
|
||||
II(d, a, b, c, x[11], 10, 0xbd3af235); /* 62 */
|
||||
II(c, d, a, b, x[2], 15, 0x2ad7d2bb); /* 63 */
|
||||
II(b, c, d, a, x[9], 21, 0xeb86d391); /* 64 */
|
||||
state[0] += a;
|
||||
state[1] += b;
|
||||
state[2] += c;
|
||||
state[3] += d;
|
||||
}
|
||||
|
||||
@@ -1,48 +1,46 @@
|
||||
#ifndef MD5_H
|
||||
#define MD5_H
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int count[2];
|
||||
unsigned int state[4];
|
||||
unsigned char buffer[64];
|
||||
}MD5_CTX;
|
||||
|
||||
|
||||
#define F(x,y,z) ((x & y) | (~x & z))
|
||||
#define G(x,y,z) ((x & z) | (y & ~z))
|
||||
#define H(x,y,z) (x^y^z)
|
||||
#define I(x,y,z) (y ^ (x | ~z))
|
||||
#define ROTATE_LEFT(x,n) ((x << n) | (x >> (32-n)))
|
||||
#define FF(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += F(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
#define GG(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += G(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
#define HH(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += H(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
#define II(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += I(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
unsigned int count[2];
|
||||
unsigned int state[4];
|
||||
unsigned char buffer[64];
|
||||
} MD5_CTX;
|
||||
|
||||
#define F(x, y, z) ((x & y) | (~x & z))
|
||||
#define G(x, y, z) ((x & z) | (y & ~z))
|
||||
#define H(x, y, z) (x ^ y ^ z)
|
||||
#define I(x, y, z) (y ^ (x | ~z))
|
||||
#define ROTATE_LEFT(x, n) ((x << n) | (x >> (32 - n)))
|
||||
#define FF(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += F(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
#define GG(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += G(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
#define HH(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += H(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
#define II(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += I(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
void MD5Init(MD5_CTX *context);
|
||||
void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen);
|
||||
void MD5Final(MD5_CTX *context,unsigned char digest[16]);
|
||||
void MD5Transform(unsigned int state[4],unsigned char block[64]);
|
||||
void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len);
|
||||
void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len);
|
||||
|
||||
void MD5Update(MD5_CTX *context, unsigned char *input, unsigned int inputlen);
|
||||
void MD5Final(MD5_CTX *context, unsigned char digest[16]);
|
||||
void MD5Transform(unsigned int state[4], unsigned char block[64]);
|
||||
void MD5Encode(unsigned char *output, unsigned int *input, unsigned int len);
|
||||
void MD5Decode(unsigned int *output, unsigned char *input, unsigned int len);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
#define RWNX_VERS_REV "241c091M (master)"
|
||||
#define RWNX_VERS_MOD "6.4.3.0"
|
||||
#define RWNX_VERS_BANNER "rwnx v6.4.3.0 - - 241c091M (master)"
|
||||
#define RELEASE_DATE "2024_0615_c3cb37b3"
|
||||
#define RELEASE_DATE "2025_0410_b99ca8b6"
|
||||
|
||||
@@ -53,22 +53,20 @@
|
||||
#undef BT_DBG
|
||||
#undef BT_ERR
|
||||
#ifdef BT_SLEEP_DBG
|
||||
#define BT_DBG(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n",\
|
||||
__func__, ## arg)
|
||||
#define BT_DBG(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n", __func__, ##arg)
|
||||
#else
|
||||
#define BT_DBG(fmt, arg...)
|
||||
#endif
|
||||
#define BT_ERR(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n",\
|
||||
__func__, ## arg)
|
||||
#define BT_ERR(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n", __func__, ##arg)
|
||||
|
||||
/*
|
||||
* Defines
|
||||
*/
|
||||
|
||||
#define VERSION "1.3.3"
|
||||
#define PROC_DIR "bluetooth/sleep"
|
||||
#define VERSION "1.3.3"
|
||||
#define PROC_DIR "bluetooth/sleep"
|
||||
|
||||
#define DEFAULT_UART_INDEX 1
|
||||
#define DEFAULT_UART_INDEX 1
|
||||
#define BT_BLUEDROID_SUPPORT 1
|
||||
static int bluesleep_start(void);
|
||||
static void bluesleep_stop(void);
|
||||
@@ -84,8 +82,8 @@ struct bluesleep_info {
|
||||
struct wake_lock wake_lock;
|
||||
#endif
|
||||
struct uart_port *uport;
|
||||
unsigned host_wake_assert:1;
|
||||
unsigned ext_wake_assert:1;
|
||||
unsigned host_wake_assert : 1;
|
||||
unsigned ext_wake_assert : 1;
|
||||
struct platform_device *pdev;
|
||||
};
|
||||
|
||||
@@ -97,21 +95,21 @@ static void bluesleep_tx_allow_sleep(void);
|
||||
DECLARE_DELAYED_WORK(sleep_workqueue, bluesleep_sleep_work);
|
||||
|
||||
/* Macros for handling sleep work */
|
||||
#define bluesleep_rx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_rx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_rx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_rx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
|
||||
/* 1 second timeout */
|
||||
#define RX_TIMER_INTERVAL 1
|
||||
#define RX_TIMER_INTERVAL 1
|
||||
|
||||
/* state variable names and bit positions */
|
||||
#define BT_PROTO 0x01
|
||||
#define BT_TXDATA 0x02
|
||||
#define BT_ASLEEP 0x04
|
||||
#define BT_TXIDLE 0x08
|
||||
#define BT_PAUSE 0x09
|
||||
#define BT_RXTIMER 0x0a
|
||||
#define BT_PROTO 0x01
|
||||
#define BT_TXDATA 0x02
|
||||
#define BT_ASLEEP 0x04
|
||||
#define BT_TXIDLE 0x08
|
||||
#define BT_PAUSE 0x09
|
||||
#define BT_RXTIMER 0x0a
|
||||
|
||||
#if BT_BLUEDROID_SUPPORT
|
||||
static bool has_lpm_enabled;
|
||||
@@ -133,8 +131,8 @@ static atomic_t open_count = ATOMIC_INIT(1);
|
||||
*/
|
||||
|
||||
#if !BT_BLUEDROID_SUPPORT
|
||||
static int bluesleep_hci_event(struct notifier_block *this,
|
||||
unsigned long event, void *data);
|
||||
static int bluesleep_hci_event(struct notifier_block *this, unsigned long event,
|
||||
void *data);
|
||||
#endif
|
||||
|
||||
/*
|
||||
@@ -182,7 +180,8 @@ static void hsuart_power(int on)
|
||||
else
|
||||
bsi->uport->ops->set_mctrl(bsi->uport, 0);
|
||||
} else {
|
||||
BT_ERR("bsi->uport = NULL, has_lpm_enabled = %d", has_lpm_enabled);
|
||||
BT_ERR("bsi->uport = NULL, has_lpm_enabled = %d",
|
||||
has_lpm_enabled);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -195,8 +194,8 @@ static inline int bluesleep_can_sleep(void)
|
||||
* are both deasserted
|
||||
*/
|
||||
return (gpio_get_value(bsi->ext_wake) != bsi->ext_wake_assert) &&
|
||||
(gpio_get_value(bsi->host_wake) != bsi->host_wake_assert) &&
|
||||
(!test_bit(BT_RXTIMER, &flags)) && (bsi->uport != NULL);
|
||||
(gpio_get_value(bsi->host_wake) != bsi->host_wake_assert) &&
|
||||
(!test_bit(BT_RXTIMER, &flags)) && (bsi->uport != NULL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -248,12 +247,13 @@ static void bluesleep_sleep_work(struct work_struct *work)
|
||||
mod_timer(&rx_timer, jiffies + (RX_TIMER_INTERVAL * HZ));
|
||||
set_bit(BT_RXTIMER, &flags);
|
||||
|
||||
if(test_bit(BT_PAUSE, &flags)){
|
||||
if (test_bit(BT_PAUSE, &flags)) {
|
||||
BT_DBG("rx wake du BT_PAUSE:%lx", flags);
|
||||
///enable bt sleep immediately
|
||||
gpio_set_value(bsi->ext_wake, !bsi->ext_wake_assert);
|
||||
} else if (gpio_get_value(bsi->ext_wake) != bsi->ext_wake_assert
|
||||
&& !test_bit(BT_TXIDLE, &flags)) {
|
||||
} else if (gpio_get_value(bsi->ext_wake) !=
|
||||
bsi->ext_wake_assert &&
|
||||
!test_bit(BT_TXIDLE, &flags)) {
|
||||
BT_DBG("force retrigger bt wake:%lx", flags);
|
||||
gpio_set_value(bsi->ext_wake, bsi->ext_wake_assert);
|
||||
msleep(20);
|
||||
@@ -318,9 +318,8 @@ static struct uart_port *bluesleep_get_uart_port(void)
|
||||
if (bluesleep_uart_dev) {
|
||||
uport = platform_get_drvdata(bluesleep_uart_dev);
|
||||
if (uport)
|
||||
BT_DBG(
|
||||
"%s get uart_port from blusleep_uart_dev: %s, port irq: %d",
|
||||
__func__, bluesleep_uart_dev->name, uport->irq);
|
||||
BT_DBG("%s get uart_port from blusleep_uart_dev: %s, port irq: %d",
|
||||
__func__, bluesleep_uart_dev->name, uport->irq);
|
||||
}
|
||||
return uport;
|
||||
}
|
||||
@@ -337,8 +336,8 @@ static int bluesleep_lpm_proc_open(struct inode *inode, struct file *file)
|
||||
}
|
||||
|
||||
static ssize_t bluesleep_write_proc_lpm(struct file *file,
|
||||
const char __user *buffer,
|
||||
size_t count, loff_t *pos)
|
||||
const char __user *buffer, size_t count,
|
||||
loff_t *pos)
|
||||
{
|
||||
char b;
|
||||
|
||||
@@ -389,8 +388,8 @@ static int bluesleep_btwrite_proc_open(struct inode *inode, struct file *file)
|
||||
}
|
||||
|
||||
static ssize_t bluesleep_write_proc_btwrite(struct file *file,
|
||||
const char __user *buffer,
|
||||
size_t count, loff_t *pos)
|
||||
const char __user *buffer,
|
||||
size_t count, loff_t *pos)
|
||||
{
|
||||
char b;
|
||||
|
||||
@@ -411,37 +410,37 @@ static ssize_t bluesleep_write_proc_btwrite(struct file *file,
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
|
||||
static const struct proc_ops lpm_fops = {
|
||||
.proc_open = bluesleep_lpm_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_open = bluesleep_lpm_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_release = single_release,
|
||||
.proc_write = bluesleep_write_proc_lpm,
|
||||
.proc_write = bluesleep_write_proc_lpm,
|
||||
};
|
||||
static const struct proc_ops btwrite_fops = {
|
||||
.proc_open = bluesleep_btwrite_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_open = bluesleep_btwrite_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_release = single_release,
|
||||
.proc_write = bluesleep_write_proc_btwrite,
|
||||
.proc_write = bluesleep_write_proc_btwrite,
|
||||
};
|
||||
|
||||
#else
|
||||
|
||||
static const struct file_operations lpm_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_lpm_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_lpm,
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_lpm_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_lpm,
|
||||
};
|
||||
static const struct file_operations btwrite_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_btwrite_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_btwrite,
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_btwrite_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_btwrite,
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -453,10 +452,10 @@ static const struct file_operations btwrite_fops = {
|
||||
* @param data The HCI device associated with the event.
|
||||
* @return <code>NOTIFY_DONE</code>.
|
||||
*/
|
||||
static int bluesleep_hci_event(struct notifier_block *this,
|
||||
unsigned long event, void *data)
|
||||
static int bluesleep_hci_event(struct notifier_block *this, unsigned long event,
|
||||
void *data)
|
||||
{
|
||||
struct hci_dev *hdev = (struct hci_dev *) data;
|
||||
struct hci_dev *hdev = (struct hci_dev *)data;
|
||||
struct hci_uart *hu;
|
||||
struct uart_state *state;
|
||||
|
||||
@@ -467,8 +466,8 @@ static int bluesleep_hci_event(struct notifier_block *this,
|
||||
case HCI_DEV_REG:
|
||||
if (!bluesleep_hdev) {
|
||||
bluesleep_hdev = hdev;
|
||||
hu = (struct hci_uart *) hdev->driver_data;
|
||||
state = (struct uart_state *) hu->tty->driver_data;
|
||||
hu = (struct hci_uart *)hdev->driver_data;
|
||||
state = (struct uart_state *)hu->tty->driver_data;
|
||||
bsi->uport = state->uart_port;
|
||||
}
|
||||
break;
|
||||
@@ -501,7 +500,6 @@ static void bluesleep_tx_allow_sleep(void)
|
||||
spin_unlock_irqrestore(&rw_lock, irq_flags);
|
||||
}
|
||||
|
||||
|
||||
/* Handles reception timer expiration.
|
||||
* Clear BT_RXTIMER.
|
||||
* @param data Not used.
|
||||
@@ -555,7 +553,7 @@ static int bluesleep_start(void)
|
||||
}
|
||||
|
||||
/* start the timer */
|
||||
mod_timer(&rx_timer, jiffies + (RX_TIMER_INTERVAL*HZ));
|
||||
mod_timer(&rx_timer, jiffies + (RX_TIMER_INTERVAL * HZ));
|
||||
/*deassert BT_WAKE first*/
|
||||
gpio_set_value(bsi->ext_wake, !bsi->ext_wake_assert);
|
||||
msleep(20);
|
||||
@@ -563,9 +561,9 @@ static int bluesleep_start(void)
|
||||
/* assert BT_WAKE */
|
||||
gpio_set_value(bsi->ext_wake, bsi->ext_wake_assert);
|
||||
retval = request_irq(bsi->host_wake_irq, bluesleep_hostwake_isr,
|
||||
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
|
||||
"bluetooth hostwake", &bsi->pdev->dev);
|
||||
if (retval < 0) {
|
||||
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
|
||||
"bluetooth hostwake", &bsi->pdev->dev);
|
||||
if (retval < 0) {
|
||||
BT_ERR("Couldn't acquire BT_HOST_WAKE IRQ");
|
||||
goto fail;
|
||||
}
|
||||
@@ -798,7 +796,7 @@ static int __init bluesleep_probe(struct platform_device *pdev)
|
||||
struct aicbsp_feature_t bsp_feature_lpm;
|
||||
|
||||
bsi = devm_kzalloc(&pdev->dev, sizeof(struct bluesleep_info),
|
||||
GFP_KERNEL);
|
||||
GFP_KERNEL);
|
||||
if (!bsi)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -816,23 +814,24 @@ static int __init bluesleep_probe(struct platform_device *pdev)
|
||||
else
|
||||
bsi->host_wake_assert = (config == OF_GPIO_ACTIVE_LOW) ? 1 : 0;
|
||||
|
||||
BT_DBG("bt_hostwake gpio=%d assert=%d\n", bsi->host_wake, bsi->host_wake_assert);
|
||||
BT_DBG("bt_hostwake gpio=%d assert=%d\n", bsi->host_wake,
|
||||
bsi->host_wake_assert);
|
||||
|
||||
if (assert_level != -1) {
|
||||
bsi->host_wake_assert = (assert_level & 0x02) > 0;
|
||||
BT_DBG("override host_wake assert to %d", bsi->host_wake_assert);
|
||||
BT_DBG("override host_wake assert to %d",
|
||||
bsi->host_wake_assert);
|
||||
}
|
||||
|
||||
ret = devm_gpio_request(dev, bsi->host_wake, "bt_hostwake");
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request bt_hostwake gpio %d\n",
|
||||
bsi->host_wake);
|
||||
BT_ERR("can't request bt_hostwake gpio %d\n", bsi->host_wake);
|
||||
goto err0;
|
||||
}
|
||||
ret = gpio_direction_input(bsi->host_wake);
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request input direction bt_wake gpio %d\n",
|
||||
bsi->host_wake);
|
||||
bsi->host_wake);
|
||||
goto err1;
|
||||
}
|
||||
|
||||
@@ -840,7 +839,7 @@ static int __init bluesleep_probe(struct platform_device *pdev)
|
||||
if (!of_property_read_bool(np, "wakeup-source")) {
|
||||
#else
|
||||
if (!of_property_read_u32(np, "wakeup-source", &bsi->wakeup_enable) &&
|
||||
(bsi->wakeup_enable == 0)) {
|
||||
(bsi->wakeup_enable == 0)) {
|
||||
#endif
|
||||
BT_DBG("wakeup source is disabled!\n");
|
||||
} else {
|
||||
@@ -853,12 +852,12 @@ static int __init bluesleep_probe(struct platform_device *pdev)
|
||||
ret = dev_pm_set_wake_irq(dev, gpio_to_irq(bsi->host_wake));
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't enable wakeup src for bt_hostwake %d\n",
|
||||
bsi->host_wake);
|
||||
bsi->host_wake);
|
||||
goto err2;
|
||||
}
|
||||
bsi->wakeup_enable = 1;
|
||||
#else
|
||||
BT_ERR("%s kernel unsupport this feature!\r\n", __func__);
|
||||
BT_ERR("%s kernel unsupport this feature!\r\n", __func__);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -871,14 +870,14 @@ static int __init bluesleep_probe(struct platform_device *pdev)
|
||||
|
||||
ret = devm_gpio_request(dev, bsi->ext_wake, "bt_wake");
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request bt_wake gpio %d\n",
|
||||
bsi->ext_wake);
|
||||
BT_ERR("can't request bt_wake gpio %d\n", bsi->ext_wake);
|
||||
goto err2;
|
||||
}
|
||||
|
||||
/* set ext_wake_assert */
|
||||
bsi->ext_wake_assert = (config == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
|
||||
BT_DBG("bt_wake gpio=%d assert=%d\n", bsi->ext_wake, bsi->ext_wake_assert);
|
||||
BT_DBG("bt_wake gpio=%d assert=%d\n", bsi->ext_wake,
|
||||
bsi->ext_wake_assert);
|
||||
|
||||
if (assert_level != -1) {
|
||||
bsi->ext_wake_assert = (assert_level & 0x01) > 0;
|
||||
@@ -889,7 +888,7 @@ static int __init bluesleep_probe(struct platform_device *pdev)
|
||||
ret = gpio_direction_output(bsi->ext_wake, bsi->ext_wake_assert);
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request output direction bt_wake gpio %d\n",
|
||||
bsi->ext_wake);
|
||||
bsi->ext_wake);
|
||||
goto err3;
|
||||
}
|
||||
/*set ext_wake deassert as default*/
|
||||
@@ -899,7 +898,7 @@ static int __init bluesleep_probe(struct platform_device *pdev)
|
||||
bsi->host_wake_irq = gpio_to_irq(bsi->host_wake);
|
||||
if (bsi->host_wake_irq < 0) {
|
||||
BT_ERR("map gpio [%d] to virq failed, errno = %d\n",
|
||||
bsi->host_wake, bsi->host_wake_irq);
|
||||
bsi->host_wake, bsi->host_wake_irq);
|
||||
ret = -ENODEV;
|
||||
goto err3;
|
||||
}
|
||||
|
||||
@@ -8,11 +8,11 @@
|
||||
#include "lpm.h"
|
||||
#include "rfkill.h"
|
||||
|
||||
#define DRV_CONFIG_FW_NAME "fw.bin"
|
||||
#define DRV_DESCRIPTION "AIC BLUETOOTH"
|
||||
#define DRV_COPYRIGHT "Copyright(c) 2015-2020 AICSemi"
|
||||
#define DRV_AUTHOR "AICSemi"
|
||||
#define DRV_VERS_MOD "1.0"
|
||||
#define DRV_CONFIG_FW_NAME "fw.bin"
|
||||
#define DRV_DESCRIPTION "AIC BLUETOOTH"
|
||||
#define DRV_COPYRIGHT "Copyright(c) 2015-2020 AICSemi"
|
||||
#define DRV_AUTHOR "AICSemi"
|
||||
#define DRV_VERS_MOD "1.0"
|
||||
|
||||
static struct platform_device *aicbt_pdev;
|
||||
|
||||
@@ -47,7 +47,8 @@ static int __init aic_bluetooth_mod_init(void)
|
||||
pr_err("rfkill init fail\n");
|
||||
goto err1;
|
||||
}
|
||||
#if defined(ANDROID_PLATFORM) && !defined(CONFIG_PLATFORM_ROCKCHIP) && !defined(CONFIG_PLATFORM_ROCKCHIP2)
|
||||
#if defined(ANDROID_PLATFORM) && !defined(CONFIG_PLATFORM_ROCKCHIP) && \
|
||||
!defined(CONFIG_PLATFORM_ROCKCHIP2)
|
||||
ret = bluesleep_init(aicbt_pdev);
|
||||
if (ret) {
|
||||
pr_err("bluesleep init fail\n");
|
||||
@@ -57,7 +58,8 @@ static int __init aic_bluetooth_mod_init(void)
|
||||
|
||||
return 0;
|
||||
|
||||
#if defined(ANDROID_PLATFORM) && !defined(CONFIG_PLATFORM_ROCKCHIP) && !defined(CONFIG_PLATFORM_ROCKCHIP2)
|
||||
#if defined(ANDROID_PLATFORM) && !defined(CONFIG_PLATFORM_ROCKCHIP) && \
|
||||
!defined(CONFIG_PLATFORM_ROCKCHIP2)
|
||||
err2:
|
||||
#endif
|
||||
rfkill_bluetooth_remove(aicbt_pdev);
|
||||
@@ -71,7 +73,8 @@ err0:
|
||||
static void __exit aic_bluetooth_mod_exit(void)
|
||||
{
|
||||
printk("%s\n", __func__);
|
||||
#if defined(ANDROID_PLATFORM) && !defined(CONFIG_PLATFORM_ROCKCHIP) && !defined(CONFIG_PLATFORM_ROCKCHIP2)
|
||||
#if defined(ANDROID_PLATFORM) && !defined(CONFIG_PLATFORM_ROCKCHIP) && \
|
||||
!defined(CONFIG_PLATFORM_ROCKCHIP2)
|
||||
bluesleep_exit(aicbt_pdev);
|
||||
#endif
|
||||
rfkill_bluetooth_remove(aicbt_pdev);
|
||||
|
||||
@@ -1,15 +1,15 @@
|
||||
#ifndef __AIC_BSP_EXPORT_H
|
||||
#define __AIC_BSP_EXPORT_H
|
||||
|
||||
#define AIC_BLUETOOTH 0
|
||||
#define AIC_WIFI 1
|
||||
#define AIC_PWR_OFF 0
|
||||
#define AIC_PWR_ON 1
|
||||
#define AIC_BLUETOOTH 0
|
||||
#define AIC_WIFI 1
|
||||
#define AIC_PWR_OFF 0
|
||||
#define AIC_PWR_ON 1
|
||||
|
||||
struct aicbsp_feature_t {
|
||||
bool band_5g_support;
|
||||
uint32_t sdio_clock;
|
||||
uint8_t sdio_phase;
|
||||
uint8_t sdio_phase;
|
||||
uint8_t irqf;
|
||||
};
|
||||
|
||||
|
||||
@@ -52,22 +52,20 @@
|
||||
#undef BT_DBG
|
||||
#undef BT_ERR
|
||||
#ifdef BT_SLEEP_DBG
|
||||
#define BT_DBG(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n",\
|
||||
__func__, ## arg)
|
||||
#define BT_DBG(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n", __func__, ##arg)
|
||||
#else
|
||||
#define BT_DBG(fmt, arg...)
|
||||
#endif
|
||||
#define BT_ERR(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n",\
|
||||
__func__, ## arg)
|
||||
#define BT_ERR(fmt, arg...) pr_debug("[BT_LPM] %s: " fmt "\n", __func__, ##arg)
|
||||
|
||||
/*
|
||||
* Defines
|
||||
*/
|
||||
|
||||
#define VERSION "1.3.3"
|
||||
#define PROC_DIR "bluetooth/sleep"
|
||||
#define VERSION "1.3.3"
|
||||
#define PROC_DIR "bluetooth/sleep"
|
||||
|
||||
#define DEFAULT_UART_INDEX 1
|
||||
#define DEFAULT_UART_INDEX 1
|
||||
#define BT_BLUEDROID_SUPPORT 1
|
||||
static int bluesleep_start(void);
|
||||
static void bluesleep_stop(void);
|
||||
@@ -83,8 +81,8 @@ struct bluesleep_info {
|
||||
struct wake_lock wake_lock;
|
||||
#endif
|
||||
struct uart_port *uport;
|
||||
unsigned host_wake_assert:1;
|
||||
unsigned ext_wake_assert:1;
|
||||
unsigned host_wake_assert : 1;
|
||||
unsigned ext_wake_assert : 1;
|
||||
struct platform_device *pdev;
|
||||
};
|
||||
|
||||
@@ -96,20 +94,20 @@ static void bluesleep_tx_allow_sleep(void);
|
||||
DECLARE_DELAYED_WORK(sleep_workqueue, bluesleep_sleep_work);
|
||||
|
||||
/* Macros for handling sleep work */
|
||||
#define bluesleep_rx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_rx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_rx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_busy() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_rx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
#define bluesleep_tx_idle() schedule_delayed_work(&sleep_workqueue, 0)
|
||||
|
||||
/* 1 second timeout */
|
||||
#define RX_TIMER_INTERVAL 1
|
||||
#define RX_TIMER_INTERVAL 1
|
||||
|
||||
/* state variable names and bit positions */
|
||||
#define BT_PROTO 0x01
|
||||
#define BT_TXDATA 0x02
|
||||
#define BT_ASLEEP 0x04
|
||||
#define BT_RXTIMER 0x20
|
||||
#define BT_TXIDLE 0x08
|
||||
#define BT_PROTO 0x01
|
||||
#define BT_TXDATA 0x02
|
||||
#define BT_ASLEEP 0x04
|
||||
#define BT_RXTIMER 0x20
|
||||
#define BT_TXIDLE 0x08
|
||||
|
||||
#if BT_BLUEDROID_SUPPORT
|
||||
static bool has_lpm_enabled;
|
||||
@@ -131,8 +129,8 @@ static atomic_t open_count = ATOMIC_INIT(1);
|
||||
*/
|
||||
|
||||
#if !BT_BLUEDROID_SUPPORT
|
||||
static int bluesleep_hci_event(struct notifier_block *this,
|
||||
unsigned long event, void *data);
|
||||
static int bluesleep_hci_event(struct notifier_block *this, unsigned long event,
|
||||
void *data);
|
||||
#endif
|
||||
|
||||
/*
|
||||
@@ -180,7 +178,8 @@ static void hsuart_power(int on)
|
||||
else
|
||||
bsi->uport->ops->set_mctrl(bsi->uport, 0);
|
||||
} else {
|
||||
BT_ERR("bsi->uport = NULL, has_lpm_enabled = %d", has_lpm_enabled);
|
||||
BT_ERR("bsi->uport = NULL, has_lpm_enabled = %d",
|
||||
has_lpm_enabled);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -193,8 +192,8 @@ static inline int bluesleep_can_sleep(void)
|
||||
* are both deasserted
|
||||
*/
|
||||
return (gpio_get_value(bsi->ext_wake) != bsi->ext_wake_assert) &&
|
||||
(gpio_get_value(bsi->host_wake) != bsi->host_wake_assert) &&
|
||||
(!test_bit(BT_RXTIMER, &flags)) && (bsi->uport != NULL);
|
||||
(gpio_get_value(bsi->host_wake) != bsi->host_wake_assert) &&
|
||||
(!test_bit(BT_RXTIMER, &flags)) && (bsi->uport != NULL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -244,8 +243,8 @@ static void bluesleep_sleep_work(struct work_struct *work)
|
||||
hsuart_power(1);
|
||||
} else {
|
||||
mod_timer(&rx_timer, jiffies + (RX_TIMER_INTERVAL * HZ));
|
||||
if (gpio_get_value(bsi->ext_wake) != bsi->ext_wake_assert
|
||||
&& !test_bit(BT_TXIDLE, &flags)) {
|
||||
if (gpio_get_value(bsi->ext_wake) != bsi->ext_wake_assert &&
|
||||
!test_bit(BT_TXIDLE, &flags)) {
|
||||
BT_DBG("force retrigger bt wake:%lx", flags);
|
||||
gpio_set_value(bsi->ext_wake, bsi->ext_wake_assert);
|
||||
msleep(20);
|
||||
@@ -310,9 +309,8 @@ static struct uart_port *bluesleep_get_uart_port(void)
|
||||
if (bluesleep_uart_dev) {
|
||||
uport = platform_get_drvdata(bluesleep_uart_dev);
|
||||
if (uport)
|
||||
BT_DBG(
|
||||
"%s get uart_port from blusleep_uart_dev: %s, port irq: %d",
|
||||
__func__, bluesleep_uart_dev->name, uport->irq);
|
||||
BT_DBG("%s get uart_port from blusleep_uart_dev: %s, port irq: %d",
|
||||
__func__, bluesleep_uart_dev->name, uport->irq);
|
||||
}
|
||||
return uport;
|
||||
}
|
||||
@@ -329,8 +327,8 @@ static int bluesleep_lpm_proc_open(struct inode *inode, struct file *file)
|
||||
}
|
||||
|
||||
static ssize_t bluesleep_write_proc_lpm(struct file *file,
|
||||
const char __user *buffer,
|
||||
size_t count, loff_t *pos)
|
||||
const char __user *buffer, size_t count,
|
||||
loff_t *pos)
|
||||
{
|
||||
char b;
|
||||
|
||||
@@ -372,8 +370,8 @@ static int bluesleep_btwrite_proc_open(struct inode *inode, struct file *file)
|
||||
}
|
||||
|
||||
static ssize_t bluesleep_write_proc_btwrite(struct file *file,
|
||||
const char __user *buffer,
|
||||
size_t count, loff_t *pos)
|
||||
const char __user *buffer,
|
||||
size_t count, loff_t *pos)
|
||||
{
|
||||
char b;
|
||||
|
||||
@@ -394,35 +392,35 @@ static ssize_t bluesleep_write_proc_btwrite(struct file *file,
|
||||
|
||||
#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 10, 0)
|
||||
static const struct proc_ops lpm_fops = {
|
||||
.proc_open = bluesleep_lpm_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_release = single_release,
|
||||
.proc_write = bluesleep_write_proc_lpm,
|
||||
.proc_open = bluesleep_lpm_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_release = single_release,
|
||||
.proc_write = bluesleep_write_proc_lpm,
|
||||
};
|
||||
static const struct proc_ops btwrite_fops = {
|
||||
.proc_open = bluesleep_btwrite_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_release = single_release,
|
||||
.proc_write = bluesleep_write_proc_btwrite,
|
||||
.proc_open = bluesleep_btwrite_proc_open,
|
||||
.proc_read = seq_read,
|
||||
.proc_lseek = seq_lseek,
|
||||
.proc_release = single_release,
|
||||
.proc_write = bluesleep_write_proc_btwrite,
|
||||
};
|
||||
#else
|
||||
static const struct file_operations lpm_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_lpm_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_lpm,
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_lpm_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_lpm,
|
||||
};
|
||||
static const struct file_operations btwrite_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_btwrite_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_btwrite,
|
||||
.owner = THIS_MODULE,
|
||||
.open = bluesleep_btwrite_proc_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = bluesleep_write_proc_btwrite,
|
||||
};
|
||||
#endif
|
||||
#else
|
||||
@@ -433,10 +431,10 @@ static const struct file_operations btwrite_fops = {
|
||||
* @param data The HCI device associated with the event.
|
||||
* @return <code>NOTIFY_DONE</code>.
|
||||
*/
|
||||
static int bluesleep_hci_event(struct notifier_block *this,
|
||||
unsigned long event, void *data)
|
||||
static int bluesleep_hci_event(struct notifier_block *this, unsigned long event,
|
||||
void *data)
|
||||
{
|
||||
struct hci_dev *hdev = (struct hci_dev *) data;
|
||||
struct hci_dev *hdev = (struct hci_dev *)data;
|
||||
struct hci_uart *hu;
|
||||
struct uart_state *state;
|
||||
|
||||
@@ -447,8 +445,8 @@ static int bluesleep_hci_event(struct notifier_block *this,
|
||||
case HCI_DEV_REG:
|
||||
if (!bluesleep_hdev) {
|
||||
bluesleep_hdev = hdev;
|
||||
hu = (struct hci_uart *) hdev->driver_data;
|
||||
state = (struct uart_state *) hu->tty->driver_data;
|
||||
hu = (struct hci_uart *)hdev->driver_data;
|
||||
state = (struct uart_state *)hu->tty->driver_data;
|
||||
bsi->uport = state->uart_port;
|
||||
}
|
||||
break;
|
||||
@@ -480,7 +478,6 @@ static void bluesleep_tx_allow_sleep(void)
|
||||
spin_unlock_irqrestore(&rw_lock, irq_flags);
|
||||
}
|
||||
|
||||
|
||||
/* Handles reception timer expiration.
|
||||
* Clear BT_RXTIMER.
|
||||
* @param data Not used.
|
||||
@@ -534,7 +531,7 @@ static int bluesleep_start(void)
|
||||
}
|
||||
|
||||
/* start the timer */
|
||||
mod_timer(&rx_timer, jiffies + (RX_TIMER_INTERVAL*HZ));
|
||||
mod_timer(&rx_timer, jiffies + (RX_TIMER_INTERVAL * HZ));
|
||||
/*deassert BT_WAKE first*/
|
||||
gpio_set_value(bsi->ext_wake, !bsi->ext_wake_assert);
|
||||
msleep(20);
|
||||
@@ -542,9 +539,9 @@ static int bluesleep_start(void)
|
||||
/* assert BT_WAKE */
|
||||
gpio_set_value(bsi->ext_wake, bsi->ext_wake_assert);
|
||||
retval = request_irq(bsi->host_wake_irq, bluesleep_hostwake_isr,
|
||||
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
|
||||
"bluetooth hostwake", &bsi->pdev->dev);
|
||||
if (retval < 0) {
|
||||
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
|
||||
"bluetooth hostwake", &bsi->pdev->dev);
|
||||
if (retval < 0) {
|
||||
BT_ERR("Couldn't acquire BT_HOST_WAKE IRQ");
|
||||
goto fail;
|
||||
}
|
||||
@@ -772,14 +769,15 @@ static struct platform_device *sw_uart_get_pdev(int id)
|
||||
static int bluesleep_probe(struct platform_device *pdev)
|
||||
{
|
||||
#if 1
|
||||
struct device_node *np = of_find_compatible_node(NULL, NULL, "allwinner,sunxi-btlpm");
|
||||
struct device_node *np =
|
||||
of_find_compatible_node(NULL, NULL, "allwinner,sunxi-btlpm");
|
||||
struct device *dev = &pdev->dev;
|
||||
enum of_gpio_flags config;
|
||||
int ret, uart_index;
|
||||
u32 val;
|
||||
|
||||
bsi = devm_kzalloc(&pdev->dev, sizeof(struct bluesleep_info),
|
||||
GFP_KERNEL);
|
||||
GFP_KERNEL);
|
||||
if (!bsi)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -792,23 +790,24 @@ static int bluesleep_probe(struct platform_device *pdev)
|
||||
|
||||
/* set host_wake_assert */
|
||||
bsi->host_wake_assert = (config == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
|
||||
BT_DBG("bt_hostwake gpio=%d assert=%d\n", bsi->host_wake, bsi->host_wake_assert);
|
||||
BT_DBG("bt_hostwake gpio=%d assert=%d\n", bsi->host_wake,
|
||||
bsi->host_wake_assert);
|
||||
|
||||
if (assert_level != -1) {
|
||||
bsi->host_wake_assert = (assert_level & 0x02) > 0;
|
||||
BT_DBG("override host_wake assert to %d", bsi->host_wake_assert);
|
||||
BT_DBG("override host_wake assert to %d",
|
||||
bsi->host_wake_assert);
|
||||
}
|
||||
|
||||
ret = devm_gpio_request(dev, bsi->host_wake, "bt_hostwake");
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request bt_hostwake gpio %d\n",
|
||||
bsi->host_wake);
|
||||
BT_ERR("can't request bt_hostwake gpio %d\n", bsi->host_wake);
|
||||
goto err0;
|
||||
}
|
||||
ret = gpio_direction_input(bsi->host_wake);
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request input direction bt_wake gpio %d\n",
|
||||
bsi->host_wake);
|
||||
bsi->host_wake);
|
||||
goto err1;
|
||||
}
|
||||
|
||||
@@ -816,7 +815,7 @@ static int bluesleep_probe(struct platform_device *pdev)
|
||||
if (!of_property_read_bool(np, "wakeup-source")) {
|
||||
#else
|
||||
if (!of_property_read_u32(np, "wakeup-source", &bsi->wakeup_enable) &&
|
||||
(bsi->wakeup_enable == 0)) {
|
||||
(bsi->wakeup_enable == 0)) {
|
||||
#endif
|
||||
BT_DBG("wakeup source is disabled!\n");
|
||||
} else {
|
||||
@@ -829,12 +828,12 @@ static int bluesleep_probe(struct platform_device *pdev)
|
||||
ret = dev_pm_set_wake_irq(dev, gpio_to_irq(bsi->host_wake));
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't enable wakeup src for bt_hostwake %d\n",
|
||||
bsi->host_wake);
|
||||
bsi->host_wake);
|
||||
goto err2;
|
||||
}
|
||||
bsi->wakeup_enable = 1;
|
||||
#else
|
||||
BT_ERR("%s kernel unsupport this feature!\r\n", __func__);
|
||||
BT_ERR("%s kernel unsupport this feature!\r\n", __func__);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -847,14 +846,14 @@ static int bluesleep_probe(struct platform_device *pdev)
|
||||
|
||||
ret = devm_gpio_request(dev, bsi->ext_wake, "bt_wake");
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request bt_wake gpio %d\n",
|
||||
bsi->ext_wake);
|
||||
BT_ERR("can't request bt_wake gpio %d\n", bsi->ext_wake);
|
||||
goto err2;
|
||||
}
|
||||
|
||||
/* set ext_wake_assert */
|
||||
bsi->ext_wake_assert = (config == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
|
||||
BT_DBG("bt_wake gpio=%d assert=%d\n", bsi->ext_wake, bsi->ext_wake_assert);
|
||||
BT_DBG("bt_wake gpio=%d assert=%d\n", bsi->ext_wake,
|
||||
bsi->ext_wake_assert);
|
||||
|
||||
if (assert_level != -1) {
|
||||
bsi->ext_wake_assert = (assert_level & 0x01) > 0;
|
||||
@@ -865,7 +864,7 @@ static int bluesleep_probe(struct platform_device *pdev)
|
||||
ret = gpio_direction_output(bsi->ext_wake, bsi->ext_wake_assert);
|
||||
if (ret < 0) {
|
||||
BT_ERR("can't request output direction bt_wake gpio %d\n",
|
||||
bsi->ext_wake);
|
||||
bsi->ext_wake);
|
||||
goto err3;
|
||||
}
|
||||
/*set ext_wake deassert as default*/
|
||||
@@ -875,7 +874,7 @@ static int bluesleep_probe(struct platform_device *pdev)
|
||||
bsi->host_wake_irq = gpio_to_irq(bsi->host_wake);
|
||||
if (bsi->host_wake_irq < 0) {
|
||||
BT_ERR("map gpio [%d] to virq failed, errno = %d\n",
|
||||
bsi->host_wake, bsi->host_wake_irq);
|
||||
bsi->host_wake, bsi->host_wake_irq);
|
||||
ret = -ENODEV;
|
||||
goto err3;
|
||||
}
|
||||
@@ -898,7 +897,7 @@ static int bluesleep_probe(struct platform_device *pdev)
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)
|
||||
bsi->ws = wakeup_source_register(dev, "bluesleep");
|
||||
bsi->ws = wakeup_source_register(dev, "bluesleep");
|
||||
#else
|
||||
bsi->ws = wakeup_source_register("bluesleep");
|
||||
#endif
|
||||
@@ -1108,4 +1107,3 @@ int bluesleep_exit(struct platform_device *dev)
|
||||
bluesleep_remove(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -18,4 +18,3 @@ int bluesleep_init(struct platform_device *pdev);
|
||||
int bluesleep_exit(struct platform_device *dev);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -44,12 +44,11 @@ static struct rfkill_ops rfkill_bluetooth_ops = {
|
||||
|
||||
int rfkill_bluetooth_init(struct platform_device *pdev)
|
||||
{
|
||||
|
||||
int rc = 0;
|
||||
|
||||
pr_info("-->%s\n", __func__);
|
||||
bt_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
|
||||
&rfkill_bluetooth_ops, NULL);
|
||||
&rfkill_bluetooth_ops, NULL);
|
||||
if (!bt_rfk) {
|
||||
rc = -ENOMEM;
|
||||
goto err_rfkill_alloc;
|
||||
@@ -78,4 +77,3 @@ int rfkill_bluetooth_remove(struct platform_device *dev)
|
||||
pr_info("<--%s\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)
|
||||
EXTRA_CFLAGS += -Wno-implicit-fallthrough
|
||||
#EXTRA_CFLAGS += -Wno-unused-function
|
||||
EXTRA_CFLAGS += -Wno-unused-function
|
||||
#EXTRA_CFLAGS += -Wno-maybe-uninitialized
|
||||
#EXTRA_CFLAGS += -Wno-unused-variable
|
||||
EXTRA_CFLAGS += -Wno-unused-variable
|
||||
|
||||
RWNX_VERS_NUM := 6.4.3.0
|
||||
|
||||
@@ -75,22 +75,20 @@ CONFIG_RFTEST=y
|
||||
CONFIG_USB_BT =y
|
||||
CONFIG_SDIO_BT=n
|
||||
CONFIG_USE_5G ?= y
|
||||
CONFIG_SDIO_PWRCTRL ?= y
|
||||
CONFIG_CREATE_TRACE_POINTS = n
|
||||
CONFIG_TXRX_THREAD_PRIO = y
|
||||
# CONFIG_COEX = n for BT_ONLY, CONFIG_COEX =y for combo and sw
|
||||
CONFIG_COEX = y
|
||||
CONFIG_RX_NETIF_RECV_SKB = y
|
||||
CONFIG_GPIO_WAKEUP ?= n
|
||||
CONFIG_SET_VENDOR_EXTENSION_IE = n
|
||||
CONFIG_SUPPORT_REALTIME_CHANGE_MAC = y
|
||||
CONFIG_WPA3_FOR_OLD_KERNEL ?= n
|
||||
CONFIG_VHT_FOR_OLD_KERNEL ?= n
|
||||
CONFIG_HE_FOR_OLD_KERNEL ?= n
|
||||
CONFIG_PREALLOC_RX_SKB = n
|
||||
CONFIG_PREALLOC_RX_SKB ?= n
|
||||
CONFIG_WIFI_SUSPEND_FOR_LINUX = n
|
||||
# Need to set fw path in BOARD_KERNEL_CMDLINE
|
||||
CONFIG_USE_FW_REQUEST = n
|
||||
CONFIG_USE_FW_REQUEST ?= n
|
||||
CONFIG_USE_P2P0=n
|
||||
CONFIG_TX_NETIF_FLOWCTRL = n
|
||||
CONFIG_ONE_TXQ = n
|
||||
@@ -108,9 +106,23 @@ CONFIG_FILTER_TCP_ACK =y
|
||||
CONFIG_RESV_MEM_SUPPORT ?= y
|
||||
CONFIG_GKI = n
|
||||
CONFIG_TEMP_COMP = n
|
||||
CONFIG_TEMP_CONTROL = n
|
||||
CONFIG_EXT_FEM_8800DCDW = n
|
||||
CONFIG_SHUTDOWN_CALLBACK = y
|
||||
CONFIG_FOR_IPCAM = n
|
||||
CONFIG_SDIO_ADMA = n
|
||||
# CONFIG_MCC = n for sta and p2p concurrent in same channel.
|
||||
CONFIG_MCC = y
|
||||
CONFIG_APF = n
|
||||
CONFIG_POWER_LIMIT = n
|
||||
|
||||
#CONFIG FOR LOW POWER MODE
|
||||
CONFIG_SDIO_PWRCTRL ?= y
|
||||
CONFIG_GPIO_WAKEUP ?= n
|
||||
CONFIG_AUTO_POWERSAVE = n
|
||||
|
||||
# Enable wifi-hal Latency Mode
|
||||
CONFIG_AICWF_LATENCY_MODE = n
|
||||
|
||||
ifneq ($(CONFIG_WIRELESS_EXT), y)
|
||||
CONFIG_USE_WIRELESS_EXT = n
|
||||
@@ -136,7 +148,10 @@ CONFIG_RWNX_RADAR ?= y
|
||||
CONFIG_RWNX_BCMC ?= y
|
||||
|
||||
# Enable Monitor+Data interface support (need FW support)
|
||||
CONFIG_RWNX_MON_DATA =y
|
||||
CONFIG_RWNX_MON_DATA = n
|
||||
CONFIG_RWNX_MON_XMIT = n
|
||||
CONFIG_RWNX_MON_RXFILTER = n
|
||||
|
||||
|
||||
# extra DEBUG config
|
||||
CONFIG_RWNX_SW_PROFILING ?= n
|
||||
@@ -185,6 +200,7 @@ $(MODULE_NAME)-$(CONFIG_SDIO_SUPPORT) += aicwf_txrxif.o
|
||||
$(MODULE_NAME)-$(CONFIG_SDIO_SUPPORT) += aicwf_sdio.o
|
||||
$(MODULE_NAME)-$(CONFIG_FILTER_TCP_ACK) += aicwf_tcp_ack.o
|
||||
$(MODULE_NAME)-$(CONFIG_SDIO_BT) += aic_btsdio.o
|
||||
$(MODULE_NAME)-$(CONFIG_SDIO_BT) += btsdio.o
|
||||
|
||||
$(MODULE_NAME)-$(CONFIG_USB_SUPPORT) += usb_host.o
|
||||
$(MODULE_NAME)-$(CONFIG_USB_SUPPORT) += aicwf_txrxif.o
|
||||
@@ -235,6 +251,9 @@ ccflags-y += -I$(srctree)/$(src)/../aic8800_bsp
|
||||
ccflags-y += -DCONFIG_AIC_FW_PATH=\"$(CONFIG_AIC_FW_PATH)\"
|
||||
ccflags-$(CONFIG_RWNX_RADAR) += -DCONFIG_RWNX_RADAR
|
||||
ccflags-$(CONFIG_RWNX_MON_DATA) += -DCONFIG_RWNX_MON_DATA
|
||||
ccflags-$(CONFIG_RWNX_MON_XMIT) += -DCONFIG_RWNX_MON_XMIT
|
||||
ccflags-$(CONFIG_RWNX_MON_RXFILTER) += -DCONFIG_RWNX_MON_RXFILTER
|
||||
|
||||
ccflags-$(CONFIG_RWNX_BFMER) += -DCONFIG_RWNX_BFMER
|
||||
ccflags-$(CONFIG_RWNX_SPLIT_TX_BUF) += -DCONFIG_RWNX_SPLIT_TX_BUF
|
||||
ifeq ($(CONFIG_RWNX_SPLIT_TX_BUF), y)
|
||||
@@ -260,6 +279,7 @@ ccflags-$(CONFIG_USE_P2P0) += -DCONFIG_USE_P2P0
|
||||
ccflags-$(CONFIG_FDRV_NO_REG_SDIO) += -DCONFIG_FDRV_NO_REG_SDIO
|
||||
ccflags-$(CONFIG_SCHED_SCAN) += -DCONFIG_SCHED_SCAN
|
||||
ccflags-$(CONFIG_OOB) += -DCONFIG_OOB
|
||||
ccflags-$(CONFIG_AICWF_LATENCY_MODE) += -DAICWF_LATENCY_MODE
|
||||
ccflags-$(CONFIG_USE_CUSTOMER_MAC) += -DCONFIG_USE_CUSTOMER_MAC
|
||||
ccflags-$(CONFIG_PREALLOC_TXQ) += -DCONFIG_PREALLOC_TXQ
|
||||
ccflags-$(CONFIG_DPD) += -DCONFIG_DPD
|
||||
@@ -270,8 +290,13 @@ ccflags-$(CONFIG_SDIO_BT) += -DCONFIG_SDIO_BT
|
||||
ccflags-$(CONFIG_RESV_MEM_SUPPORT) += -DCONFIG_RESV_MEM_SUPPORT
|
||||
ccflags-$(CONFIG_GKI) += -DCONFIG_GKI
|
||||
ccflags-$(CONFIG_TEMP_COMP) += -DCONFIG_TEMP_COMP
|
||||
ccflags-$(CONFIG_TEMP_CONTROL) += -DCONFIG_TEMP_CONTROL
|
||||
ccflags-$(CONFIG_POWER_LIMIT) += -DCONFIG_POWER_LIMIT
|
||||
ccflags-$(CONFIG_EXT_FEM_8800DCDW) += -DCONFIG_EXT_FEM_8800DCDW
|
||||
ccflags-$(CONFIG_MCC) += -DCONFIG_MCC
|
||||
ccflags-$(CONFIG_SHUTDOWN_CALLBACK) += -DCONFIG_SHUTDOWN_CALLBACK
|
||||
ccflags-$(CONFIG_FOR_IPCAM) += -DCONFIG_FOR_IPCAM
|
||||
ccflags-$(CONFIG_SDIO_ADMA) += -DCONFIG_SDIO_ADMA
|
||||
|
||||
|
||||
ifeq ($(CONFIG_SDIO_SUPPORT), y)
|
||||
@@ -307,11 +332,13 @@ endif
|
||||
|
||||
ccflags-$(CONFIG_RX_REORDER) += -DAICWF_RX_REORDER
|
||||
ccflags-$(CONFIG_ARP_OFFLOAD) += -DAICWF_ARP_OFFLOAD
|
||||
ccflags-$(CONFIG_RADAR_DETECT) += -DRADAR_OR_IR_DETECT
|
||||
ccflags-$(CONFIG_RADAR_OR_IR_DETECT) += -DCONFIG_RADAR_OR_IR_DETECT
|
||||
ccflags-$(CONFIG_DOWNLOAD_FW) += -DCONFIG_DOWNLOAD_FW
|
||||
ccflags-$(CONFIG_RX_NETIF_RECV_SKB) += -DCONFIG_RX_NETIF_RECV_SKB
|
||||
ccflags-$(CONFIG_ONE_TXQ) += -DCONFIG_ONE_TXQ
|
||||
ccflags-$(CONFIG_TX_NETIF_FLOWCTRL) += -DCONFIG_TX_NETIF_FLOWCTRL
|
||||
ccflags-$(CONFIG_APF) += -DCONFIG_APF
|
||||
ccflags-$(CONFIG_AUTO_POWERSAVE) += -DCONFIG_AUTO_POWERSAVE
|
||||
|
||||
ccflags-y += -DAIC_TRACE_INCLUDE_PATH=$(src)
|
||||
MAKEFLAGS +=-j$(shell nproc)
|
||||
@@ -362,6 +389,7 @@ ccflags-y += -DANDROID_PLATFORM
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_PLATFORM_UBUNTU), y)
|
||||
ccflags-$(CONFIG_PLATFORM_UBUNTU) += -DCONFIG_PLATFORM_UBUNTU
|
||||
KDIR ?= /lib/modules/$(shell uname -r)/build
|
||||
PWD ?= $(shell pwd)
|
||||
KVER ?= $(shell uname -r)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -15,13 +15,13 @@
|
||||
#ifndef _AIC_BR_EXT_H_
|
||||
#define _AIC_BR_EXT_H_
|
||||
|
||||
#define CL_IPV6_PASS 1
|
||||
#define MACADDRLEN 6
|
||||
#define WLAN_ETHHDR_LEN 14
|
||||
#define CL_IPV6_PASS 1
|
||||
#define MACADDRLEN 6
|
||||
#define WLAN_ETHHDR_LEN 14
|
||||
|
||||
#define NAT25_HASH_BITS 4
|
||||
#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS)
|
||||
#define NAT25_AGEING_TIME 300
|
||||
#define NAT25_HASH_BITS 4
|
||||
#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS)
|
||||
#define NAT25_AGEING_TIME 300
|
||||
|
||||
#define NDEV_FMT "%s"
|
||||
#define NDEV_ARG(ndev) ndev->name
|
||||
@@ -32,22 +32,23 @@
|
||||
#define FUNC_ADPT_FMT "%s(%s)"
|
||||
//#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL)
|
||||
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
|
||||
#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
|
||||
|
||||
#define MAC_ARG(x) \
|
||||
((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], \
|
||||
((u8 *)(x))[4], ((u8 *)(x))[5]
|
||||
|
||||
#ifdef CL_IPV6_PASS
|
||||
#define MAX_NETWORK_ADDR_LEN 17
|
||||
#define MAX_NETWORK_ADDR_LEN 17
|
||||
#else
|
||||
#define MAX_NETWORK_ADDR_LEN 11
|
||||
#define MAX_NETWORK_ADDR_LEN 11
|
||||
#endif
|
||||
|
||||
struct nat25_network_db_entry {
|
||||
struct nat25_network_db_entry *next_hash;
|
||||
struct nat25_network_db_entry **pprev_hash;
|
||||
atomic_t use_count;
|
||||
unsigned char macAddr[6];
|
||||
unsigned long ageing_timer;
|
||||
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
|
||||
struct nat25_network_db_entry *next_hash;
|
||||
struct nat25_network_db_entry **pprev_hash;
|
||||
atomic_t use_count;
|
||||
unsigned char macAddr[6];
|
||||
unsigned long ageing_timer;
|
||||
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
|
||||
};
|
||||
|
||||
enum NAT25_METHOD {
|
||||
@@ -60,12 +61,12 @@ enum NAT25_METHOD {
|
||||
};
|
||||
|
||||
struct br_ext_info {
|
||||
unsigned int nat25_disable;
|
||||
unsigned int macclone_enable;
|
||||
unsigned int dhcp_bcst_disable;
|
||||
int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */
|
||||
unsigned char nat25_dmzMac[MACADDRLEN];
|
||||
unsigned int nat25sc_disable;
|
||||
unsigned int nat25_disable;
|
||||
unsigned int macclone_enable;
|
||||
unsigned int dhcp_bcst_disable;
|
||||
int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */
|
||||
unsigned char nat25_dmzMac[MACADDRLEN];
|
||||
unsigned int nat25sc_disable;
|
||||
};
|
||||
|
||||
void nat25_db_cleanup(struct rwnx_vif *vif);
|
||||
|
||||
@@ -12,9 +12,9 @@ enum aicbsp_pwr_state {
|
||||
};
|
||||
|
||||
struct aicbsp_feature_t {
|
||||
int hwinfo;
|
||||
int hwinfo;
|
||||
uint32_t sdio_clock;
|
||||
uint8_t sdio_phase;
|
||||
uint8_t sdio_phase;
|
||||
int fwlog_en;
|
||||
uint8_t irqf;
|
||||
};
|
||||
@@ -23,32 +23,38 @@ enum skb_buff_id {
|
||||
AIC_RESV_MEM_TXDATA,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DPD
|
||||
#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
|
||||
typedef struct {
|
||||
uint32_t bit_mask[3];
|
||||
uint32_t reserved;
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t dpd_11b[96];
|
||||
uint32_t dpd_low[96];
|
||||
uint32_t idac_11b[48];
|
||||
uint32_t idac_high[48];
|
||||
uint32_t idac_low[48];
|
||||
uint32_t loft_res[18];
|
||||
uint32_t rx_iqim_res[16];
|
||||
uint32_t bit_mask[3];
|
||||
uint32_t reserved;
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t dpd_11b[96];
|
||||
uint32_t dpd_low[96];
|
||||
uint32_t idac_11b[48];
|
||||
uint32_t idac_high[48];
|
||||
uint32_t idac_low[48];
|
||||
uint32_t loft_res[18];
|
||||
uint32_t rx_iqim_res[16];
|
||||
} rf_misc_ram_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t bit_mask[4];
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t loft_res[18];
|
||||
uint32_t bit_mask[4];
|
||||
uint32_t dpd_high[96];
|
||||
uint32_t loft_res[18];
|
||||
} rf_misc_ram_lite_t;
|
||||
|
||||
#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
|
||||
#define DPD_RESULT_SIZE_8800DC sizeof(rf_misc_ram_lite_t)
|
||||
#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
|
||||
#define DPD_RESULT_SIZE_8800DC sizeof(rf_misc_ram_lite_t)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DPD
|
||||
extern rf_misc_ram_lite_t dpd_res;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LOFT_CALIB
|
||||
extern rf_misc_ram_lite_t loft_res_local;
|
||||
#endif
|
||||
|
||||
int aicbsp_set_subsys(int, int);
|
||||
int aicbsp_get_feature(struct aicbsp_feature_t *feature, char *fw_path);
|
||||
bool aicbsp_get_load_fw_in_fdrv(void);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -17,84 +17,83 @@
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
|
||||
#ifdef CONFIG_PLATFORM_UBUNTU
|
||||
#define CONFIG_BLUEDROID 1 /* bleuz 0, bluedroid 1 */
|
||||
#define CONFIG_BLUEDROID 0 /* bleuz 0, bluedroid 1 */
|
||||
#else
|
||||
#define CONFIG_BLUEDROID 1 /* bleuz 0, bluedroid 1 */
|
||||
#define CONFIG_BLUEDROID 1 /* bleuz 0, bluedroid 1 */
|
||||
#endif
|
||||
/* #define HCI_VERSION_CODE KERNEL_VERSION(3, 14, 41) */
|
||||
#define HCI_VERSION_CODE LINUX_VERSION_CODE
|
||||
|
||||
#define PRINT_CMD_EVENT 1
|
||||
#define PRINT_ACL_DATA 1
|
||||
#define PRINT_SCO_DATA 1
|
||||
|
||||
#define PRINT_CMD_EVENT 1
|
||||
#define PRINT_ACL_DATA 1
|
||||
#define PRINT_SCO_DATA 1
|
||||
|
||||
#define AICBT_DBG_FLAG 1
|
||||
#define AICBT_DBG_FLAG 1
|
||||
|
||||
#if AICBT_DBG_FLAG
|
||||
#define AICBT_DBG(fmt, arg...) printk( "aic_btsdio: " fmt "\n" , ## arg)
|
||||
#define AICBT_DBG(fmt, arg...) printk("aic_btsdio: " fmt "\n", ##arg)
|
||||
#else
|
||||
#define AICBT_DBG(fmt, arg...)
|
||||
#endif
|
||||
|
||||
#define AICBT_INFO(fmt, arg...) printk("aic_btsdio: " fmt "\n" , ## arg)
|
||||
#define AICBT_WARN(fmt, arg...) printk("aic_btsdio: " fmt "\n" , ## arg)
|
||||
#define AICBT_ERR(fmt, arg...) printk("aic_btsdio: " fmt "\n" , ## arg)
|
||||
#define AICBT_INFO(fmt, arg...) printk("aic_btsdio: " fmt "\n", ##arg)
|
||||
#define AICBT_WARN(fmt, arg...) printk("aic_btsdio: " fmt "\n", ##arg)
|
||||
#define AICBT_ERR(fmt, arg...) printk("aic_btsdio: " fmt "\n", ##arg)
|
||||
|
||||
#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 4, 0)
|
||||
#define GET_DRV_DATA(x) hci_get_drvdata(x)
|
||||
#define GET_DRV_DATA(x) hci_get_drvdata(x)
|
||||
#else
|
||||
#define GET_DRV_DATA(x) x->driver_data
|
||||
#define GET_DRV_DATA(x) x->driver_data
|
||||
#endif
|
||||
|
||||
#if CONFIG_BLUEDROID
|
||||
struct btusb_data {
|
||||
struct hci_dev *hdev;
|
||||
//struct usb_device *udev;
|
||||
//struct usb_interface *intf;
|
||||
//struct usb_interface *isoc;
|
||||
struct hci_dev *hdev;
|
||||
//struct usb_device *udev;
|
||||
//struct usb_interface *intf;
|
||||
//struct usb_interface *isoc;
|
||||
|
||||
spinlock_t lock;
|
||||
spinlock_t lock;
|
||||
|
||||
unsigned long flags;
|
||||
unsigned long flags;
|
||||
|
||||
struct work_struct work;
|
||||
struct work_struct waker;
|
||||
struct work_struct work;
|
||||
struct work_struct waker;
|
||||
|
||||
/*struct usb_anchor tx_anchor;
|
||||
/*struct usb_anchor tx_anchor;
|
||||
struct usb_anchor intr_anchor;
|
||||
struct usb_anchor bulk_anchor;
|
||||
struct usb_anchor isoc_anchor;
|
||||
struct usb_anchor deferred;*/
|
||||
int tx_in_flight;
|
||||
spinlock_t txlock;
|
||||
|
||||
int tx_in_flight;
|
||||
spinlock_t txlock;
|
||||
|
||||
#if (CONFIG_BLUEDROID == 0)
|
||||
#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)
|
||||
spinlock_t rxlock;
|
||||
struct sk_buff *evt_skb;
|
||||
struct sk_buff *acl_skb;
|
||||
struct sk_buff *sco_skb;
|
||||
spinlock_t rxlock;
|
||||
struct sk_buff *evt_skb;
|
||||
struct sk_buff *acl_skb;
|
||||
struct sk_buff *sco_skb;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*struct usb_endpoint_descriptor *intr_ep;
|
||||
/*struct usb_endpoint_descriptor *intr_ep;
|
||||
struct usb_endpoint_descriptor *bulk_tx_ep;
|
||||
struct usb_endpoint_descriptor *bulk_rx_ep;
|
||||
struct usb_endpoint_descriptor *isoc_tx_ep;
|
||||
struct usb_endpoint_descriptor *isoc_rx_ep;*/
|
||||
|
||||
__u8 cmdreq_type;
|
||||
__u8 cmdreq_type;
|
||||
|
||||
unsigned int sco_num;
|
||||
int isoc_altsetting;
|
||||
int suspend_count;
|
||||
uint16_t sco_handle;
|
||||
unsigned int sco_num;
|
||||
int isoc_altsetting;
|
||||
int suspend_count;
|
||||
uint16_t sco_handle;
|
||||
|
||||
#if (CONFIG_BLUEDROID == 0)
|
||||
#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)
|
||||
int (*recv_bulk) (struct btusb_data * data, void *buffer, int count);
|
||||
int (*recv_bulk)(struct btusb_data *data, void *buffer, int count);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -102,81 +101,78 @@ struct btusb_data {
|
||||
#if 0
|
||||
struct early_suspend early_suspend;
|
||||
#else
|
||||
struct notifier_block pm_notifier;
|
||||
struct notifier_block reboot_notifier;
|
||||
struct notifier_block pm_notifier;
|
||||
struct notifier_block reboot_notifier;
|
||||
#endif
|
||||
//firmware_info *fw_info;
|
||||
//firmware_info *fw_info;
|
||||
|
||||
#ifdef CONFIG_SCO_OVER_HCI
|
||||
AIC_sco_card_t *pSCOSnd;
|
||||
AIC_sco_card_t *pSCOSnd;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
#define QUEUE_SIZE 500
|
||||
|
||||
/***************************************
|
||||
** AicSemi - Integrate from bluetooth.h **
|
||||
*****************************************/
|
||||
/* Reserv for core and drivers use */
|
||||
#define BT_SKB_RESERVE 8
|
||||
#define BT_SKB_RESERVE 8
|
||||
|
||||
/* BD Address */
|
||||
typedef struct {
|
||||
__u8 b[6];
|
||||
__u8 b[6];
|
||||
} __packed bdaddr_t;
|
||||
|
||||
/* Skb helpers */
|
||||
struct bt_skb_cb {
|
||||
__u8 pkt_type;
|
||||
__u8 incoming;
|
||||
__u16 expect;
|
||||
__u16 tx_seq;
|
||||
__u8 retries;
|
||||
__u8 sar;
|
||||
__u8 force_active;
|
||||
__u8 pkt_type;
|
||||
__u8 incoming;
|
||||
__u16 expect;
|
||||
__u16 tx_seq;
|
||||
__u8 retries;
|
||||
__u8 sar;
|
||||
__u8 force_active;
|
||||
};
|
||||
|
||||
#define bt_cb(skb) ((struct bt_skb_cb *)((skb)->cb))
|
||||
|
||||
|
||||
/***********************************
|
||||
** AicSemi - Integrate from hci.h **
|
||||
***********************************/
|
||||
#define HCI_MAX_ACL_SIZE 1024
|
||||
#define HCI_MAX_SCO_SIZE 255
|
||||
#define HCI_MAX_EVENT_SIZE 260
|
||||
#define HCI_MAX_FRAME_SIZE (HCI_MAX_ACL_SIZE + 4)
|
||||
#define HCI_MAX_ACL_SIZE 1024
|
||||
#define HCI_MAX_SCO_SIZE 255
|
||||
#define HCI_MAX_EVENT_SIZE 260
|
||||
#define HCI_MAX_FRAME_SIZE (HCI_MAX_ACL_SIZE + 4)
|
||||
|
||||
/* HCI bus types */
|
||||
#define HCI_VIRTUAL 0
|
||||
#define HCI_USB 1
|
||||
#define HCI_PCCARD 2
|
||||
#define HCI_UART 3
|
||||
#define HCI_RS232 4
|
||||
#define HCI_PCI 5
|
||||
#define HCI_SDIO 6
|
||||
#define HCI_VIRTUAL 0
|
||||
#define HCI_USB 1
|
||||
#define HCI_PCCARD 2
|
||||
#define HCI_UART 3
|
||||
#define HCI_RS232 4
|
||||
#define HCI_PCI 5
|
||||
#define HCI_SDIO 6
|
||||
|
||||
/* HCI controller types */
|
||||
#define HCI_BREDR 0x00
|
||||
#define HCI_AMP 0x01
|
||||
#define HCI_BREDR 0x00
|
||||
#define HCI_AMP 0x01
|
||||
|
||||
/* HCI device flags */
|
||||
enum {
|
||||
HCI_UP,
|
||||
HCI_INIT,
|
||||
HCI_RUNNING,
|
||||
HCI_UP,
|
||||
HCI_INIT,
|
||||
HCI_RUNNING,
|
||||
|
||||
HCI_PSCAN,
|
||||
HCI_ISCAN,
|
||||
HCI_AUTH,
|
||||
HCI_ENCRYPT,
|
||||
HCI_INQUIRY,
|
||||
HCI_PSCAN,
|
||||
HCI_ISCAN,
|
||||
HCI_AUTH,
|
||||
HCI_ENCRYPT,
|
||||
HCI_INQUIRY,
|
||||
|
||||
HCI_RAW,
|
||||
HCI_RAW,
|
||||
|
||||
HCI_RESET,
|
||||
HCI_RESET,
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -184,104 +180,104 @@ enum {
|
||||
* states from the controller.
|
||||
*/
|
||||
enum {
|
||||
HCI_SETUP,
|
||||
HCI_AUTO_OFF,
|
||||
HCI_MGMT,
|
||||
HCI_PAIRABLE,
|
||||
HCI_SERVICE_CACHE,
|
||||
HCI_LINK_KEYS,
|
||||
HCI_DEBUG_KEYS,
|
||||
HCI_UNREGISTER,
|
||||
HCI_SETUP,
|
||||
HCI_AUTO_OFF,
|
||||
HCI_MGMT,
|
||||
HCI_PAIRABLE,
|
||||
HCI_SERVICE_CACHE,
|
||||
HCI_LINK_KEYS,
|
||||
HCI_DEBUG_KEYS,
|
||||
HCI_UNREGISTER,
|
||||
|
||||
HCI_LE_SCAN,
|
||||
HCI_SSP_ENABLED,
|
||||
HCI_HS_ENABLED,
|
||||
HCI_LE_ENABLED,
|
||||
HCI_CONNECTABLE,
|
||||
HCI_DISCOVERABLE,
|
||||
HCI_LINK_SECURITY,
|
||||
HCI_PENDING_CLASS,
|
||||
HCI_LE_SCAN,
|
||||
HCI_SSP_ENABLED,
|
||||
HCI_HS_ENABLED,
|
||||
HCI_LE_ENABLED,
|
||||
HCI_CONNECTABLE,
|
||||
HCI_DISCOVERABLE,
|
||||
HCI_LINK_SECURITY,
|
||||
HCI_PENDING_CLASS,
|
||||
};
|
||||
|
||||
/* HCI data types */
|
||||
#define HCI_COMMAND_PKT 0x01
|
||||
#define HCI_ACLDATA_PKT 0x02
|
||||
#define HCI_SCODATA_PKT 0x03
|
||||
#define HCI_EVENT_PKT 0x04
|
||||
#define HCI_VENDOR_PKT 0xff
|
||||
#define HCI_COMMAND_PKT 0x01
|
||||
#define HCI_ACLDATA_PKT 0x02
|
||||
#define HCI_SCODATA_PKT 0x03
|
||||
#define HCI_EVENT_PKT 0x04
|
||||
#define HCI_VENDOR_PKT 0xff
|
||||
|
||||
#define HCI_MAX_NAME_LENGTH 248
|
||||
#define HCI_MAX_EIR_LENGTH 240
|
||||
#define HCI_MAX_NAME_LENGTH 248
|
||||
#define HCI_MAX_EIR_LENGTH 240
|
||||
|
||||
#define HCI_OP_READ_LOCAL_VERSION 0x1001
|
||||
#define HCI_OP_READ_LOCAL_VERSION 0x1001
|
||||
struct hci_rp_read_local_version {
|
||||
__u8 status;
|
||||
__u8 hci_ver;
|
||||
__le16 hci_rev;
|
||||
__u8 lmp_ver;
|
||||
__le16 manufacturer;
|
||||
__le16 lmp_subver;
|
||||
__u8 status;
|
||||
__u8 hci_ver;
|
||||
__le16 hci_rev;
|
||||
__u8 lmp_ver;
|
||||
__le16 manufacturer;
|
||||
__le16 lmp_subver;
|
||||
} __packed;
|
||||
|
||||
#define HCI_EV_CMD_COMPLETE 0x0e
|
||||
#define HCI_EV_CMD_COMPLETE 0x0e
|
||||
struct hci_ev_cmd_complete {
|
||||
__u8 ncmd;
|
||||
__le16 opcode;
|
||||
__u8 ncmd;
|
||||
__le16 opcode;
|
||||
} __packed;
|
||||
|
||||
/* ---- HCI Packet structures ---- */
|
||||
#define HCI_COMMAND_HDR_SIZE 3
|
||||
#define HCI_EVENT_HDR_SIZE 2
|
||||
#define HCI_ACL_HDR_SIZE 4
|
||||
#define HCI_SCO_HDR_SIZE 3
|
||||
#define HCI_EVENT_HDR_SIZE 2
|
||||
#define HCI_ACL_HDR_SIZE 4
|
||||
#define HCI_SCO_HDR_SIZE 3
|
||||
|
||||
struct hci_command_hdr {
|
||||
__le16 opcode; /* OCF & OGF */
|
||||
__u8 plen;
|
||||
__le16 opcode; /* OCF & OGF */
|
||||
__u8 plen;
|
||||
} __packed;
|
||||
|
||||
struct hci_event_hdr {
|
||||
__u8 evt;
|
||||
__u8 plen;
|
||||
__u8 evt;
|
||||
__u8 plen;
|
||||
} __packed;
|
||||
|
||||
struct hci_acl_hdr {
|
||||
__le16 handle; /* Handle & Flags(PB, BC) */
|
||||
__le16 dlen;
|
||||
__le16 handle; /* Handle & Flags(PB, BC) */
|
||||
__le16 dlen;
|
||||
} __packed;
|
||||
|
||||
struct hci_sco_hdr {
|
||||
__le16 handle;
|
||||
__u8 dlen;
|
||||
__le16 handle;
|
||||
__u8 dlen;
|
||||
} __packed;
|
||||
|
||||
static inline struct hci_event_hdr *hci_event_hdr(const struct sk_buff *skb)
|
||||
{
|
||||
return (struct hci_event_hdr *) skb->data;
|
||||
return (struct hci_event_hdr *)skb->data;
|
||||
}
|
||||
|
||||
static inline struct hci_acl_hdr *hci_acl_hdr(const struct sk_buff *skb)
|
||||
{
|
||||
return (struct hci_acl_hdr *) skb->data;
|
||||
return (struct hci_acl_hdr *)skb->data;
|
||||
}
|
||||
|
||||
static inline struct hci_sco_hdr *hci_sco_hdr(const struct sk_buff *skb)
|
||||
{
|
||||
return (struct hci_sco_hdr *) skb->data;
|
||||
return (struct hci_sco_hdr *)skb->data;
|
||||
}
|
||||
|
||||
/* ---- HCI Ioctl requests structures ---- */
|
||||
struct hci_dev_stats {
|
||||
__u32 err_rx;
|
||||
__u32 err_tx;
|
||||
__u32 cmd_tx;
|
||||
__u32 evt_rx;
|
||||
__u32 acl_tx;
|
||||
__u32 acl_rx;
|
||||
__u32 sco_tx;
|
||||
__u32 sco_rx;
|
||||
__u32 byte_rx;
|
||||
__u32 byte_tx;
|
||||
__u32 err_rx;
|
||||
__u32 err_tx;
|
||||
__u32 cmd_tx;
|
||||
__u32 evt_rx;
|
||||
__u32 acl_tx;
|
||||
__u32 acl_rx;
|
||||
__u32 sco_tx;
|
||||
__u32 sco_rx;
|
||||
__u32 byte_rx;
|
||||
__u32 byte_tx;
|
||||
};
|
||||
/* AicSemi - Integrate from hci.h end */
|
||||
|
||||
@@ -289,131 +285,130 @@ struct hci_dev_stats {
|
||||
** AicSemi - Integrate from hci_core.h **
|
||||
*****************************************/
|
||||
struct hci_conn_hash {
|
||||
struct list_head list;
|
||||
unsigned int acl_num;
|
||||
unsigned int sco_num;
|
||||
unsigned int le_num;
|
||||
struct list_head list;
|
||||
unsigned int acl_num;
|
||||
unsigned int sco_num;
|
||||
unsigned int le_num;
|
||||
};
|
||||
|
||||
#define HCI_MAX_SHORT_NAME_LENGTH 10
|
||||
#define HCI_MAX_SHORT_NAME_LENGTH 10
|
||||
|
||||
#define NUM_REASSEMBLY 4
|
||||
struct hci_dev {
|
||||
struct mutex lock;
|
||||
struct mutex lock;
|
||||
|
||||
char name[8];
|
||||
unsigned long flags;
|
||||
__u16 id;
|
||||
__u8 bus;
|
||||
__u8 dev_type;
|
||||
char name[8];
|
||||
unsigned long flags;
|
||||
__u16 id;
|
||||
__u8 bus;
|
||||
__u8 dev_type;
|
||||
|
||||
struct sk_buff *reassembly[NUM_REASSEMBLY];
|
||||
struct sk_buff *reassembly[NUM_REASSEMBLY];
|
||||
|
||||
struct hci_conn_hash conn_hash;
|
||||
struct hci_conn_hash conn_hash;
|
||||
|
||||
struct hci_dev_stats stat;
|
||||
struct hci_dev_stats stat;
|
||||
|
||||
#if LINUX_VERSION_CODE <= KERNEL_VERSION(3, 4, 0)
|
||||
atomic_t refcnt;
|
||||
struct module *owner;
|
||||
void *driver_data;
|
||||
atomic_t refcnt;
|
||||
struct module *owner;
|
||||
void *driver_data;
|
||||
#endif
|
||||
|
||||
atomic_t promisc;
|
||||
atomic_t promisc;
|
||||
|
||||
struct device *parent;
|
||||
struct device dev;
|
||||
struct device *parent;
|
||||
struct device dev;
|
||||
|
||||
unsigned long dev_flags;
|
||||
unsigned long dev_flags;
|
||||
|
||||
int (*open)(struct hci_dev *hdev);
|
||||
int (*close)(struct hci_dev *hdev);
|
||||
int (*flush)(struct hci_dev *hdev);
|
||||
int (*send)(struct sk_buff *skb);
|
||||
int (*open)(struct hci_dev *hdev);
|
||||
int (*close)(struct hci_dev *hdev);
|
||||
int (*flush)(struct hci_dev *hdev);
|
||||
int (*send)(struct sk_buff *skb);
|
||||
#if LINUX_VERSION_CODE <= KERNEL_VERSION(3, 4, 0)
|
||||
void (*destruct)(struct hci_dev *hdev);
|
||||
void (*destruct)(struct hci_dev *hdev);
|
||||
#endif
|
||||
#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 7, 1)
|
||||
__u16 voice_setting;
|
||||
__u16 voice_setting;
|
||||
#endif
|
||||
void (*notify)(struct hci_dev *hdev, unsigned int evt);
|
||||
int (*ioctl)(struct hci_dev *hdev, unsigned int cmd, unsigned long arg);
|
||||
void (*notify)(struct hci_dev *hdev, unsigned int evt);
|
||||
int (*ioctl)(struct hci_dev *hdev, unsigned int cmd, unsigned long arg);
|
||||
u8 *align_data;
|
||||
};
|
||||
|
||||
#if LINUX_VERSION_CODE <= KERNEL_VERSION(3, 4, 0)
|
||||
static inline struct hci_dev *__hci_dev_hold(struct hci_dev *d)
|
||||
{
|
||||
atomic_inc(&d->refcnt);
|
||||
return d;
|
||||
atomic_inc(&d->refcnt);
|
||||
return d;
|
||||
}
|
||||
|
||||
static inline void __hci_dev_put(struct hci_dev *d)
|
||||
{
|
||||
if (atomic_dec_and_test(&d->refcnt))
|
||||
d->destruct(d);
|
||||
if (atomic_dec_and_test(&d->refcnt))
|
||||
d->destruct(d);
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void *hci_get_drvdata(struct hci_dev *hdev)
|
||||
{
|
||||
return dev_get_drvdata(&hdev->dev);
|
||||
return dev_get_drvdata(&hdev->dev);
|
||||
}
|
||||
|
||||
static inline void hci_set_drvdata(struct hci_dev *hdev, void *data)
|
||||
{
|
||||
dev_set_drvdata(&hdev->dev, data);
|
||||
dev_set_drvdata(&hdev->dev, data);
|
||||
}
|
||||
|
||||
#define SET_HCIDEV_DEV(hdev, pdev) ((hdev)->parent = (pdev))
|
||||
|
||||
|
||||
/* ---- HCI Packet structures ---- */
|
||||
#define HCI_COMMAND_HDR_SIZE 3
|
||||
#define HCI_EVENT_HDR_SIZE 2
|
||||
#define HCI_ACL_HDR_SIZE 4
|
||||
#define HCI_SCO_HDR_SIZE 3
|
||||
#define HCI_EVENT_HDR_SIZE 2
|
||||
#define HCI_ACL_HDR_SIZE 4
|
||||
#define HCI_SCO_HDR_SIZE 3
|
||||
|
||||
/* ----- HCI Commands ---- */
|
||||
#define HCI_OP_INQUIRY 0x0401
|
||||
#define HCI_OP_INQUIRY_CANCEL 0x0402
|
||||
#define HCI_OP_EXIT_PERIODIC_INQ 0x0404
|
||||
#define HCI_OP_CREATE_CONN 0x0405
|
||||
#define HCI_OP_DISCONNECT 0x0406
|
||||
#define HCI_OP_ADD_SCO 0x0407
|
||||
#define HCI_OP_CREATE_CONN_CANCEL 0x0408
|
||||
#define HCI_OP_ACCEPT_CONN_REQ 0x0409
|
||||
#define HCI_OP_REJECT_CONN_REQ 0x040a
|
||||
#define HCI_OP_LINK_KEY_REPLY 0x040b
|
||||
#define HCI_OP_LINK_KEY_NEG_REPLY 0x040c
|
||||
#define HCI_OP_PIN_CODE_REPLY 0x040d
|
||||
#define HCI_OP_PIN_CODE_NEG_REPLY 0x040e
|
||||
#define HCI_OP_CHANGE_CONN_PTYPE 0x040f
|
||||
#define HCI_OP_AUTH_REQUESTED 0x0411
|
||||
#define HCI_OP_SET_CONN_ENCRYPT 0x0413
|
||||
#define HCI_OP_CHANGE_CONN_LINK_KEY 0x0415
|
||||
#define HCI_OP_REMOTE_NAME_REQ 0x0419
|
||||
#define HCI_OP_REMOTE_NAME_REQ_CANCEL 0x041a
|
||||
#define HCI_OP_READ_REMOTE_FEATURES 0x041b
|
||||
#define HCI_OP_READ_REMOTE_EXT_FEATURES 0x041c
|
||||
#define HCI_OP_READ_REMOTE_VERSION 0x041d
|
||||
#define HCI_OP_SETUP_SYNC_CONN 0x0428
|
||||
#define HCI_OP_ACCEPT_SYNC_CONN_REQ 0x0429
|
||||
#define HCI_OP_REJECT_SYNC_CONN_REQ 0x042a
|
||||
#define HCI_OP_SNIFF_MODE 0x0803
|
||||
#define HCI_OP_EXIT_SNIFF_MODE 0x0804
|
||||
#define HCI_OP_ROLE_DISCOVERY 0x0809
|
||||
#define HCI_OP_SWITCH_ROLE 0x080b
|
||||
#define HCI_OP_READ_LINK_POLICY 0x080c
|
||||
#define HCI_OP_WRITE_LINK_POLICY 0x080d
|
||||
#define HCI_OP_READ_DEF_LINK_POLICY 0x080e
|
||||
#define HCI_OP_WRITE_DEF_LINK_POLICY 0x080f
|
||||
#define HCI_OP_SNIFF_SUBRATE 0x0811
|
||||
#define HCI_OP_INQUIRY 0x0401
|
||||
#define HCI_OP_INQUIRY_CANCEL 0x0402
|
||||
#define HCI_OP_EXIT_PERIODIC_INQ 0x0404
|
||||
#define HCI_OP_CREATE_CONN 0x0405
|
||||
#define HCI_OP_DISCONNECT 0x0406
|
||||
#define HCI_OP_ADD_SCO 0x0407
|
||||
#define HCI_OP_CREATE_CONN_CANCEL 0x0408
|
||||
#define HCI_OP_ACCEPT_CONN_REQ 0x0409
|
||||
#define HCI_OP_REJECT_CONN_REQ 0x040a
|
||||
#define HCI_OP_LINK_KEY_REPLY 0x040b
|
||||
#define HCI_OP_LINK_KEY_NEG_REPLY 0x040c
|
||||
#define HCI_OP_PIN_CODE_REPLY 0x040d
|
||||
#define HCI_OP_PIN_CODE_NEG_REPLY 0x040e
|
||||
#define HCI_OP_CHANGE_CONN_PTYPE 0x040f
|
||||
#define HCI_OP_AUTH_REQUESTED 0x0411
|
||||
#define HCI_OP_SET_CONN_ENCRYPT 0x0413
|
||||
#define HCI_OP_CHANGE_CONN_LINK_KEY 0x0415
|
||||
#define HCI_OP_REMOTE_NAME_REQ 0x0419
|
||||
#define HCI_OP_REMOTE_NAME_REQ_CANCEL 0x041a
|
||||
#define HCI_OP_READ_REMOTE_FEATURES 0x041b
|
||||
#define HCI_OP_READ_REMOTE_EXT_FEATURES 0x041c
|
||||
#define HCI_OP_READ_REMOTE_VERSION 0x041d
|
||||
#define HCI_OP_SETUP_SYNC_CONN 0x0428
|
||||
#define HCI_OP_ACCEPT_SYNC_CONN_REQ 0x0429
|
||||
#define HCI_OP_REJECT_SYNC_CONN_REQ 0x042a
|
||||
#define HCI_OP_SNIFF_MODE 0x0803
|
||||
#define HCI_OP_EXIT_SNIFF_MODE 0x0804
|
||||
#define HCI_OP_ROLE_DISCOVERY 0x0809
|
||||
#define HCI_OP_SWITCH_ROLE 0x080b
|
||||
#define HCI_OP_READ_LINK_POLICY 0x080c
|
||||
#define HCI_OP_WRITE_LINK_POLICY 0x080d
|
||||
#define HCI_OP_READ_DEF_LINK_POLICY 0x080e
|
||||
#define HCI_OP_WRITE_DEF_LINK_POLICY 0x080f
|
||||
#define HCI_OP_SNIFF_SUBRATE 0x0811
|
||||
#define HCI_OP_Write_Link_Policy_Settings 0x080d
|
||||
#define HCI_OP_SET_EVENT_MASK 0x0c01
|
||||
#define HCI_OP_RESET 0x0c03
|
||||
#define HCI_OP_SET_EVENT_FLT 0x0c05
|
||||
#define HCI_OP_Write_Extended_Inquiry_Response 0x0c52
|
||||
#define HCI_OP_SET_EVENT_MASK 0x0c01
|
||||
#define HCI_OP_RESET 0x0c03
|
||||
#define HCI_OP_SET_EVENT_FLT 0x0c05
|
||||
#define HCI_OP_Write_Extended_Inquiry_Response 0x0c52
|
||||
#define HCI_OP_Write_Simple_Pairing_Mode 0x0c56
|
||||
#define HCI_OP_Read_Buffer_Size 0x1005
|
||||
#define HCI_OP_Host_Buffer_Size 0x0c33
|
||||
@@ -449,42 +444,42 @@ static inline void hci_set_drvdata(struct hci_dev *hdev, void *data)
|
||||
#define HCI_OP_LE_Connection_Update 0x2013
|
||||
|
||||
/* ----- HCI events---- */
|
||||
#define HCI_OP_DISCONNECT 0x0406
|
||||
#define HCI_EV_INQUIRY_COMPLETE 0x01
|
||||
#define HCI_EV_INQUIRY_RESULT 0x02
|
||||
#define HCI_EV_CONN_COMPLETE 0x03
|
||||
#define HCI_EV_CONN_REQUEST 0x04
|
||||
#define HCI_EV_DISCONN_COMPLETE 0x05
|
||||
#define HCI_EV_AUTH_COMPLETE 0x06
|
||||
#define HCI_EV_REMOTE_NAME 0x07
|
||||
#define HCI_EV_ENCRYPT_CHANGE 0x08
|
||||
#define HCI_EV_CHANGE_LINK_KEY_COMPLETE 0x09
|
||||
#define HCI_OP_DISCONNECT 0x0406
|
||||
#define HCI_EV_INQUIRY_COMPLETE 0x01
|
||||
#define HCI_EV_INQUIRY_RESULT 0x02
|
||||
#define HCI_EV_CONN_COMPLETE 0x03
|
||||
#define HCI_EV_CONN_REQUEST 0x04
|
||||
#define HCI_EV_DISCONN_COMPLETE 0x05
|
||||
#define HCI_EV_AUTH_COMPLETE 0x06
|
||||
#define HCI_EV_REMOTE_NAME 0x07
|
||||
#define HCI_EV_ENCRYPT_CHANGE 0x08
|
||||
#define HCI_EV_CHANGE_LINK_KEY_COMPLETE 0x09
|
||||
|
||||
#define HCI_EV_REMOTE_FEATURES 0x0b
|
||||
#define HCI_EV_REMOTE_VERSION 0x0c
|
||||
#define HCI_EV_QOS_SETUP_COMPLETE 0x0d
|
||||
#define HCI_EV_CMD_COMPLETE 0x0e
|
||||
#define HCI_EV_CMD_STATUS 0x0f
|
||||
#define HCI_EV_REMOTE_FEATURES 0x0b
|
||||
#define HCI_EV_REMOTE_VERSION 0x0c
|
||||
#define HCI_EV_QOS_SETUP_COMPLETE 0x0d
|
||||
#define HCI_EV_CMD_COMPLETE 0x0e
|
||||
#define HCI_EV_CMD_STATUS 0x0f
|
||||
|
||||
#define HCI_EV_ROLE_CHANGE 0x12
|
||||
#define HCI_EV_NUM_COMP_PKTS 0x13
|
||||
#define HCI_EV_MODE_CHANGE 0x14
|
||||
#define HCI_EV_PIN_CODE_REQ 0x16
|
||||
#define HCI_EV_LINK_KEY_REQ 0x17
|
||||
#define HCI_EV_LINK_KEY_NOTIFY 0x18
|
||||
#define HCI_EV_CLOCK_OFFSET 0x1c
|
||||
#define HCI_EV_PKT_TYPE_CHANGE 0x1d
|
||||
#define HCI_EV_PSCAN_REP_MODE 0x20
|
||||
#define HCI_EV_ROLE_CHANGE 0x12
|
||||
#define HCI_EV_NUM_COMP_PKTS 0x13
|
||||
#define HCI_EV_MODE_CHANGE 0x14
|
||||
#define HCI_EV_PIN_CODE_REQ 0x16
|
||||
#define HCI_EV_LINK_KEY_REQ 0x17
|
||||
#define HCI_EV_LINK_KEY_NOTIFY 0x18
|
||||
#define HCI_EV_CLOCK_OFFSET 0x1c
|
||||
#define HCI_EV_PKT_TYPE_CHANGE 0x1d
|
||||
#define HCI_EV_PSCAN_REP_MODE 0x20
|
||||
|
||||
#define HCI_EV_INQUIRY_RESULT_WITH_RSSI 0x22
|
||||
#define HCI_EV_REMOTE_EXT_FEATURES 0x23
|
||||
#define HCI_EV_SYNC_CONN_COMPLETE 0x2c
|
||||
#define HCI_EV_SYNC_CONN_CHANGED 0x2d
|
||||
#define HCI_EV_SNIFF_SUBRATE 0x2e
|
||||
#define HCI_EV_EXTENDED_INQUIRY_RESULT 0x2f
|
||||
#define HCI_EV_IO_CAPA_REQUEST 0x31
|
||||
#define HCI_EV_SIMPLE_PAIR_COMPLETE 0x36
|
||||
#define HCI_EV_REMOTE_HOST_FEATURES 0x3d
|
||||
#define HCI_EV_INQUIRY_RESULT_WITH_RSSI 0x22
|
||||
#define HCI_EV_REMOTE_EXT_FEATURES 0x23
|
||||
#define HCI_EV_SYNC_CONN_COMPLETE 0x2c
|
||||
#define HCI_EV_SYNC_CONN_CHANGED 0x2d
|
||||
#define HCI_EV_SNIFF_SUBRATE 0x2e
|
||||
#define HCI_EV_EXTENDED_INQUIRY_RESULT 0x2f
|
||||
#define HCI_EV_IO_CAPA_REQUEST 0x31
|
||||
#define HCI_EV_SIMPLE_PAIR_COMPLETE 0x36
|
||||
#define HCI_EV_REMOTE_HOST_FEATURES 0x3d
|
||||
#define HCI_EV_LE_Meta 0x3e
|
||||
|
||||
/* ULP Event sub code */
|
||||
@@ -499,12 +494,12 @@ static inline void hci_set_drvdata(struct hci_dev *hdev, void *data)
|
||||
#define HCI_BLE_DIRECT_ADV_EVT 0x0b
|
||||
#define HCI_BLE_PHY_UPDATE_COMPLETE_EVT 0x0c
|
||||
#define HCI_LE_EXTENDED_ADVERTISING_REPORT_EVT 0x0D
|
||||
#define HCI_BLE_PERIODIC_ADV_SYNC_EST_EVT 0x0E
|
||||
#define HCI_BLE_PERIODIC_ADV_REPORT_EVT 0x0F
|
||||
#define HCI_BLE_PERIODIC_ADV_SYNC_LOST_EVT 0x10
|
||||
#define HCI_BLE_SCAN_TIMEOUT_EVT 0x11
|
||||
#define HCI_BLE_PERIODIC_ADV_SYNC_EST_EVT 0x0E
|
||||
#define HCI_BLE_PERIODIC_ADV_REPORT_EVT 0x0F
|
||||
#define HCI_BLE_PERIODIC_ADV_SYNC_LOST_EVT 0x10
|
||||
#define HCI_BLE_SCAN_TIMEOUT_EVT 0x11
|
||||
#define HCI_LE_ADVERTISING_SET_TERMINATED_EVT 0x12
|
||||
#define HCI_BLE_SCAN_REQ_RX_EVT 0x13
|
||||
#define HCI_BLE_SCAN_REQ_RX_EVT 0x13
|
||||
#define HCI_BLE_CIS_EST_EVT 0x19
|
||||
#define HCI_BLE_CIS_REQ_EVT 0x1a
|
||||
#define HCI_BLE_CREATE_BIG_CPL_EVT 0x1b
|
||||
@@ -515,35 +510,38 @@ static inline void hci_set_drvdata(struct hci_dev *hdev, void *data)
|
||||
|
||||
#define HCI_VENDOR_SPECIFIC_EVT 0xFF /* Vendor specific events */
|
||||
|
||||
#define CONFIG_MAC_OFFSET_GEN_1_2 (0x3C) //MAC's OFFSET in config/efuse for aic generation 1~2 bluetooth chip
|
||||
#define CONFIG_MAC_OFFSET_GEN_3PLUS (0x44) //MAC's OFFSET in config/efuse for aic generation 3+ bluetooth chip
|
||||
#define CONFIG_MAC_OFFSET_GEN_1_2 \
|
||||
(0x3C) //MAC's OFFSET in config/efuse for aic generation 1~2 bluetooth chip
|
||||
#define CONFIG_MAC_OFFSET_GEN_3PLUS \
|
||||
(0x44) //MAC's OFFSET in config/efuse for aic generation 3+ bluetooth chip
|
||||
|
||||
//Define ioctl cmd the same as HCIDEVUP in the kernel
|
||||
#define DOWN_FW_CFG _IOW('E', 176, int)
|
||||
#define DOWN_FW_CFG _IOW('E', 176, int)
|
||||
//#ifdef CONFIG_SCO_OVER_HCI
|
||||
//#define SET_ISO_CFG _IOW('H', 202, int)
|
||||
//#else
|
||||
#define SET_ISO_CFG _IOW('E', 177, int)
|
||||
#define SET_ISO_CFG _IOW('E', 177, int)
|
||||
//#endif
|
||||
#define RESET_CONTROLLER _IOW('E', 178, int)
|
||||
#define DWFW_CMPLT _IOW('E', 179, int)
|
||||
#define RESET_CONTROLLER _IOW('E', 178, int)
|
||||
#define DWFW_CMPLT _IOW('E', 179, int)
|
||||
|
||||
#define GET_USB_INFO _IOR('E', 180, int)
|
||||
#define GET_USB_INFO _IOR('E', 180, int)
|
||||
|
||||
void bt_data_dump(char* tag, void* data, unsigned long len);
|
||||
void bt_data_dump(char *tag, void *data, unsigned long len);
|
||||
int aic_enqueue(struct sk_buff *skb);
|
||||
int aic_queue_cnt(void);
|
||||
int bt_sdio_recv(u8 *data,u32 data_len);
|
||||
|
||||
int bt_sdio_recv(u8 *data, u32 data_len);
|
||||
|
||||
int btchr_init(void);
|
||||
void btchr_exit(void);
|
||||
int hdev_init(void);
|
||||
void hdev_exit(void);
|
||||
|
||||
|
||||
struct hci_dev *hci_dev_get(int index);
|
||||
int hci_recv_fragment(struct hci_dev *hdev, int type, void *data, int count);
|
||||
|
||||
#endif//_AICWF_SDIO_BT_H_
|
||||
|
||||
#else
|
||||
int btsdio_init(void);
|
||||
void btsdio_remove(void);
|
||||
int bt_sdio_recv(u8 *data, u32 data_len);
|
||||
#endif
|
||||
#endif //_AICWF_SDIO_BT_H_
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -14,20 +14,19 @@
|
||||
#include "rwnx_defs.h"
|
||||
|
||||
typedef struct _android_wifi_priv_cmd {
|
||||
char *buf;
|
||||
int used_len;
|
||||
int total_len;
|
||||
char *buf;
|
||||
int used_len;
|
||||
int total_len;
|
||||
} android_wifi_priv_cmd;
|
||||
|
||||
#ifdef CONFIG_COMPAT
|
||||
typedef struct _compat_android_wifi_priv_cmd {
|
||||
compat_caddr_t buf;
|
||||
int used_len;
|
||||
int total_len;
|
||||
compat_caddr_t buf;
|
||||
int used_len;
|
||||
int total_len;
|
||||
} compat_android_wifi_priv_cmd;
|
||||
#endif /* CONFIG_COMPAT */
|
||||
|
||||
int android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
|
||||
|
||||
#endif /* _AIC_PRIV_CMD_H_ */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -3,8 +3,8 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define GOOGLE_OUI 0x001A11
|
||||
#define BRCM_OUI 0x001018
|
||||
#define GOOGLE_OUI 0x001A11
|
||||
#define BRCM_OUI 0x001018
|
||||
|
||||
typedef enum {
|
||||
START_MKEEP_ALIVE,
|
||||
@@ -17,49 +17,49 @@ typedef enum {
|
||||
|
||||
/* define all vendor startup commands between 0x0 and 0x0FFF */
|
||||
VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
|
||||
VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
|
||||
VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
|
||||
|
||||
/* define all GScan related commands between 0x1000 and 0x10FF */
|
||||
ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
|
||||
ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
|
||||
ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
|
||||
|
||||
/* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
|
||||
ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
|
||||
ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
|
||||
ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
|
||||
|
||||
/* define all RTT related commands between 0x1100 and 0x11FF */
|
||||
ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
|
||||
ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
|
||||
ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
|
||||
|
||||
ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
|
||||
ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
|
||||
ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
|
||||
|
||||
/* define all Logger related commands between 0x1400 and 0x14FF */
|
||||
ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400,
|
||||
ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END = 0x14FF,
|
||||
ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END = 0x14FF,
|
||||
|
||||
/* define all wifi offload related commands between 0x1600 and 0x16FF */
|
||||
ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600,
|
||||
ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END = 0x16FF,
|
||||
ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END = 0x16FF,
|
||||
|
||||
/* define all NAN related commands between 0x1700 and 0x17FF */
|
||||
ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700,
|
||||
ANDROID_NL80211_SUBCMD_NAN_RANGE_END = 0x17FF,
|
||||
ANDROID_NL80211_SUBCMD_NAN_RANGE_END = 0x17FF,
|
||||
|
||||
/* define all Android Packet Filter related commands between 0x1800 and 0x18FF */
|
||||
ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800,
|
||||
ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END = 0x18FF,
|
||||
ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END = 0x18FF,
|
||||
|
||||
/* This is reserved for future usage */
|
||||
|
||||
} ANDROID_VENDOR_SUB_COMMAND;
|
||||
|
||||
typedef enum {
|
||||
WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE = ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START,
|
||||
WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE =
|
||||
ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START,
|
||||
WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE,
|
||||
} WIFI_OFFLOAD_SUB_COMMAND;
|
||||
|
||||
|
||||
enum mkeep_alive_attributes {
|
||||
MKEEP_ALIVE_ATTRIBUTE_ID = 0x1,
|
||||
MKEEP_ALIVE_ATTRIBUTE_IP_PKT,
|
||||
@@ -117,36 +117,53 @@ enum logger_attributes {
|
||||
LOGGER_ATTRIBUTE_MAX = LOGGER_ATTRIBUTE_AFTER_LAST - 1,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_APF
|
||||
enum wifi_apf_attr {
|
||||
APF_ATTRIBUTE_VERSION,
|
||||
APF_ATTRIBUTE_MAX_LEN,
|
||||
APF_ATTRIBUTE_PROGRAM,
|
||||
APF_ATTRIBUTE_PROGRAM_LEN,
|
||||
APF_ATTRIBUTE_LAST,
|
||||
APF_ATTRIBUTE_MAX = APF_ATTRIBUTE_LAST - 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
enum wifi_sub_command {
|
||||
GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
|
||||
GSCAN_SUBCMD_SET_CONFIG, /* 0x1001 */
|
||||
GSCAN_SUBCMD_SET_SCAN_CONFIG, /* 0x1002 */
|
||||
GSCAN_SUBCMD_ENABLE_GSCAN, /* 0x1003 */
|
||||
GSCAN_SUBCMD_GET_SCAN_RESULTS, /* 0x1004 */
|
||||
GSCAN_SUBCMD_SCAN_RESULTS, /* 0x1005 */
|
||||
GSCAN_SUBCMD_SET_HOTLIST, /* 0x1006 */
|
||||
GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG, /* 0x1007 */
|
||||
GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS, /* 0x1008 */
|
||||
GSCAN_SUBCMD_GET_CHANNEL_LIST, /* 0x1009 */
|
||||
WIFI_SUBCMD_GET_FEATURE_SET, /* 0x100A */
|
||||
WIFI_SUBCMD_GET_FEATURE_SET_MATRIX, /* 0x100B */
|
||||
WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI, /* 0x100C */
|
||||
WIFI_SUBCMD_NODFS_SET, /* 0x100D */
|
||||
WIFI_SUBCMD_SET_COUNTRY_CODE, /* 0x100E */
|
||||
GSCAN_SUBCMD_GET_CAPABILITIES =
|
||||
ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
|
||||
GSCAN_SUBCMD_SET_CONFIG, /* 0x1001 */
|
||||
GSCAN_SUBCMD_SET_SCAN_CONFIG, /* 0x1002 */
|
||||
GSCAN_SUBCMD_ENABLE_GSCAN, /* 0x1003 */
|
||||
GSCAN_SUBCMD_GET_SCAN_RESULTS, /* 0x1004 */
|
||||
GSCAN_SUBCMD_SCAN_RESULTS, /* 0x1005 */
|
||||
GSCAN_SUBCMD_SET_HOTLIST, /* 0x1006 */
|
||||
GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG, /* 0x1007 */
|
||||
GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS, /* 0x1008 */
|
||||
GSCAN_SUBCMD_GET_CHANNEL_LIST, /* 0x1009 */
|
||||
WIFI_SUBCMD_GET_FEATURE_SET, /* 0x100A */
|
||||
WIFI_SUBCMD_GET_FEATURE_SET_MATRIX, /* 0x100B */
|
||||
WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI, /* 0x100C */
|
||||
WIFI_SUBCMD_NODFS_SET, /* 0x100D */
|
||||
WIFI_SUBCMD_SET_COUNTRY_CODE, /* 0x100E */
|
||||
/* Add more sub commands here */
|
||||
GSCAN_SUBCMD_SET_EPNO_SSID, /* 0x100F */
|
||||
WIFI_SUBCMD_SET_SSID_WHITE_LIST, /* 0x1010 */
|
||||
WIFI_SUBCMD_SET_ROAM_PARAMS, /* 0x1011 */
|
||||
WIFI_SUBCMD_ENABLE_LAZY_ROAM, /* 0x1012 */
|
||||
WIFI_SUBCMD_SET_BSSID_PREF, /* 0x1013 */
|
||||
WIFI_SUBCMD_SET_BSSID_BLACKLIST, /* 0x1014 */
|
||||
GSCAN_SUBCMD_ANQPO_CONFIG, /* 0x1015 */
|
||||
WIFI_SUBCMD_SET_RSSI_MONITOR, /* 0x1016 */
|
||||
WIFI_SUBCMD_CONFIG_ND_OFFLOAD, /* 0x1017 */
|
||||
GSCAN_SUBCMD_SET_EPNO_SSID, /* 0x100F */
|
||||
WIFI_SUBCMD_SET_SSID_WHITE_LIST, /* 0x1010 */
|
||||
WIFI_SUBCMD_SET_ROAM_PARAMS, /* 0x1011 */
|
||||
WIFI_SUBCMD_ENABLE_LAZY_ROAM, /* 0x1012 */
|
||||
WIFI_SUBCMD_SET_BSSID_PREF, /* 0x1013 */
|
||||
WIFI_SUBCMD_SET_BSSID_BLACKLIST, /* 0x1014 */
|
||||
GSCAN_SUBCMD_ANQPO_CONFIG, /* 0x1015 */
|
||||
WIFI_SUBCMD_SET_RSSI_MONITOR, /* 0x1016 */
|
||||
WIFI_SUBCMD_CONFIG_ND_OFFLOAD, /* 0x1017 */
|
||||
WIFI_SUBCMD_SET_LATENCY_MODE, /* 0x1018 */
|
||||
/* Add more sub commands here */
|
||||
GSCAN_SUBCMD_MAX,
|
||||
APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START,
|
||||
APF_SUBCMD_GET_CAPABILITIES =
|
||||
ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START,
|
||||
APF_SUBCMD_SET_FILTER,
|
||||
#ifdef CONFIG_APF
|
||||
APF_SUBCMD_READ_FILTER_DATA,
|
||||
#endif
|
||||
};
|
||||
|
||||
enum gscan_attributes {
|
||||
@@ -163,18 +180,18 @@ enum gscan_attributes {
|
||||
GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
|
||||
|
||||
GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
|
||||
GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, /* indicates no more results */
|
||||
GSCAN_ATTRIBUTE_FLUSH_FEATURE, /* Flush all the configs */
|
||||
GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, /* indicates no more results */
|
||||
GSCAN_ATTRIBUTE_FLUSH_FEATURE, /* Flush all the configs */
|
||||
GSCAN_ENABLE_FULL_SCAN_RESULTS,
|
||||
GSCAN_ATTRIBUTE_REPORT_EVENTS,
|
||||
|
||||
/* remaining reserved for additional attributes */
|
||||
GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
|
||||
GSCAN_ATTRIBUTE_FLUSH_RESULTS,
|
||||
GSCAN_ATTRIBUTE_SCAN_RESULTS, /* flat array of wifi_scan_result */
|
||||
GSCAN_ATTRIBUTE_SCAN_ID, /* indicates scan number */
|
||||
GSCAN_ATTRIBUTE_SCAN_FLAGS, /* indicates if scan was aborted */
|
||||
GSCAN_ATTRIBUTE_AP_FLAGS, /* flags on significant change event */
|
||||
GSCAN_ATTRIBUTE_SCAN_RESULTS, /* flat array of wifi_scan_result */
|
||||
GSCAN_ATTRIBUTE_SCAN_ID, /* indicates scan number */
|
||||
GSCAN_ATTRIBUTE_SCAN_FLAGS, /* indicates if scan was aborted */
|
||||
GSCAN_ATTRIBUTE_AP_FLAGS, /* flags on significant change event */
|
||||
GSCAN_ATTRIBUTE_NUM_CHANNELS,
|
||||
GSCAN_ATTRIBUTE_CHANNEL_LIST,
|
||||
GSCAN_ATTRIBUTE_CH_BUCKET_BITMASK,
|
||||
@@ -190,6 +207,7 @@ enum andr_wifi_attributes {
|
||||
ANDR_WIFI_ATTRIBUTE_NODFS_SET,
|
||||
ANDR_WIFI_ATTRIBUTE_COUNTRY,
|
||||
ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE,
|
||||
ANDR_WIFI_ATTRIBUTE_LATENCY_MODE,
|
||||
// Add more attribute here
|
||||
ANDR_WIFI_ATTRIBUTE_AFTER_LAST,
|
||||
ANDR_WIFI_ATTRIBUTE_MAX = ANDR_WIFI_ATTRIBUTE_AFTER_LAST - 1,
|
||||
@@ -197,45 +215,61 @@ enum andr_wifi_attributes {
|
||||
|
||||
enum wifi_support_feature {
|
||||
/* Feature enums */
|
||||
WIFI_FEATURE_INFRA = 0x0001, /* Basic infrastructure mode */
|
||||
WIFI_FEATURE_INFRA_5G = 0x0002, /* Support for 5, GHz Band */
|
||||
WIFI_FEATURE_HOTSPOT = 0x0004, /* Support for GAS/ANQP */
|
||||
WIFI_FEATURE_P2P = 0x0008, /* Wifi-Direct */
|
||||
WIFI_FEATURE_SOFT_AP = 0x0010, /* Soft AP */
|
||||
WIFI_FEATURE_GSCAN = 0x0020, /* Google-Scan APIs */
|
||||
WIFI_FEATURE_NAN = 0x0040, /* Neighbor Awareness Networking */
|
||||
WIFI_FEATURE_D2D_RTT = 0x0080, /* Device-to-device RTT */
|
||||
WIFI_FEATURE_D2AP_RTT = 0x0100, /* Device-to-AP RTT */
|
||||
WIFI_FEATURE_BATCH_SCAN = 0x0200, /* Batched Scan (legacy) */
|
||||
WIFI_FEATURE_PNO = 0x0400, /* Preferred network offload */
|
||||
WIFI_FEATURE_ADDITIONAL_STA = 0x0800, /* Support for two STAs */
|
||||
WIFI_FEATURE_TDLS = 0x1000, /* Tunnel directed link setup */
|
||||
WIFI_FEATURE_TDLS_OFFCHANNEL = 0x2000, /* Support for TDLS off channel */
|
||||
WIFI_FEATURE_EPR = 0x4000, /* Enhanced power reporting */
|
||||
WIFI_FEATURE_AP_STA = 0x8000, /* Support for AP STA Concurrency */
|
||||
WIFI_FEATURE_LINK_LAYER_STATS = 0x10000, /* Support for Linkstats */
|
||||
WIFI_FEATURE_LOGGER = 0x20000, /* WiFi Logger */
|
||||
WIFI_FEATURE_HAL_EPNO = 0x40000, /* WiFi PNO enhanced */
|
||||
WIFI_FEATURE_RSSI_MONITOR = 0x80000, /* RSSI Monitor */
|
||||
WIFI_FEATURE_MKEEP_ALIVE = 0x100000, /* WiFi mkeep_alive */
|
||||
WIFI_FEATURE_CONFIG_NDO = 0x200000, /* ND offload configure */
|
||||
WIFI_FEATURE_TX_TRANSMIT_POWER = 0x400000, /* Capture Tx transmit power levels */
|
||||
WIFI_FEATURE_CONTROL_ROAMING = 0x800000, /* Enable/Disable firmware roaming */
|
||||
WIFI_FEATURE_IE_WHITELIST = 0x1000000, /* Support Probe IE white listing */
|
||||
WIFI_FEATURE_SCAN_RAND = 0x2000000, /* Support MAC & Probe Sequence Number randomization */
|
||||
WIFI_FEATURE_INVALID = 0xFFFFFFFF, /* Invalid Feature */
|
||||
WIFI_FEATURE_INFRA = 0x0001, /* Basic infrastructure mode */
|
||||
WIFI_FEATURE_INFRA_5G = 0x0002, /* Support for 5, GHz Band */
|
||||
WIFI_FEATURE_HOTSPOT = 0x0004, /* Support for GAS/ANQP */
|
||||
WIFI_FEATURE_P2P = 0x0008, /* Wifi-Direct */
|
||||
WIFI_FEATURE_SOFT_AP = 0x0010, /* Soft AP */
|
||||
WIFI_FEATURE_GSCAN = 0x0020, /* Google-Scan APIs */
|
||||
WIFI_FEATURE_NAN = 0x0040, /* Neighbor Awareness Networking */
|
||||
WIFI_FEATURE_D2D_RTT = 0x0080, /* Device-to-device RTT */
|
||||
WIFI_FEATURE_D2AP_RTT = 0x0100, /* Device-to-AP RTT */
|
||||
WIFI_FEATURE_BATCH_SCAN = 0x0200, /* Batched Scan (legacy) */
|
||||
WIFI_FEATURE_PNO = 0x0400, /* Preferred network offload */
|
||||
WIFI_FEATURE_ADDITIONAL_STA =
|
||||
0x0800, /* Support for two STAs */
|
||||
WIFI_FEATURE_TDLS = 0x1000, /* Tunnel directed link setup */
|
||||
WIFI_FEATURE_TDLS_OFFCHANNEL =
|
||||
0x2000, /* Support for TDLS off channel */
|
||||
WIFI_FEATURE_EPR = 0x4000, /* Enhanced power reporting */
|
||||
WIFI_FEATURE_AP_STA = 0x8000, /* Support for AP STA Concurrency */
|
||||
WIFI_FEATURE_LINK_LAYER_STATS =
|
||||
0x10000, /* Support for Linkstats */
|
||||
WIFI_FEATURE_LOGGER = 0x20000, /* WiFi Logger */
|
||||
WIFI_FEATURE_HAL_EPNO = 0x40000, /* WiFi PNO enhanced */
|
||||
WIFI_FEATURE_RSSI_MONITOR =
|
||||
0x80000, /* RSSI Monitor */
|
||||
WIFI_FEATURE_MKEEP_ALIVE =
|
||||
0x100000, /* WiFi mkeep_alive */
|
||||
WIFI_FEATURE_CONFIG_NDO =
|
||||
0x200000, /* ND offload configure */
|
||||
WIFI_FEATURE_TX_TRANSMIT_POWER =
|
||||
0x400000, /* Capture Tx transmit power levels */
|
||||
WIFI_FEATURE_CONTROL_ROAMING =
|
||||
0x800000, /* Enable/Disable firmware roaming */
|
||||
WIFI_FEATURE_IE_WHITELIST =
|
||||
0x1000000, /* Support Probe IE white listing */
|
||||
WIFI_FEATURE_SCAN_RAND =
|
||||
0x2000000, /* Support MAC & Probe Sequence Number randomization */
|
||||
WIFI_FEATURE_SET_LATENCY_MODE =
|
||||
0x40000000, /* Support Latency mode setting */
|
||||
WIFI_FEATURE_INVALID =
|
||||
0xFFFFFFFF, /* Invalid Feature */
|
||||
};
|
||||
|
||||
enum wifi_logger_feature {
|
||||
WIFI_LOGGER_MEMORY_DUMP_SUPPORTED = (1 << (0)), // Memory dump of FW
|
||||
WIFI_LOGGER_PER_PACKET_TX_RX_STATUS_SUPPORTED = (1 << (1)), // PKT status
|
||||
WIFI_LOGGER_CONNECT_EVENT_SUPPORTED = (1 << (2)), // Connectivity event
|
||||
WIFI_LOGGER_POWER_EVENT_SUPPORTED = (1 << (3)), // POWER of Driver
|
||||
WIFI_LOGGER_WAKE_LOCK_SUPPORTED = (1 << (4)), // WAKE LOCK of Driver
|
||||
WIFI_LOGGER_VERBOSE_SUPPORTED = (1 << (5)), // verbose log of FW
|
||||
WIFI_LOGGER_WATCHDOG_TIMER_SUPPORTED = (1 << (6)), // monitor the health of FW
|
||||
WIFI_LOGGER_DRIVER_DUMP_SUPPORTED = (1 << (7)), // dumps driver state
|
||||
WIFI_LOGGER_PACKET_FATE_SUPPORTED = (1 << (8)), // tracks connection packets' fate
|
||||
WIFI_LOGGER_MEMORY_DUMP_SUPPORTED = (1 << (0)), // Memory dump of FW
|
||||
WIFI_LOGGER_PER_PACKET_TX_RX_STATUS_SUPPORTED =
|
||||
(1 << (1)), // PKT status
|
||||
WIFI_LOGGER_CONNECT_EVENT_SUPPORTED = (1 << (2)), // Connectivity event
|
||||
WIFI_LOGGER_POWER_EVENT_SUPPORTED = (1 << (3)), // POWER of Driver
|
||||
WIFI_LOGGER_WAKE_LOCK_SUPPORTED = (1 << (4)), // WAKE LOCK of Driver
|
||||
WIFI_LOGGER_VERBOSE_SUPPORTED = (1 << (5)), // verbose log of FW
|
||||
WIFI_LOGGER_WATCHDOG_TIMER_SUPPORTED =
|
||||
(1 << (6)), // monitor the health of FW
|
||||
WIFI_LOGGER_DRIVER_DUMP_SUPPORTED = (1 << (7)), // dumps driver state
|
||||
WIFI_LOGGER_PACKET_FATE_SUPPORTED =
|
||||
(1 << (8)), // tracks connection packets' fate
|
||||
};
|
||||
|
||||
enum wake_stats_attributes {
|
||||
@@ -266,20 +300,19 @@ enum wake_stats_attributes {
|
||||
|
||||
enum vendor_nl80211_subcmd {
|
||||
/* copied from wpa_supplicant brcm definations */
|
||||
VENDOR_NL80211_SUBCMD_UNSPEC = 0,
|
||||
VENDOR_NL80211_SUBCMD_UNSPEC = 0,
|
||||
VENDOR_NL80211_SUBCMD_SET_PMK = 4,
|
||||
VENDOR_NL80211_SUBCMD_SET_MAC = 6,
|
||||
VENDOR_NL80211_SCMD_ACS = 9,
|
||||
VENDOR_NL80211_SCMD_MAX = 10,
|
||||
VENDOR_NL80211_SCMD_ACS = 9,
|
||||
VENDOR_NL80211_SCMD_MAX = 10,
|
||||
};
|
||||
|
||||
enum nl80211_vendor_subcmd_attributes {
|
||||
WIFI_VENDOR_ATTR_DRIVER_CMD = 0,
|
||||
WIFI_VENDOR_ATTR_DRIVER_KEY_PMK = 1,
|
||||
WIFI_VENDOR_ATTR_DRIVER_MAC_ADDR = 3,
|
||||
WIFI_VENDOR_ATTR_DRIVER_CMD = 0,
|
||||
WIFI_VENDOR_ATTR_DRIVER_KEY_PMK = 1,
|
||||
WIFI_VENDOR_ATTR_DRIVER_MAC_ADDR = 3,
|
||||
WIFI_VENDOR_ATTR_DRIVER_AFTER_LAST = 5,
|
||||
WIFI_VENDOR_ATTR_DRIVER_MAX =
|
||||
WIFI_VENDOR_ATTR_DRIVER_AFTER_LAST - 1,
|
||||
WIFI_VENDOR_ATTR_DRIVER_MAX = WIFI_VENDOR_ATTR_DRIVER_AFTER_LAST - 1,
|
||||
};
|
||||
|
||||
typedef int wifi_ring_buffer_id;
|
||||
@@ -296,51 +329,50 @@ struct wifi_ring_buffer_status {
|
||||
};
|
||||
|
||||
struct rx_data_cnt_details_t {
|
||||
int rx_unicast_cnt; /*Total rx unicast packet which woke up host */
|
||||
int rx_multicast_cnt; /*Total rx multicast packet which woke up host */
|
||||
int rx_broadcast_cnt; /*Total rx broadcast packet which woke up host */
|
||||
int rx_unicast_cnt; /*Total rx unicast packet which woke up host */
|
||||
int rx_multicast_cnt; /*Total rx multicast packet which woke up host */
|
||||
int rx_broadcast_cnt; /*Total rx broadcast packet which woke up host */
|
||||
};
|
||||
|
||||
struct rx_wake_pkt_type_classification_t {
|
||||
int icmp_pkt; /*wake icmp packet count */
|
||||
int icmp6_pkt; /*wake icmp6 packet count */
|
||||
int icmp6_ra; /*wake icmp6 RA packet count */
|
||||
int icmp6_na; /*wake icmp6 NA packet count */
|
||||
int icmp6_ns; /*wake icmp6 NS packet count */
|
||||
int icmp_pkt; /*wake icmp packet count */
|
||||
int icmp6_pkt; /*wake icmp6 packet count */
|
||||
int icmp6_ra; /*wake icmp6 RA packet count */
|
||||
int icmp6_na; /*wake icmp6 NA packet count */
|
||||
int icmp6_ns; /*wake icmp6 NS packet count */
|
||||
//ToDo: Any more interesting classification to add?
|
||||
};
|
||||
|
||||
struct rx_multicast_cnt_t{
|
||||
struct rx_multicast_cnt_t {
|
||||
int ipv4_rx_multicast_addr_cnt; /*Rx wake packet was ipv4 multicast */
|
||||
int ipv6_rx_multicast_addr_cnt; /*Rx wake packet was ipv6 multicast */
|
||||
int other_rx_multicast_addr_cnt;/*Rx wake packet was non-ipv4 and non-ipv6*/
|
||||
int other_rx_multicast_addr_cnt; /*Rx wake packet was non-ipv4 and non-ipv6*/
|
||||
};
|
||||
|
||||
struct wlan_driver_wake_reason_cnt_t {
|
||||
int total_cmd_event_wake; /* Total count of cmd event wakes */
|
||||
int *cmd_event_wake_cnt; /* Individual wake count array, each index a reason */
|
||||
int cmd_event_wake_cnt_sz; /* Max number of cmd event wake reasons */
|
||||
int cmd_event_wake_cnt_used; /* Number of cmd event wake reasons specific to the driver */
|
||||
int total_cmd_event_wake; /* Total count of cmd event wakes */
|
||||
int *cmd_event_wake_cnt; /* Individual wake count array, each index a reason */
|
||||
int cmd_event_wake_cnt_sz; /* Max number of cmd event wake reasons */
|
||||
int cmd_event_wake_cnt_used; /* Number of cmd event wake reasons specific to the driver */
|
||||
|
||||
int total_driver_fw_local_wake; /* Total count of drive/fw wakes, for local reasons */
|
||||
int *driver_fw_local_wake_cnt; /* Individual wake count array, each index a reason */
|
||||
int driver_fw_local_wake_cnt_sz; /* Max number of local driver/fw wake reasons */
|
||||
int total_driver_fw_local_wake; /* Total count of drive/fw wakes, for local reasons */
|
||||
int *driver_fw_local_wake_cnt; /* Individual wake count array, each index a reason */
|
||||
int driver_fw_local_wake_cnt_sz; /* Max number of local driver/fw wake reasons */
|
||||
int driver_fw_local_wake_cnt_used; /* Number of local driver/fw wake reasons specific to the driver */
|
||||
|
||||
int total_rx_data_wake; /* total data rx packets, that woke up host */
|
||||
int total_rx_data_wake; /* total data rx packets, that woke up host */
|
||||
struct rx_data_cnt_details_t rx_wake_details;
|
||||
struct rx_wake_pkt_type_classification_t rx_wake_pkt_classification_info;
|
||||
struct rx_multicast_cnt_t rx_multicast_wake_pkt_info;
|
||||
};
|
||||
|
||||
typedef struct wl_mkeep_alive_pkt {
|
||||
u16 version; /* Version for mkeep_alive */
|
||||
u16 length; /* length of fixed parameters in the structure */
|
||||
u32 period_msec; /* high bit on means immediate send */
|
||||
u16 version; /* Version for mkeep_alive */
|
||||
u16 length; /* length of fixed parameters in the structure */
|
||||
u32 period_msec; /* high bit on means immediate send */
|
||||
u16 len_bytes;
|
||||
u8 keep_alive_id; /* 0 - 3 for N = 4 */
|
||||
u8 data[1];
|
||||
u8 keep_alive_id; /* 0 - 3 for N = 4 */
|
||||
u8 data[1];
|
||||
} wl_mkeep_alive_pkt_t;
|
||||
|
||||
#endif /* _AIC_VENDOR_H */
|
||||
|
||||
|
||||
@@ -3,64 +3,159 @@
|
||||
#include "reg_access.h"
|
||||
#include "aicwf_compat_8800d80.h"
|
||||
|
||||
#define FW_USERCONFIG_NAME_8800D80 "aic_userconfig_8800d80.txt"
|
||||
#define FW_USERCONFIG_NAME_8800D80 "aic_userconfig_8800d80.txt"
|
||||
#define FW_USERCONFIG_NAME_8800D80X2 "aic_userconfig_8800d80x2.txt"
|
||||
#define FW_POWERLIMIT_NAME_8800D80 "aic_powerlimit_8800d80.txt"
|
||||
|
||||
int rwnx_request_firmware_common(struct rwnx_hw *rwnx_hw,
|
||||
u32** buffer, const char *filename);
|
||||
int rwnx_request_firmware_common(struct rwnx_hw *rwnx_hw, u32 **buffer,
|
||||
const char *filename);
|
||||
void rwnx_plat_userconfig_parsing2(char *buffer, int size);
|
||||
void rwnx_plat_userconfig_parsing3(char *buffer, int size);
|
||||
void rwnx_plat_userconfig_parsing_8800d80x2(char *buffer, int size);
|
||||
|
||||
void rwnx_release_firmware_common(u32** buffer);
|
||||
void rwnx_release_firmware_common(u32 **buffer);
|
||||
|
||||
int aicwf_set_rf_config_8800d80(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm)
|
||||
int aicwf_set_rf_config_8800d80(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_set_rf_calib_cfm *cfm)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if ((ret = rwnx_send_txpwr_lvl_v3_req(rwnx_hw))) {
|
||||
return -1;
|
||||
if (rwnx_hw->sdiodev->chipid == PRODUCT_ID_AIC8800D80) {
|
||||
if ((ret = rwnx_send_txpwr_lvl_v3_req(rwnx_hw))) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((ret = rwnx_send_txpwr_ofst2x_req(rwnx_hw))) {
|
||||
return -1;
|
||||
}
|
||||
} else if (rwnx_hw->sdiodev->chipid == PRODUCT_ID_AIC8800D80X2) {
|
||||
if ((ret = rwnx_send_txpwr_lvl_v4_req(rwnx_hw))) {
|
||||
return -1;
|
||||
}
|
||||
if ((ret = rwnx_send_txpwr_ofst2x_v2_req(rwnx_hw))) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if ((ret = rwnx_send_txpwr_lvl_adj_req(rwnx_hw))) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((ret = rwnx_send_txpwr_ofst2x_req(rwnx_hw))) {
|
||||
if ((ret = rwnx_send_rf_calib_req(rwnx_hw, cfm))) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((ret = rwnx_send_rf_calib_req(rwnx_hw, cfm))) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0 ;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rwnx_plat_userconfig_load_8800d80(struct rwnx_hw *rwnx_hw)
|
||||
int rwnx_plat_userconfig_load_8800d80(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
int size;
|
||||
u32 *dst=NULL;
|
||||
char *filename = FW_USERCONFIG_NAME_8800D80;
|
||||
int size;
|
||||
u32 *dst = NULL;
|
||||
char *filename = FW_USERCONFIG_NAME_8800D80;
|
||||
|
||||
AICWFDBG(LOGINFO, "userconfig file path:%s \r\n", filename);
|
||||
AICWFDBG(LOGINFO, "userconfig file path:%s \r\n", filename);
|
||||
|
||||
/* load file */
|
||||
size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
|
||||
if (size <= 0) {
|
||||
AICWFDBG(LOGERROR, "wrong size of firmware file\n");
|
||||
dst = NULL;
|
||||
return 0;
|
||||
}
|
||||
/* load file */
|
||||
size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
|
||||
if (size <= 0) {
|
||||
AICWFDBG(LOGERROR, "wrong size of firmware file\n");
|
||||
dst = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Copy the file on the Embedded side */
|
||||
AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size);
|
||||
AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size);
|
||||
|
||||
rwnx_plat_userconfig_parsing3((char *)dst, size);
|
||||
|
||||
rwnx_release_firmware_common(&dst);
|
||||
|
||||
AICWFDBG(LOGINFO, "userconfig download complete\n\n");
|
||||
return 0;
|
||||
rwnx_release_firmware_common(&dst);
|
||||
|
||||
AICWFDBG(LOGINFO, "userconfig download complete\n\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rwnx_plat_userconfig_load_8800d80x2(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
int size;
|
||||
u32 *dst = NULL;
|
||||
char *filename = FW_USERCONFIG_NAME_8800D80X2;
|
||||
|
||||
AICWFDBG(LOGINFO, "userconfig file path:%s \r\n", filename);
|
||||
|
||||
/* load file */
|
||||
size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
|
||||
if (size <= 0) {
|
||||
AICWFDBG(LOGERROR, "wrong size of firmware file\n");
|
||||
dst = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Copy the file on the Embedded side */
|
||||
AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size);
|
||||
|
||||
rwnx_plat_userconfig_parsing_8800d80x2((char *)dst, size);
|
||||
|
||||
rwnx_release_firmware_common(&dst);
|
||||
|
||||
AICWFDBG(LOGINFO, "userconfig download complete\n\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_POWER_LIMIT
|
||||
extern char country_code[4];
|
||||
int rwnx_plat_powerlimit_load_8800d80(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
int size;
|
||||
u32 *dst = NULL;
|
||||
char *filename = FW_POWERLIMIT_NAME_8800D80;
|
||||
|
||||
AICWFDBG(LOGDEBUG, "powerlimit file path:%s \r\n", filename);
|
||||
|
||||
/* load file */
|
||||
size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
|
||||
if (size <= 0) {
|
||||
AICWFDBG(LOGERROR, "wrong size of cfg file\n");
|
||||
dst = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
AICWFDBG(LOGDEBUG, "### Load file done: %s, size=%d\n", filename, size);
|
||||
|
||||
/* parsing the file */
|
||||
rwnx_plat_powerlimit_parsing((char *)dst, size, country_code);
|
||||
|
||||
rwnx_release_firmware_common(&dst);
|
||||
|
||||
AICWFDBG(LOGDEBUG, "powerlimit download complete\n\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rwnx_plat_powerlimit_load_8800d80x2(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
int size;
|
||||
u32 *dst = NULL;
|
||||
char *filename = FW_POWERLIMIT_NAME_8800D80;
|
||||
|
||||
AICWFDBG(LOGDEBUG, "powerlimit file path:%s \r\n", filename);
|
||||
|
||||
/* load file */
|
||||
size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
|
||||
if (size <= 0) {
|
||||
AICWFDBG(LOGERROR, "wrong size of cfg file\n");
|
||||
dst = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
AICWFDBG(LOGDEBUG, "### Load file done: %s, size=%d\n", filename, size);
|
||||
|
||||
/* parsing the file */
|
||||
rwnx_plat_powerlimit_parsing((char *)dst, size, country_code);
|
||||
|
||||
rwnx_release_firmware_common(&dst);
|
||||
|
||||
AICWFDBG(LOGDEBUG, "powerlimit download complete\n\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -2,8 +2,14 @@
|
||||
#define _AICWF_COMPAT_8800D80_H_
|
||||
#include <linux/types.h>
|
||||
|
||||
int aicwf_set_rf_config_8800d80(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm);
|
||||
int rwnx_plat_userconfig_load_8800d80(struct rwnx_hw *rwnx_hw);
|
||||
int aicwf_set_rf_config_8800d80(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_set_rf_calib_cfm *cfm);
|
||||
int rwnx_plat_userconfig_load_8800d80(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_plat_userconfig_load_8800d80x2(struct rwnx_hw *rwnx_hw);
|
||||
|
||||
#ifdef CONFIG_POWER_LIMIT
|
||||
int rwnx_plat_powerlimit_load_8800d80(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_plat_powerlimit_load_8800d80x2(struct rwnx_hw *rwnx_hw);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -2,14 +2,15 @@
|
||||
#include "aic_bsp_export.h"
|
||||
|
||||
#ifdef CONFIG_DPD
|
||||
int aicwf_fdrv_dpd_result_apply_8800dc(struct rwnx_hw * rwnx_hw, rf_misc_ram_lite_t * dpd_res);
|
||||
int aicwf_fdrv_dpd_result_apply_8800dc(struct rwnx_hw *rwnx_hw,
|
||||
rf_misc_ram_lite_t *dpd_res);
|
||||
#ifndef CONFIG_FORCE_DPD_CALIB
|
||||
int aicwf_fdrv_dpd_result_load_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res);
|
||||
int aicwf_fdrv_dpd_result_load_8800dc(struct rwnx_hw *rwnx_hw,
|
||||
rf_misc_ram_lite_t *dpd_res);
|
||||
#endif
|
||||
#endif
|
||||
int aicwf_fdrv_misc_ram_init_8800dc(struct rwnx_hw *rwnx_hw);
|
||||
int aicwf_set_rf_config_8800dc(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm);
|
||||
int rwnx_plat_userconfig_load_8800dc(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_plat_userconfig_load_8800dw(struct rwnx_hw *rwnx_hw);
|
||||
|
||||
|
||||
int aicwf_set_rf_config_8800dc(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_set_rf_calib_cfm *cfm);
|
||||
int rwnx_plat_userconfig_load_8800dc(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_plat_userconfig_load_8800dw(struct rwnx_hw *rwnx_hw);
|
||||
|
||||
@@ -2,39 +2,36 @@
|
||||
|
||||
#define RWNX_FN_ENTRY_STR ">>> %s()\n", __func__
|
||||
|
||||
|
||||
|
||||
/* message levels */
|
||||
#define LOGERROR 0x0001
|
||||
#define LOGINFO 0x0002
|
||||
#define LOGTRACE 0x0004
|
||||
#define LOGDEBUG 0x0008
|
||||
#define LOGDATA 0x0010
|
||||
#define LOGIRQ 0x0020
|
||||
#define LOGSDPWRC 0x0040
|
||||
#define LOGWAKELOCK 0x0080
|
||||
#define LOGRXPOLL 0x0100
|
||||
#define LOGERROR 0x0001
|
||||
#define LOGINFO 0x0002
|
||||
#define LOGTRACE 0x0004
|
||||
#define LOGDEBUG 0x0008
|
||||
#define LOGDATA 0x0010
|
||||
#define LOGIRQ 0x0020
|
||||
#define LOGSDPWRC 0x0040
|
||||
#define LOGWAKELOCK 0x0080
|
||||
#define LOGRXPOLL 0x0100
|
||||
|
||||
extern int aicwf_dbg_level;
|
||||
void rwnx_data_dump(char* tag, void* data, unsigned long len);
|
||||
|
||||
#define AICWF_LOG "AICWFDBG("
|
||||
void rwnx_data_dump(char *tag, void *data, unsigned long len);
|
||||
|
||||
#define AICWF_LOG "AICWFDBG("
|
||||
|
||||
#ifdef DEBUG
|
||||
#define AICWFDBG(level, args, arg...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & level) { \
|
||||
printk(AICWF_LOG#level")\t" args, ##arg); \
|
||||
} \
|
||||
} while (0)
|
||||
#define AICWFDBG(level, args, arg...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & level) { \
|
||||
printk(AICWF_LOG #level ")\t" args, ##arg); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define RWNX_DBG(fmt, ...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & LOGTRACE) { \
|
||||
printk(AICWF_LOG"LOGTRACE)\t"fmt , ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
#define RWNX_DBG(fmt, ...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & LOGTRACE) { \
|
||||
printk(AICWF_LOG "LOGTRACE)\t" fmt, ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
#else
|
||||
|
||||
#define AICWFDBG(level, args, arg...)
|
||||
@@ -43,20 +40,19 @@ do { \
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define RWNX_DBG(fmt, ...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & LOGTRACE) { \
|
||||
printk(AICWF_LOG"LOGTRACE"")\t" fmt, ##__VA_ARGS__); \
|
||||
} \
|
||||
#define RWNX_DBG(fmt, ...) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & LOGTRACE) { \
|
||||
printk(AICWF_LOG "LOGTRACE" \
|
||||
")\t" fmt, \
|
||||
##__VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
#define AICWFDBG(args, level) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & level) { \
|
||||
printk(AICWF_LOG "(%s)\t", #level); \
|
||||
printf args; \
|
||||
} \
|
||||
} while (0)
|
||||
#define AICWFDBG(args, level) \
|
||||
do { \
|
||||
if (aicwf_dbg_level & level) { \
|
||||
printk(AICWF_LOG"(%s)\t" ,#level); \
|
||||
printf args; \
|
||||
} \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -12,86 +12,89 @@ int aic_rxbuff_num_max = 30;
|
||||
|
||||
int aic_rxbuff_size = (64 * 512);
|
||||
|
||||
struct rx_buff *aicwf_prealloc_rxbuff_alloc(spinlock_t *lock)
|
||||
struct rx_buff *aicwf_prealloc_rxbuff_alloc(spinlock_t *lock)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct rx_buff *rxbuff = NULL;
|
||||
unsigned long flags;
|
||||
struct rx_buff *rxbuff = NULL;
|
||||
|
||||
spin_lock_irqsave(lock, flags);
|
||||
if (list_empty(&aic_rx_buff_list.rxbuff_list)) {
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
printk("%s %d, rxbuff list is empty\n", __func__, __LINE__);
|
||||
return NULL;
|
||||
} else {
|
||||
spin_lock_irqsave(lock, flags);
|
||||
if (list_empty(&aic_rx_buff_list.rxbuff_list)) {
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
printk("%s %d, rxbuff list is empty\n", __func__, __LINE__);
|
||||
return NULL;
|
||||
} else {
|
||||
rxbuff = list_first_entry(&aic_rx_buff_list.rxbuff_list,
|
||||
struct rx_buff, queue);
|
||||
struct rx_buff, queue);
|
||||
list_del_init(&rxbuff->queue);
|
||||
atomic_dec(&aic_rx_buff_list.rxbuff_list_len);
|
||||
atomic_dec(&aic_rx_buff_list.rxbuff_list_len);
|
||||
}
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
//printk("len:%d\n", aic_rx_buff_list.rxbuff_list_len);
|
||||
memset(rxbuff->data, 0, aic_rxbuff_size);
|
||||
rxbuff->len = 0;
|
||||
rxbuff->start = NULL;
|
||||
rxbuff->read = NULL;
|
||||
rxbuff->end = NULL;
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
//printk("len:%d\n", aic_rx_buff_list.rxbuff_list_len);
|
||||
memset(rxbuff->data, 0, aic_rxbuff_size);
|
||||
rxbuff->len = 0;
|
||||
rxbuff->start = NULL;
|
||||
rxbuff->read = NULL;
|
||||
rxbuff->end = NULL;
|
||||
|
||||
return rxbuff;
|
||||
return rxbuff;
|
||||
}
|
||||
|
||||
void aicwf_prealloc_rxbuff_free(struct rx_buff *rxbuff, spinlock_t *lock)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(lock, flags);
|
||||
spin_lock_irqsave(lock, flags);
|
||||
list_add_tail(&rxbuff->queue, &aic_rx_buff_list.rxbuff_list);
|
||||
atomic_inc(&aic_rx_buff_list.rxbuff_list_len);
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
}
|
||||
|
||||
int aicwf_prealloc_init()
|
||||
{
|
||||
struct rx_buff *rxbuff;
|
||||
int i = 0;
|
||||
struct rx_buff *rxbuff;
|
||||
int i = 0;
|
||||
|
||||
printk("%s enter\n", __func__);
|
||||
INIT_LIST_HEAD(&aic_rx_buff_list.rxbuff_list);
|
||||
|
||||
for (i = 0 ; i < aic_rxbuff_num_max ; i++) {
|
||||
rxbuff = kzalloc(sizeof(struct rx_buff), GFP_KERNEL);
|
||||
if (rxbuff) {
|
||||
rxbuff->data = kzalloc(aic_rxbuff_size, GFP_KERNEL);
|
||||
if (rxbuff->data == NULL) {
|
||||
printk("failed to alloc rxbuff data\n");
|
||||
kfree(rxbuff);
|
||||
continue;
|
||||
}
|
||||
rxbuff->len = 0;
|
||||
rxbuff->start = NULL;
|
||||
rxbuff->read = NULL;
|
||||
rxbuff->end = NULL;
|
||||
list_add_tail(&rxbuff->queue, &aic_rx_buff_list.rxbuff_list);
|
||||
atomic_inc(&aic_rx_buff_list.rxbuff_list_len);
|
||||
}
|
||||
}
|
||||
printk("%s enter\n", __func__);
|
||||
INIT_LIST_HEAD(&aic_rx_buff_list.rxbuff_list);
|
||||
|
||||
printk("pre alloc rxbuff list len: %d\n", (int)atomic_read(&aic_rx_buff_list.rxbuff_list_len));
|
||||
return 0;
|
||||
for (i = 0; i < aic_rxbuff_num_max; i++) {
|
||||
rxbuff = kzalloc(sizeof(struct rx_buff), GFP_KERNEL);
|
||||
if (rxbuff) {
|
||||
rxbuff->data = kzalloc(aic_rxbuff_size, GFP_KERNEL);
|
||||
if (rxbuff->data == NULL) {
|
||||
printk("failed to alloc rxbuff data\n");
|
||||
kfree(rxbuff);
|
||||
continue;
|
||||
}
|
||||
rxbuff->len = 0;
|
||||
rxbuff->start = NULL;
|
||||
rxbuff->read = NULL;
|
||||
rxbuff->end = NULL;
|
||||
list_add_tail(&rxbuff->queue,
|
||||
&aic_rx_buff_list.rxbuff_list);
|
||||
atomic_inc(&aic_rx_buff_list.rxbuff_list_len);
|
||||
}
|
||||
}
|
||||
|
||||
printk("pre alloc rxbuff list len: %d\n",
|
||||
(int)atomic_read(&aic_rx_buff_list.rxbuff_list_len));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void aicwf_prealloc_exit()
|
||||
{
|
||||
struct rx_buff *rxbuff;
|
||||
struct rx_buff *pos;
|
||||
|
||||
printk("%s enter\n", __func__);
|
||||
struct rx_buff *rxbuff;
|
||||
struct rx_buff *pos;
|
||||
|
||||
printk("free pre alloc rxbuff list %d\n", (int)atomic_read(&aic_rx_buff_list.rxbuff_list_len));
|
||||
list_for_each_entry_safe(rxbuff, pos, &aic_rx_buff_list.rxbuff_list, queue) {
|
||||
list_del_init(&rxbuff->queue);
|
||||
kfree(rxbuff->data);
|
||||
kfree(rxbuff);
|
||||
}
|
||||
printk("%s enter\n", __func__);
|
||||
|
||||
printk("free pre alloc rxbuff list %d\n",
|
||||
(int)atomic_read(&aic_rx_buff_list.rxbuff_list_len));
|
||||
list_for_each_entry_safe (rxbuff, pos, &aic_rx_buff_list.rxbuff_list,
|
||||
queue) {
|
||||
list_del_init(&rxbuff->queue);
|
||||
kfree(rxbuff->data);
|
||||
kfree(rxbuff);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -3,17 +3,17 @@
|
||||
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
struct rx_buff {
|
||||
struct list_head queue;
|
||||
unsigned char *data;
|
||||
u32 len;
|
||||
uint8_t *start;
|
||||
uint8_t *end;
|
||||
uint8_t *read;
|
||||
struct list_head queue;
|
||||
unsigned char *data;
|
||||
u32 len;
|
||||
uint8_t *start;
|
||||
uint8_t *end;
|
||||
uint8_t *read;
|
||||
};
|
||||
|
||||
struct aicwf_rx_buff_list {
|
||||
struct list_head rxbuff_list;
|
||||
atomic_t rxbuff_list_len;
|
||||
struct list_head rxbuff_list;
|
||||
atomic_t rxbuff_list_len;
|
||||
};
|
||||
|
||||
struct rx_buff *aicwf_prealloc_rxbuff_alloc(spinlock_t *lock);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -16,97 +16,110 @@
|
||||
#include <linux/semaphore.h>
|
||||
#include "rwnx_cmds.h"
|
||||
#include "aicwf_rx_prealloc.h"
|
||||
#define AICWF_SDIO_NAME "aicwf_sdio"
|
||||
#define SDIOWIFI_FUNC_BLOCKSIZE 512
|
||||
#define AICWF_SDIO_NAME "aicwf_sdio"
|
||||
#define SDIOWIFI_FUNC_BLOCKSIZE 512
|
||||
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG 0x02
|
||||
#define SDIOWIFI_INTR_CONFIG_REG 0x04
|
||||
#define SDIOWIFI_SLEEP_REG 0x05
|
||||
#define SDIOWIFI_WAKEUP_REG 0x09
|
||||
#define SDIOWIFI_FLOW_CTRL_REG 0x0A
|
||||
#define SDIOWIFI_REGISTER_BLOCK 0x0B
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG 0x11
|
||||
#define SDIOWIFI_BLOCK_CNT_REG 0x12
|
||||
#define SDIOWIFI_FLOWCTRL_MASK_REG 0x7F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR 0x07
|
||||
#define SDIOWIFI_RD_FIFO_ADDR 0x08
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG 0x02
|
||||
#define SDIOWIFI_INTR_CONFIG_REG 0x04
|
||||
#define SDIOWIFI_SLEEP_REG 0x05
|
||||
#define SDIOWIFI_WAKEUP_REG 0x09
|
||||
#define SDIOWIFI_FLOW_CTRL_REG 0x0A
|
||||
#define SDIOWIFI_REGISTER_BLOCK 0x0B
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG 0x11
|
||||
#define SDIOWIFI_BLOCK_CNT_REG 0x12
|
||||
#define SDIOWIFI_FLOWCTRL_MASK_REG 0x7F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR 0x07
|
||||
#define SDIOWIFI_RD_FIFO_ADDR 0x08
|
||||
|
||||
#define SDIOWIFI_INTR_ENABLE_REG_V3 0x00
|
||||
#define SDIOWIFI_INTR_PENDING_REG_V3 0x01
|
||||
#define SDIOWIFI_INTR_TO_DEVICE_REG_V3 0x02
|
||||
#define SDIOWIFI_FLOW_CTRL_Q1_REG_V3 0x03
|
||||
#define SDIOWIFI_MISC_INT_STATUS_REG_V3 0x04
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG_V3 0x05
|
||||
#define SDIOWIFI_BYTEMODE_LEN_MSB_REG_V3 0x06
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG_V3 0x07
|
||||
#define SDIOWIFI_MISC_CTRL_REG_V3 0x08
|
||||
#define SDIOWIFI_FLOW_CTRL_Q2_REG_V3 0x09
|
||||
#define SDIOWIFI_CLK_TEST_RESULT_REG_V3 0x0A
|
||||
#define SDIOWIFI_RD_FIFO_ADDR_V3 0x0F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR_V3 0x10
|
||||
#define SDIOWIFI_INTR_ENABLE_REG_V3 0x00
|
||||
#define SDIOWIFI_INTR_PENDING_REG_V3 0x01
|
||||
#define SDIOWIFI_INTR_TO_DEVICE_REG_V3 0x02
|
||||
#define SDIOWIFI_FLOW_CTRL_Q1_REG_V3 0x03
|
||||
#define SDIOWIFI_MISC_INT_STATUS_REG_V3 0x04
|
||||
#define SDIOWIFI_BYTEMODE_LEN_REG_V3 0x05
|
||||
#define SDIOWIFI_BYTEMODE_LEN_MSB_REG_V3 0x06
|
||||
#define SDIOWIFI_BYTEMODE_ENABLE_REG_V3 0x07
|
||||
#define SDIOWIFI_MISC_CTRL_REG_V3 0x08
|
||||
#define SDIOWIFI_FLOW_CTRL_Q2_REG_V3 0x09
|
||||
#define SDIOWIFI_CLK_TEST_RESULT_REG_V3 0x0A
|
||||
#define SDIOWIFI_RD_FIFO_ADDR_V3 0x0F
|
||||
#define SDIOWIFI_WR_FIFO_ADDR_V3 0x10
|
||||
|
||||
#define SDIOCLK_FREE_RUNNING_BIT (1 << 6)
|
||||
#define SDIOCLK_FREE_RUNNING_BIT (1 << 6)
|
||||
|
||||
#define SDIOWIFI_PWR_CTRL_INTERVAL 30
|
||||
#define FLOW_CTRL_RETRY_COUNT 50
|
||||
#define BUFFER_SIZE 1536
|
||||
#define TAIL_LEN 4
|
||||
#define TXQLEN (2048*4)
|
||||
#define SDIOWIFI_PWR_CTRL_INTERVAL 30
|
||||
#define FLOW_CTRL_RETRY_COUNT 50
|
||||
#define BUFFER_SIZE 1536
|
||||
#define TAIL_LEN 4
|
||||
#define TXQLEN (2048 * 4)
|
||||
|
||||
#define SDIO_SLEEP_ST 0
|
||||
#define SDIO_ACTIVE_ST 1
|
||||
#define SDIO_SLEEP_ST 0
|
||||
#define SDIO_ACTIVE_ST 1
|
||||
|
||||
#define DATA_FLOW_CTRL_THRESH 2
|
||||
#ifdef CONFIG_TX_NETIF_FLOWCTRL
|
||||
#define AICWF_SDIO_TX_LOW_WATER 100
|
||||
#define AICWF_SDIO_TX_HIGH_WATER 500
|
||||
#define AICWF_SDIO_TX_LOW_WATER 100
|
||||
#define AICWF_SDIO_TX_HIGH_WATER 500
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TEMP_CONTROL
|
||||
#define TEMP_GET_INTERVAL (60 * 1000)
|
||||
#define TEMP_THD_1 80 //temperature 1 (℃)
|
||||
#define TEMP_THD_2 95 //temperature 2 (℃)
|
||||
#define BUFFERING_V1 8
|
||||
#define BUFFERING_V2 13
|
||||
#define TMR_INTERVAL_1 60 //timer_1 60ms
|
||||
#define TMR_INTERVAL_2 180 //timer_2 130ms
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
SDIO_TYPE_DATA = 0X00,
|
||||
SDIO_TYPE_CFG = 0X10,
|
||||
SDIO_TYPE_CFG_CMD_RSP = 0X11,
|
||||
SDIO_TYPE_DATA = 0X00,
|
||||
SDIO_TYPE_CFG = 0X10,
|
||||
SDIO_TYPE_CFG_CMD_RSP = 0X11,
|
||||
SDIO_TYPE_CFG_DATA_CFM = 0X12,
|
||||
SDIO_TYPE_CFG_PRINT = 0X13
|
||||
SDIO_TYPE_CFG_PRINT = 0X13
|
||||
} sdio_type;
|
||||
|
||||
/* SDIO Device ID */
|
||||
#define SDIO_VENDOR_ID_AIC8801 0x5449
|
||||
#define SDIO_VENDOR_ID_AIC8800DC 0xc8a1
|
||||
#define SDIO_VENDOR_ID_AIC8800D80 0xc8a1
|
||||
#define SDIO_VENDOR_ID_AIC8801 0x5449
|
||||
#define SDIO_VENDOR_ID_AIC8800DC 0xc8a1
|
||||
#define SDIO_VENDOR_ID_AIC8800D80 0xc8a1
|
||||
#define SDIO_VENDOR_ID_AIC8800D80X2 0xc8a1
|
||||
|
||||
#define SDIO_DEVICE_ID_AIC8801 0x0145
|
||||
#define SDIO_DEVICE_ID_AIC8800DC 0xc08d
|
||||
#define SDIO_DEVICE_ID_AIC8800D80 0x0082
|
||||
#define SDIO_DEVICE_ID_AIC8801 0x0145
|
||||
#define SDIO_DEVICE_ID_AIC8800DC 0xc08d
|
||||
#define SDIO_DEVICE_ID_AIC8800D80 0x0082
|
||||
#define SDIO_DEVICE_ID_AIC8800D80X2 0x2082
|
||||
|
||||
enum AICWF_IC{
|
||||
PRODUCT_ID_AIC8801 = 0,
|
||||
enum AICWF_IC {
|
||||
PRODUCT_ID_AIC8801 = 0,
|
||||
PRODUCT_ID_AIC8800DC,
|
||||
PRODUCT_ID_AIC8800DW,
|
||||
PRODUCT_ID_AIC8800D80
|
||||
PRODUCT_ID_AIC8800D80,
|
||||
PRODUCT_ID_AIC8800D80X2
|
||||
};
|
||||
|
||||
|
||||
struct rwnx_hw;
|
||||
|
||||
struct aic_sdio_reg {
|
||||
u8 bytemode_len_reg;
|
||||
u8 intr_config_reg;
|
||||
u8 sleep_reg;
|
||||
u8 wakeup_reg;
|
||||
u8 flow_ctrl_reg;
|
||||
u8 flowctrl_mask_reg;
|
||||
u8 register_block;
|
||||
u8 bytemode_enable_reg;
|
||||
u8 block_cnt_reg;
|
||||
u8 misc_int_status_reg;
|
||||
u8 rd_fifo_addr;
|
||||
u8 wr_fifo_addr;
|
||||
u8 bytemode_len_reg;
|
||||
u8 intr_config_reg;
|
||||
u8 sleep_reg;
|
||||
u8 wakeup_reg;
|
||||
u8 flow_ctrl_reg;
|
||||
u8 flowctrl_mask_reg;
|
||||
u8 register_block;
|
||||
u8 bytemode_enable_reg;
|
||||
u8 block_cnt_reg;
|
||||
u8 misc_int_status_reg;
|
||||
u8 rd_fifo_addr;
|
||||
u8 wr_fifo_addr;
|
||||
};
|
||||
|
||||
struct aic_sdio_dev {
|
||||
struct rwnx_hw *rwnx_hw;
|
||||
struct sdio_func *func;
|
||||
struct sdio_func *func2;
|
||||
struct device *dev;
|
||||
struct aicwf_bus *bus_if;
|
||||
struct rwnx_cmd_mgr cmd_mgr;
|
||||
@@ -119,7 +132,7 @@ struct aic_sdio_dev {
|
||||
spinlock_t tx_flow_lock;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SDIO_PWRCTRL)
|
||||
#if defined(CONFIG_SDIO_PWRCTRL)
|
||||
//for sdio pwr ctrl
|
||||
struct timer_list timer;
|
||||
uint active_duration;
|
||||
@@ -127,21 +140,46 @@ struct aic_sdio_dev {
|
||||
struct task_struct *pwrctl_tsk;
|
||||
spinlock_t pwrctl_lock;
|
||||
struct semaphore pwrctl_wakeup_sema;
|
||||
#endif
|
||||
#endif
|
||||
u16 chipid;
|
||||
struct aic_sdio_reg sdio_reg;
|
||||
struct aic_sdio_reg sdio_reg;
|
||||
|
||||
spinlock_t wslock;//AIDEN test
|
||||
spinlock_t wslock; //AIDEN test
|
||||
bool oob_enable;
|
||||
atomic_t is_bus_suspend;
|
||||
atomic_t is_bus_suspend;
|
||||
|
||||
#ifdef CONFIG_TEMP_CONTROL
|
||||
spinlock_t tx_flow_lock;
|
||||
struct timer_list netif_timer;
|
||||
struct timer_list tp_ctrl_timer;
|
||||
struct work_struct tp_ctrl_work;
|
||||
struct work_struct netif_work;
|
||||
s8_l cur_temp;
|
||||
bool net_stop;
|
||||
bool on_off; //for command, 0 - off, 1 - on
|
||||
int8_t get_level; //for command, 0 - 100%, 1 - 12%, 2 - 3%
|
||||
int8_t set_level; //for command, 0 - driver auto, 1 - 12%, 2 - 3%
|
||||
int interval_t1;
|
||||
int interval_t2;
|
||||
u8_l cur_stat; //0--normal temp, 1/2--buffering temp
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_TEMP_CONTROL
|
||||
void aicwf_netif_worker(struct work_struct *work);
|
||||
void aicwf_temp_ctrl_worker(struct work_struct *work);
|
||||
void aicwf_temp_ctrl(struct aic_sdio_dev *sdiodev);
|
||||
void aicwf_netif_ctrl(struct aic_sdio_dev *sdiodev, int val);
|
||||
#endif
|
||||
extern struct aicwf_rx_buff_list aic_rx_buff_list;
|
||||
int aicwf_sdio_writeb(struct aic_sdio_dev *sdiodev, uint regaddr, u8 val);
|
||||
int aicwf_sdio_func2_readb(struct aic_sdio_dev *sdiodev, uint regaddr, u8 *val);
|
||||
int aicwf_sdio_func2_writeb(struct aic_sdio_dev *sdiodev, uint regaddr, u8 val);
|
||||
void aicwf_sdio_hal_irqhandler(struct sdio_func *func);
|
||||
|
||||
#if defined(CONFIG_SDIO_PWRCTRL)
|
||||
void aicwf_sdio_pwrctl_timer(struct aic_sdio_dev *sdiodev, uint duration);
|
||||
int aicwf_sdio_pwr_stctl(struct aic_sdio_dev *sdiodev, uint target);
|
||||
int aicwf_sdio_pwr_stctl(struct aic_sdio_dev *sdiodev, uint target);
|
||||
#endif
|
||||
void aicwf_sdio_reg_init(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_sdio_func_init(struct aic_sdio_dev *sdiodev);
|
||||
@@ -153,9 +191,11 @@ void aicwf_sdio_tx_netif_flowctrl(struct rwnx_hw *rwnx_hw, bool state);
|
||||
int aicwf_sdio_flow_ctrl(struct aic_sdio_dev *sdiodev);
|
||||
int aicwf_sdio_flow_ctrl_msg(struct aic_sdio_dev *sdiodev);
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
int aicwf_sdio_recv_pkt(struct aic_sdio_dev *sdiodev, struct rx_buff *rxbbuf, u32 size);
|
||||
int aicwf_sdio_recv_pkt(struct aic_sdio_dev *sdiodev, struct rx_buff *rxbbuf,
|
||||
u32 size);
|
||||
#else
|
||||
int aicwf_sdio_recv_pkt(struct aic_sdio_dev *sdiodev, struct sk_buff *skbbuf, u32 size);
|
||||
int aicwf_sdio_recv_pkt(struct aic_sdio_dev *sdiodev, struct sk_buff *skbbuf,
|
||||
u32 size);
|
||||
#endif
|
||||
int aicwf_sdio_send_pkt(struct aic_sdio_dev *sdiodev, u8 *buf, uint count);
|
||||
void *aicwf_sdio_bus_init(struct aic_sdio_dev *sdiodev);
|
||||
|
||||
@@ -1,21 +1,20 @@
|
||||
#include"aicwf_tcp_ack.h"
|
||||
#include "aicwf_tcp_ack.h"
|
||||
//#include"rwnx_tx.h"
|
||||
//#include "aicwf_tcp_ack.h"
|
||||
#include"rwnx_defs.h"
|
||||
extern int intf_tx(struct rwnx_hw *priv,struct msg_buf *msg);
|
||||
#include "rwnx_defs.h"
|
||||
extern int intf_tx(struct rwnx_hw *priv, struct msg_buf *msg);
|
||||
struct msg_buf *intf_tcp_alloc_msg(struct msg_buf *msg)
|
||||
{
|
||||
//printk("%s \n",__func__);
|
||||
int len=sizeof(struct msg_buf) ;
|
||||
msg = kzalloc(len , /*GFP_KERNEL*/GFP_ATOMIC);
|
||||
if(!msg)
|
||||
int len = sizeof(struct msg_buf);
|
||||
msg = kzalloc(len, /*GFP_KERNEL*/ GFP_ATOMIC);
|
||||
if (!msg)
|
||||
printk("%s: alloc failed \n", __func__);
|
||||
memset(msg,0,len);
|
||||
memset(msg, 0, len);
|
||||
return msg;
|
||||
}
|
||||
|
||||
void intf_tcp_drop_msg(struct rwnx_hw *priv,
|
||||
struct msg_buf *msg)
|
||||
|
||||
void intf_tcp_drop_msg(struct rwnx_hw *priv, struct msg_buf *msg)
|
||||
{
|
||||
//printk("%s \n",__func__);
|
||||
if (msg->skb)
|
||||
@@ -24,7 +23,7 @@ void intf_tcp_drop_msg(struct rwnx_hw *priv,
|
||||
kfree(msg);
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
|
||||
void tcp_ack_timeout(unsigned long data)
|
||||
#else
|
||||
void tcp_ack_timeout(struct timer_list *t)
|
||||
@@ -35,10 +34,10 @@ void tcp_ack_timeout(struct timer_list *t)
|
||||
struct msg_buf *msg;
|
||||
struct tcp_ack_manage *ack_m = NULL;
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
|
||||
ack_info = (struct tcp_ack_info *)data;
|
||||
#else
|
||||
ack_info = container_of(t,struct tcp_ack_info,timer);
|
||||
ack_info = container_of(t, struct tcp_ack_info, timer);
|
||||
#endif
|
||||
|
||||
ack_m = container_of(ack_info, struct tcp_ack_manage,
|
||||
@@ -51,7 +50,7 @@ void tcp_ack_timeout(struct timer_list *t)
|
||||
ack_info->drop_cnt = 0;
|
||||
ack_info->in_send_msg = msg;
|
||||
write_sequnlock_bh(&ack_info->seqlock);
|
||||
intf_tx(ack_m->priv, msg);//send skb
|
||||
intf_tx(ack_m->priv, msg); //send skb
|
||||
//ack_info->in_send_msg = NULL;//add by dwx
|
||||
//write_sequnlock_bh(&ack_info->seqlock);
|
||||
//intf_tx(ack_m->priv, msg);
|
||||
@@ -66,7 +65,7 @@ void tcp_ack_init(struct rwnx_hw *priv)
|
||||
struct tcp_ack_info *ack_info;
|
||||
struct tcp_ack_manage *ack_m = &priv->ack_m;
|
||||
|
||||
printk("%s \n",__func__);
|
||||
printk("%s \n", __func__);
|
||||
memset(ack_m, 0, sizeof(struct tcp_ack_manage));
|
||||
ack_m->priv = priv;
|
||||
spin_lock_init(&ack_m->lock);
|
||||
@@ -81,12 +80,12 @@ void tcp_ack_init(struct rwnx_hw *priv)
|
||||
ack_info->last_time = jiffies;
|
||||
ack_info->timeout = msecs_to_jiffies(ACK_OLD_TIME);
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
|
||||
setup_timer(&ack_info->timer, tcp_ack_timeout,
|
||||
(unsigned long)ack_info);
|
||||
#else
|
||||
timer_setup(&ack_info->timer,tcp_ack_timeout,0);
|
||||
#endif
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
|
||||
setup_timer(&ack_info->timer, tcp_ack_timeout,
|
||||
(unsigned long)ack_info);
|
||||
#else
|
||||
timer_setup(&ack_info->timer, tcp_ack_timeout, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
atomic_set(&ack_m->enable, 1);
|
||||
@@ -99,7 +98,7 @@ void tcp_ack_deinit(struct rwnx_hw *priv)
|
||||
struct tcp_ack_manage *ack_m = &priv->ack_m;
|
||||
struct msg_buf *drop_msg = NULL;
|
||||
|
||||
printk("%s \n",__func__);
|
||||
printk("%s \n", __func__);
|
||||
atomic_set(&ack_m->enable, 0);
|
||||
|
||||
for (i = 0; i < TCP_ACK_NUM; i++) {
|
||||
@@ -112,12 +111,11 @@ void tcp_ack_deinit(struct rwnx_hw *priv)
|
||||
write_sequnlock_bh(&ack_m->ack_info[i].seqlock);
|
||||
|
||||
if (drop_msg)
|
||||
intf_tcp_drop_msg(priv, drop_msg);//drop skb
|
||||
intf_tcp_drop_msg(priv, drop_msg); //drop skb
|
||||
}
|
||||
}
|
||||
|
||||
int tcp_check_quick_ack(unsigned char *buf,
|
||||
struct tcp_ack_msg *msg)
|
||||
int tcp_check_quick_ack(unsigned char *buf, struct tcp_ack_msg *msg)
|
||||
{
|
||||
int ip_hdr_len;
|
||||
unsigned char *temp;
|
||||
@@ -151,14 +149,14 @@ int tcp_check_quick_ack(unsigned char *buf,
|
||||
}
|
||||
|
||||
int is_drop_tcp_ack(struct tcphdr *tcphdr, int tcp_tot_len,
|
||||
unsigned short *win_scale)
|
||||
unsigned short *win_scale)
|
||||
{
|
||||
//printk("%s \n",__func__);
|
||||
int drop = 1;
|
||||
int len = tcphdr->doff * 4;
|
||||
unsigned char *ptr;
|
||||
|
||||
if(tcp_tot_len > len) {
|
||||
if (tcp_tot_len > len) {
|
||||
drop = 0;
|
||||
} else {
|
||||
len -= sizeof(struct tcphdr);
|
||||
@@ -188,7 +186,7 @@ int is_drop_tcp_ack(struct tcphdr *tcphdr, int tcp_tot_len,
|
||||
case TCPOPT_WINDOW:
|
||||
if (*ptr < 15)
|
||||
*win_scale = (1 << (*ptr));
|
||||
printk("%d\n",*win_scale);
|
||||
//printk("%d\n",*win_scale);
|
||||
break;
|
||||
default:
|
||||
drop = 2;
|
||||
@@ -203,15 +201,13 @@ int is_drop_tcp_ack(struct tcphdr *tcphdr, int tcp_tot_len,
|
||||
return drop;
|
||||
}
|
||||
|
||||
|
||||
/* flag:0 for not tcp ack
|
||||
* 1 for ack which can be drop
|
||||
* 2 for other ack whith more info
|
||||
*/
|
||||
|
||||
int tcp_check_ack(unsigned char *buf,
|
||||
struct tcp_ack_msg *msg,
|
||||
unsigned short *win_scale)
|
||||
int tcp_check_ack(unsigned char *buf, struct tcp_ack_msg *msg,
|
||||
unsigned short *win_scale)
|
||||
{
|
||||
int ret;
|
||||
int ip_hdr_len;
|
||||
@@ -221,7 +217,7 @@ int tcp_check_ack(unsigned char *buf,
|
||||
struct iphdr *iphdr;
|
||||
struct tcphdr *tcphdr;
|
||||
|
||||
ethhdr =(struct ethhdr *)buf;
|
||||
ethhdr = (struct ethhdr *)buf;
|
||||
if (ethhdr->h_proto != htons(ETH_P_IP))
|
||||
return 0;
|
||||
|
||||
@@ -236,7 +232,7 @@ int tcp_check_ack(unsigned char *buf,
|
||||
if (!(temp[13] & 0x10))
|
||||
return 0;
|
||||
|
||||
tcp_tot_len = ntohs(iphdr->tot_len) - ip_hdr_len;// tcp total len
|
||||
tcp_tot_len = ntohs(iphdr->tot_len) - ip_hdr_len; // tcp total len
|
||||
ret = is_drop_tcp_ack(tcphdr, tcp_tot_len, win_scale);
|
||||
//printk("is drop:%d \n",ret);
|
||||
|
||||
@@ -248,13 +244,12 @@ int tcp_check_ack(unsigned char *buf,
|
||||
msg->seq = ntohl(tcphdr->ack_seq);
|
||||
msg->win = ntohs(tcphdr->window);
|
||||
}
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* return val: -1 for not match, others for match */
|
||||
int tcp_ack_match(struct tcp_ack_manage *ack_m,
|
||||
struct tcp_ack_msg *ack_msg)
|
||||
int tcp_ack_match(struct tcp_ack_manage *ack_m, struct tcp_ack_msg *ack_msg)
|
||||
{
|
||||
int i, ret = -1;
|
||||
unsigned start;
|
||||
@@ -268,19 +263,17 @@ int tcp_ack_match(struct tcp_ack_manage *ack_m,
|
||||
ret = -1;
|
||||
|
||||
ack = &ack_info->ack_msg;
|
||||
if (ack_info->busy &&
|
||||
ack->dest == ack_msg->dest &&
|
||||
if (ack_info->busy && ack->dest == ack_msg->dest &&
|
||||
ack->source == ack_msg->source &&
|
||||
ack->saddr == ack_msg->saddr &&
|
||||
ack->daddr == ack_msg->daddr)
|
||||
ret = i;
|
||||
} while(read_seqretry(&ack_info->seqlock, start));
|
||||
} while (read_seqretry(&ack_info->seqlock, start));
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
void tcp_ack_update(struct tcp_ack_manage *ack_m)
|
||||
{
|
||||
int i;
|
||||
@@ -294,7 +287,7 @@ void tcp_ack_update(struct tcp_ack_manage *ack_m)
|
||||
write_seqlock_bh(&ack_info->seqlock);
|
||||
if (ack_info->busy &&
|
||||
time_after(jiffies, ack_info->last_time +
|
||||
ack_info->timeout)) {
|
||||
ack_info->timeout)) {
|
||||
ack_m->free_index = i;
|
||||
ack_m->max_num--;
|
||||
ack_info->busy = 0;
|
||||
@@ -336,20 +329,17 @@ int tcp_ack_alloc_index(struct tcp_ack_manage *ack_m)
|
||||
ack_m->max_num++;
|
||||
ret = i;
|
||||
}
|
||||
} while(read_seqretry(&ack_info->seqlock, start));
|
||||
} while (read_seqretry(&ack_info->seqlock, start));
|
||||
}
|
||||
spin_unlock_bh(&ack_m->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/* return val: 0 for not handle tx, 1 for handle tx */
|
||||
int tcp_ack_handle(struct msg_buf *new_msgbuf,
|
||||
struct tcp_ack_manage *ack_m,
|
||||
struct tcp_ack_info *ack_info,
|
||||
struct tcp_ack_msg *ack_msg,
|
||||
int type)
|
||||
int tcp_ack_handle(struct msg_buf *new_msgbuf, struct tcp_ack_manage *ack_m,
|
||||
struct tcp_ack_info *ack_info, struct tcp_ack_msg *ack_msg,
|
||||
int type)
|
||||
{
|
||||
int quick_ack = 0;
|
||||
struct tcp_ack_msg *ack;
|
||||
@@ -366,8 +356,7 @@ int tcp_ack_handle(struct msg_buf *new_msgbuf,
|
||||
if (U32_BEFORE(ack->seq, ack_msg->seq)) {
|
||||
ack->seq = ack_msg->seq;
|
||||
if (ack_info->psh_flag &&
|
||||
!U32_BEFORE(ack_msg->seq,
|
||||
ack_info->psh_seq)) {
|
||||
!U32_BEFORE(ack_msg->seq, ack_info->psh_seq)) {
|
||||
ack_info->psh_flag = 0;
|
||||
}
|
||||
|
||||
@@ -376,15 +365,15 @@ int tcp_ack_handle(struct msg_buf *new_msgbuf,
|
||||
drop_msg = ack_info->msgbuf;
|
||||
ack_info->msgbuf = NULL;
|
||||
del_timer(&ack_info->timer);
|
||||
}else{
|
||||
} else {
|
||||
//printk("msgbuf is NULL \n");
|
||||
}
|
||||
|
||||
ack_info->in_send_msg = NULL;
|
||||
ack_info->drop_cnt = atomic_read(&ack_m->max_drop_cnt);
|
||||
} else {
|
||||
printk("%s before abnormal ack: %d, %d\n",
|
||||
__func__, ack->seq, ack_msg->seq);
|
||||
printk("%s before abnormal ack: %d, %d\n", __func__,
|
||||
ack->seq, ack_msg->seq);
|
||||
drop_msg = new_msgbuf;
|
||||
ret = 1;
|
||||
}
|
||||
@@ -418,8 +407,8 @@ int tcp_ack_handle(struct msg_buf *new_msgbuf,
|
||||
(jiffies + msecs_to_jiffies(5)));
|
||||
}
|
||||
} else {
|
||||
printk("%s before ack: %d, %d\n",
|
||||
__func__, ack->seq, ack_msg->seq);
|
||||
printk("%s before ack: %d, %d\n", __func__, ack->seq,
|
||||
ack_msg->seq);
|
||||
drop_msg = new_msgbuf;
|
||||
ret = 1;
|
||||
}
|
||||
@@ -427,29 +416,27 @@ int tcp_ack_handle(struct msg_buf *new_msgbuf,
|
||||
write_sequnlock_bh(&ack_info->seqlock);
|
||||
|
||||
if (drop_msg)
|
||||
intf_tcp_drop_msg(ack_m->priv, drop_msg);// drop skb
|
||||
intf_tcp_drop_msg(ack_m->priv, drop_msg); // drop skb
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int tcp_ack_handle_new(struct msg_buf *new_msgbuf,
|
||||
struct tcp_ack_manage *ack_m,
|
||||
struct tcp_ack_info *ack_info,
|
||||
struct tcp_ack_msg *ack_msg,
|
||||
int type)
|
||||
int tcp_ack_handle_new(struct msg_buf *new_msgbuf, struct tcp_ack_manage *ack_m,
|
||||
struct tcp_ack_info *ack_info,
|
||||
struct tcp_ack_msg *ack_msg, int type)
|
||||
{
|
||||
int quick_ack = 0;
|
||||
struct tcp_ack_msg *ack;
|
||||
int ret = 0;
|
||||
struct msg_buf *drop_msg = NULL;
|
||||
struct msg_buf * send_msg = NULL;
|
||||
//struct msg_buf * send_msg = NULL;
|
||||
//printk("",);
|
||||
write_seqlock_bh(&ack_info->seqlock);
|
||||
|
||||
ack_info->last_time = jiffies;
|
||||
ack = &ack_info->ack_msg;
|
||||
ack_info->last_time = jiffies;
|
||||
ack = &ack_info->ack_msg;
|
||||
|
||||
if(U32_BEFORE(ack->seq, ack_msg->seq)){
|
||||
if (U32_BEFORE(ack->seq, ack_msg->seq)) {
|
||||
if (ack_info->msgbuf) {
|
||||
drop_msg = ack_info->msgbuf;
|
||||
ack_info->msgbuf = NULL;
|
||||
@@ -466,25 +453,25 @@ int tcp_ack_handle_new(struct msg_buf *new_msgbuf,
|
||||
|
||||
ack->seq = ack_msg->seq;
|
||||
|
||||
if(quick_ack || (!ack_info->in_send_msg &&
|
||||
if (quick_ack || (!ack_info->in_send_msg &&
|
||||
(ack_info->drop_cnt >=
|
||||
atomic_read(&ack_m->max_drop_cnt)))){
|
||||
atomic_read(&ack_m->max_drop_cnt)))) {
|
||||
ack_info->drop_cnt = 0;
|
||||
send_msg = new_msgbuf;
|
||||
ack_info->in_send_msg = send_msg;
|
||||
//send_msg = new_msgbuf;
|
||||
ack_info->in_send_msg = new_msgbuf;
|
||||
del_timer(&ack_info->timer);
|
||||
}else{
|
||||
} else {
|
||||
ret = 1;
|
||||
ack_info->msgbuf = new_msgbuf;
|
||||
if (!timer_pending(&ack_info->timer))
|
||||
mod_timer(&ack_info->timer,
|
||||
(jiffies + msecs_to_jiffies(5)));
|
||||
}
|
||||
|
||||
|
||||
//ret = 1;
|
||||
}else {
|
||||
printk("%s before ack: %d, %d\n",
|
||||
__func__, ack->seq, ack_msg->seq);
|
||||
} else {
|
||||
printk("%s before ack: %d, %d\n", __func__, ack->seq,
|
||||
ack_msg->seq);
|
||||
drop_msg = new_msgbuf;
|
||||
ret = 1;
|
||||
}
|
||||
@@ -495,23 +482,21 @@ int tcp_ack_handle_new(struct msg_buf *new_msgbuf,
|
||||
}*/
|
||||
|
||||
//ack_info->in_send_msg=NULL;
|
||||
|
||||
|
||||
write_sequnlock_bh(&ack_info->seqlock);
|
||||
|
||||
/*if(send_msg){
|
||||
/*if(send_msg){
|
||||
intf_tx(ack_m->priv,send_msg);
|
||||
//ack_info->in_send_msg=NULL;
|
||||
}*/
|
||||
|
||||
if (drop_msg)
|
||||
intf_tcp_drop_msg(ack_m->priv, drop_msg);// drop skb
|
||||
intf_tcp_drop_msg(ack_m->priv, drop_msg); // drop skb
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
void filter_rx_tcp_ack(struct rwnx_hw *priv,
|
||||
unsigned char *buf, unsigned plen)
|
||||
void filter_rx_tcp_ack(struct rwnx_hw *priv, unsigned char *buf, unsigned plen)
|
||||
{
|
||||
int index;
|
||||
struct tcp_ack_msg ack_msg;
|
||||
@@ -521,8 +506,7 @@ void filter_rx_tcp_ack(struct rwnx_hw *priv,
|
||||
if (!atomic_read(&ack_m->enable))
|
||||
return;
|
||||
|
||||
if ((plen > MAX_TCP_ACK) ||
|
||||
!tcp_check_quick_ack(buf, &ack_msg))
|
||||
if ((plen > MAX_TCP_ACK) || !tcp_check_quick_ack(buf, &ack_msg))
|
||||
return;
|
||||
|
||||
index = tcp_ack_match(ack_m, &ack_msg);
|
||||
@@ -536,9 +520,8 @@ void filter_rx_tcp_ack(struct rwnx_hw *priv,
|
||||
}
|
||||
|
||||
/* return val: 0 for not filter, 1 for filter */
|
||||
int filter_send_tcp_ack(struct rwnx_hw *priv,
|
||||
struct msg_buf *msgbuf,
|
||||
unsigned char *buf, unsigned int plen)
|
||||
int filter_send_tcp_ack(struct rwnx_hw *priv, struct msg_buf *msgbuf,
|
||||
unsigned char *buf, unsigned int plen)
|
||||
{
|
||||
//printk("%s \n",__func__);
|
||||
int ret = 0;
|
||||
@@ -550,9 +533,6 @@ int filter_send_tcp_ack(struct rwnx_hw *priv,
|
||||
struct tcp_ack_info *ack_info;
|
||||
struct tcp_ack_manage *ack_m = &priv->ack_m;
|
||||
|
||||
if (plen > MAX_TCP_ACK)
|
||||
return 0;
|
||||
|
||||
tcp_ack_update(ack_m);
|
||||
drop = tcp_check_ack(buf, &ack_msg, &win_scale);
|
||||
//printk("drop:%d win_scale:%d",drop,win_scale);
|
||||
@@ -562,8 +542,7 @@ int filter_send_tcp_ack(struct rwnx_hw *priv,
|
||||
index = tcp_ack_match(ack_m, &ack_msg);
|
||||
if (index >= 0) {
|
||||
ack_info = ack_m->ack_info + index;
|
||||
if ((0 != win_scale) &&
|
||||
(ack_info->win_scale != win_scale)) {
|
||||
if ((0 != win_scale) && (ack_info->win_scale != win_scale)) {
|
||||
write_seqlock_bh(&ack_info->seqlock);
|
||||
ack_info->win_scale = win_scale;
|
||||
write_sequnlock_bh(&ack_info->seqlock);
|
||||
@@ -571,13 +550,14 @@ int filter_send_tcp_ack(struct rwnx_hw *priv,
|
||||
|
||||
if (drop > 0 && atomic_read(&ack_m->enable)) {
|
||||
win = ack_info->win_scale * ack_msg.win;
|
||||
if ((win_scale!=0) && (win < (ack_m->ack_winsize * SIZE_KB)))
|
||||
{
|
||||
if ((win_scale != 0) &&
|
||||
(win < (ack_m->ack_winsize * SIZE_KB))) {
|
||||
drop = 2;
|
||||
printk("%d %d %d",win_scale,win,(ack_m->ack_winsize * SIZE_KB));
|
||||
printk("%d %d %d", win_scale, win,
|
||||
(ack_m->ack_winsize * SIZE_KB));
|
||||
}
|
||||
ret = tcp_ack_handle_new(msgbuf, ack_m, ack_info,
|
||||
&ack_msg, drop);
|
||||
&ack_msg, drop);
|
||||
}
|
||||
|
||||
goto out;
|
||||
@@ -593,7 +573,7 @@ int filter_send_tcp_ack(struct rwnx_hw *priv,
|
||||
atomic_read(&ack_m->max_drop_cnt);
|
||||
ack_m->ack_info[index].win_scale =
|
||||
(win_scale != 0) ? win_scale : 1;
|
||||
|
||||
|
||||
//ack_m->ack_info[index].msgbuf = NULL;
|
||||
//ack_m->ack_info[index].in_send_msg = NULL;
|
||||
ack = &ack_m->ack_info[index].ack_msg;
|
||||
@@ -609,8 +589,7 @@ out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void move_tcpack_msg(struct rwnx_hw *priv,
|
||||
struct msg_buf *msg)
|
||||
void move_tcpack_msg(struct rwnx_hw *priv, struct msg_buf *msg)
|
||||
{
|
||||
struct tcp_ack_info *ack_info;
|
||||
struct tcp_ack_manage *ack_m = &priv->ack_m;
|
||||
@@ -630,4 +609,3 @@ void move_tcpack_msg(struct rwnx_hw *priv,
|
||||
write_sequnlock_bh(&ack_info->seqlock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -9,44 +9,23 @@
|
||||
#include <net/tcp.h>
|
||||
#include <linux/timer.h>
|
||||
|
||||
#define TCP_ACK_NUM 32
|
||||
#define TCP_ACK_EXIT_VAL 0x800
|
||||
#define TCP_ACK_DROP_CNT 10
|
||||
|
||||
#define TCP_ACK_NUM 32
|
||||
#define TCP_ACK_EXIT_VAL 0x800
|
||||
#define TCP_ACK_DROP_CNT 10
|
||||
|
||||
#define ACK_OLD_TIME 4000
|
||||
#define U32_BEFORE(a, b) ((__s32)((__u32)a - (__u32)b) <= 0)
|
||||
#define ACK_OLD_TIME 4000
|
||||
#define U32_BEFORE(a, b) ((__s32)((__u32)a - (__u32)b) <= 0)
|
||||
|
||||
#define MAX_TCP_ACK 200
|
||||
/*min window size in KB, it's 256KB*/
|
||||
#define MIN_WIN 256
|
||||
#define SIZE_KB 1024
|
||||
|
||||
|
||||
struct msg_buf {
|
||||
//struct list_head list;
|
||||
struct sk_buff *skb;
|
||||
struct rwnx_vif *rwnx_vif;
|
||||
|
||||
/* data just tx cmd use,not include the head */
|
||||
/*void *data;
|
||||
void *tran_data;
|
||||
unsigned long pcie_addr;
|
||||
u8 type;
|
||||
u8 mode;
|
||||
u16 len;
|
||||
unsigned long timeout;*/
|
||||
|
||||
/*unsigned int fifo_id;
|
||||
struct sprdwl_msg_list *msglist;*/
|
||||
|
||||
/*unsigned char buffer_type;
|
||||
struct sprdwl_xmit_msg_list *xmit_msg_list;
|
||||
unsigned char msg_type;
|
||||
|
||||
unsigned long last_time;
|
||||
u8 ctxt_id;*/
|
||||
|
||||
};
|
||||
|
||||
struct tcp_ack_msg {
|
||||
@@ -58,7 +37,6 @@ struct tcp_ack_msg {
|
||||
u16 win;
|
||||
};
|
||||
|
||||
|
||||
struct tcp_ack_info {
|
||||
int ack_info_num;
|
||||
int busy;
|
||||
@@ -98,14 +76,15 @@ void tcp_ack_init(struct rwnx_hw *priv);
|
||||
|
||||
void tcp_ack_deinit(struct rwnx_hw *priv);
|
||||
|
||||
|
||||
int is_drop_tcp_ack(struct tcphdr *tcphdr, int tcp_tot_len, unsigned short *win_scale);
|
||||
int is_drop_tcp_ack(struct tcphdr *tcphdr, int tcp_tot_len,
|
||||
unsigned short *win_scale);
|
||||
|
||||
int is_tcp_ack(struct sk_buff *skb, unsigned short *win_scale);
|
||||
|
||||
int filter_send_tcp_ack(struct rwnx_hw *priv, struct msg_buf *msgbuf,unsigned char *buf, unsigned int plen);
|
||||
int filter_send_tcp_ack(struct rwnx_hw *priv, struct msg_buf *msgbuf,
|
||||
unsigned char *buf, unsigned int plen);
|
||||
|
||||
void filter_rx_tcp_ack(struct rwnx_hw *priv,unsigned char *buf, unsigned plen);
|
||||
void filter_rx_tcp_ack(struct rwnx_hw *priv, unsigned char *buf, unsigned plen);
|
||||
|
||||
void move_tcpack_msg(struct rwnx_hw *priv, struct msg_buf * msg);
|
||||
void move_tcpack_msg(struct rwnx_hw *priv, struct msg_buf *msg);
|
||||
#endif
|
||||
|
||||
@@ -31,11 +31,13 @@
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
void aicwf_rxframe_queue_init_2(struct rx_frame_queue *pq, int max_len)
|
||||
{
|
||||
//int prio;
|
||||
//int prio;
|
||||
|
||||
memset(pq, 0, offsetof(struct rx_frame_queue, queuelist) + (sizeof(struct list_head)));
|
||||
pq->qmax = (u16)max_len;
|
||||
INIT_LIST_HEAD(&pq->queuelist);
|
||||
memset(pq, 0,
|
||||
offsetof(struct rx_frame_queue, queuelist) +
|
||||
(sizeof(struct list_head)));
|
||||
pq->qmax = (u16)max_len;
|
||||
INIT_LIST_HEAD(&pq->queuelist);
|
||||
#if 0
|
||||
memset(pq, 0, offsetof(struct rx_frame_queue, queuelist) + (sizeof(struct list_head) * num_prio));
|
||||
pq->num_prio = (u16)num_prio;
|
||||
@@ -48,27 +50,26 @@ void aicwf_rxframe_queue_init_2(struct rx_frame_queue *pq, int max_len)
|
||||
}
|
||||
|
||||
//extern struct aic_sdio_dev *g_sdiodev;
|
||||
void rxbuff_queue_flush(struct aicwf_rx_priv* rx_priv)
|
||||
void rxbuff_queue_flush(struct aicwf_rx_priv *rx_priv)
|
||||
{
|
||||
|
||||
//int prio;
|
||||
//int prio;
|
||||
struct rx_frame_queue *pq = &rx_priv->rxq;
|
||||
struct list_head *pos;
|
||||
struct list_head *n;
|
||||
struct list_head *head;
|
||||
struct rx_buff *tempbuf = NULL;
|
||||
struct list_head *pos;
|
||||
struct list_head *n;
|
||||
struct list_head *head;
|
||||
struct rx_buff *tempbuf = NULL;
|
||||
|
||||
head = &pq->queuelist;
|
||||
list_for_each_safe(pos, n, head) {
|
||||
tempbuf = list_entry(pos, struct rx_buff, queue);
|
||||
list_del_init(&tempbuf->queue);
|
||||
head = &pq->queuelist;
|
||||
list_for_each_safe (pos, n, head) {
|
||||
tempbuf = list_entry(pos, struct rx_buff, queue);
|
||||
list_del_init(&tempbuf->queue);
|
||||
#if 0
|
||||
rxbuff_free(tempbuf);
|
||||
#else
|
||||
aicwf_prealloc_rxbuff_free(tempbuf, &rx_priv->rxbuff_lock);
|
||||
aicwf_prealloc_rxbuff_free(tempbuf, &rx_priv->rxbuff_lock);
|
||||
#endif
|
||||
pq->qcnt--;
|
||||
}
|
||||
pq->qcnt--;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -92,32 +93,43 @@ int aicwf_bus_init(uint bus_hdrlen, struct device *dev)
|
||||
|
||||
init_completion(&bus_if->bustx_trgg);
|
||||
init_completion(&bus_if->busrx_trgg);
|
||||
//new oob feature
|
||||
init_completion(&bus_if->busirq_trgg);
|
||||
//new oob feature
|
||||
init_completion(&bus_if->busirq_trgg);
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
spin_lock_init(&bus_if->bus_priv.sdio->wslock);//AIDEN test
|
||||
bus_if->bustx_thread = kthread_run(sdio_bustx_thread, (void *)bus_if, "aicwf_bustx_thread");
|
||||
bus_if->busrx_thread = kthread_run(sdio_busrx_thread, (void *)bus_if->bus_priv.sdio->rx_priv, "aicwf_busrx_thread");
|
||||
//new oob feature
|
||||
spin_lock_init(&bus_if->bus_priv.sdio->wslock); //AIDEN test
|
||||
bus_if->bustx_thread = kthread_run(sdio_bustx_thread, (void *)bus_if,
|
||||
"aicwf_bustx_thread");
|
||||
bus_if->busrx_thread =
|
||||
kthread_run(sdio_busrx_thread,
|
||||
(void *)bus_if->bus_priv.sdio->rx_priv,
|
||||
"aicwf_busrx_thread");
|
||||
//new oob feature
|
||||
#ifdef CONFIG_OOB
|
||||
if(bus_if->bus_priv.sdio->oob_enable){
|
||||
bus_if->busirq_thread = kthread_run(sdio_busirq_thread, (void *)bus_if->bus_priv.sdio->rx_priv, "aicwf_busirq_thread");
|
||||
}
|
||||
if (bus_if->bus_priv.sdio->oob_enable) {
|
||||
bus_if->busirq_thread =
|
||||
kthread_run(sdio_busirq_thread,
|
||||
(void *)bus_if->bus_priv.sdio->rx_priv,
|
||||
"aicwf_busirq_thread");
|
||||
}
|
||||
#endif //CONFIG_OOB
|
||||
#endif
|
||||
#ifdef AICWF_USB_SUPPORT
|
||||
bus_if->bustx_thread = kthread_run(usb_bustx_thread, (void *)bus_if, "aicwf_bustx_thread");
|
||||
bus_if->busrx_thread = kthread_run(usb_busrx_thread, (void *)bus_if->bus_priv.usb->rx_priv, "aicwf_busrx_thread");
|
||||
bus_if->bustx_thread = kthread_run(usb_bustx_thread, (void *)bus_if,
|
||||
"aicwf_bustx_thread");
|
||||
bus_if->busrx_thread =
|
||||
kthread_run(usb_busrx_thread,
|
||||
(void *)bus_if->bus_priv.usb->rx_priv,
|
||||
"aicwf_busrx_thread");
|
||||
#endif
|
||||
|
||||
if (IS_ERR(bus_if->bustx_thread)) {
|
||||
bus_if->bustx_thread = NULL;
|
||||
bus_if->bustx_thread = NULL;
|
||||
txrx_err("aicwf_bustx_thread run fail\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (IS_ERR(bus_if->busrx_thread)) {
|
||||
bus_if->busrx_thread = NULL;
|
||||
bus_if->busrx_thread = NULL;
|
||||
txrx_err("aicwf_bustx_thread run fail\n");
|
||||
goto fail;
|
||||
}
|
||||
@@ -205,8 +217,9 @@ struct aicwf_tx_priv *aicwf_tx_init(void *arg)
|
||||
#endif
|
||||
|
||||
atomic_set(&tx_priv->aggr_count, 0);
|
||||
#ifdef CONFIG_RESV_MEM_SUPPORT
|
||||
tx_priv->aggr_buf = aicbsp_resv_mem_alloc_skb(MAX_AGGR_TXPKT_LEN, AIC_RESV_MEM_TXDATA);
|
||||
#ifdef CONFIG_RESV_MEM_SUPPORT
|
||||
tx_priv->aggr_buf = aicbsp_resv_mem_alloc_skb(MAX_AGGR_TXPKT_LEN,
|
||||
AIC_RESV_MEM_TXDATA);
|
||||
#else
|
||||
tx_priv->aggr_buf = dev_alloc_skb(MAX_AGGR_TXPKT_LEN);
|
||||
#endif
|
||||
@@ -218,40 +231,49 @@ struct aicwf_tx_priv *aicwf_tx_init(void *arg)
|
||||
tx_priv->head = tx_priv->aggr_buf->data;
|
||||
tx_priv->tail = tx_priv->aggr_buf->data;
|
||||
|
||||
#ifdef CONFIG_SDIO_ADMA
|
||||
tx_priv->aggr_segcnt = 0;
|
||||
tx_priv->len = 0;
|
||||
#endif
|
||||
|
||||
return tx_priv;
|
||||
}
|
||||
|
||||
void aicwf_tx_deinit(struct aicwf_tx_priv *tx_priv)
|
||||
{
|
||||
if (tx_priv && tx_priv->aggr_buf) {
|
||||
#ifdef CONFIG_RESV_MEM_SUPPORT
|
||||
aicbsp_resv_mem_kfree_skb(tx_priv->aggr_buf, AIC_RESV_MEM_TXDATA);
|
||||
#ifdef CONFIG_RESV_MEM_SUPPORT
|
||||
aicbsp_resv_mem_kfree_skb(tx_priv->aggr_buf,
|
||||
AIC_RESV_MEM_TXDATA);
|
||||
#else
|
||||
dev_kfree_skb(tx_priv->aggr_buf);
|
||||
#endif
|
||||
kfree(tx_priv);
|
||||
}
|
||||
#ifdef CONFIG_SDIO_ADMA
|
||||
aicwf_sdio_aggrbuf_reset(tx_priv);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
static bool aicwf_another_ptk_1(struct rx_buff *buffer)
|
||||
{
|
||||
u8 *read = buffer->read;
|
||||
u16 aggr_len = 0;
|
||||
u8 *read = buffer->read;
|
||||
u16 aggr_len = 0;
|
||||
|
||||
BUG_ON((read - buffer->start)%4 != 0);
|
||||
BUG_ON((read - buffer->start) % 4 != 0);
|
||||
|
||||
if(read == NULL || read >= buffer->end) {
|
||||
return false;
|
||||
}
|
||||
if (read == NULL || read >= buffer->end) {
|
||||
return false;
|
||||
}
|
||||
|
||||
aggr_len = (*read | (*(read + 1) << 8));
|
||||
if(aggr_len == 0) {
|
||||
return false;
|
||||
}
|
||||
aggr_len = (*read | (*(read + 1) << 8));
|
||||
if (aggr_len == 0) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
return true;
|
||||
}
|
||||
#else
|
||||
static bool aicwf_another_ptk(struct sk_buff *skb)
|
||||
@@ -286,7 +308,7 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
u16 aggr_len = 0, adjust_len = 0;
|
||||
u8 *data = NULL;
|
||||
u8_l *msg = NULL;
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
struct rx_buff *buffer = NULL;
|
||||
|
||||
while (1) {
|
||||
@@ -305,50 +327,71 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
data = buffer->read;
|
||||
pkt_len = (*data | (*(data + 1) << 8));
|
||||
|
||||
if ((data[2] & SDIO_TYPE_CFG) != SDIO_TYPE_CFG) { // type : data
|
||||
if ((data[2] & SDIO_TYPE_CFG) !=
|
||||
SDIO_TYPE_CFG) { // type : data
|
||||
aggr_len = pkt_len + RX_HWHRD_LEN;
|
||||
|
||||
if (aggr_len & (RX_ALIGNMENT - 1))
|
||||
adjust_len = roundup(aggr_len, RX_ALIGNMENT);
|
||||
adjust_len =
|
||||
roundup(aggr_len, RX_ALIGNMENT);
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
skb_inblock = __dev_alloc_skb(aggr_len + CCMP_OR_WEP_INFO, GFP_KERNEL);
|
||||
skb_inblock = __dev_alloc_skb(
|
||||
aggr_len + CCMP_OR_WEP_INFO,
|
||||
GFP_KERNEL);
|
||||
if (skb_inblock == NULL) {
|
||||
txrx_err("no more space! skip\n");
|
||||
buffer->read = buffer->read + adjust_len;
|
||||
buffer->read =
|
||||
buffer->read + adjust_len;
|
||||
continue;
|
||||
}
|
||||
|
||||
skb_put(skb_inblock, aggr_len);
|
||||
memcpy(skb_inblock->data, data, aggr_len);
|
||||
rwnx_rxdataind_aicwf(rx_priv->sdiodev->rwnx_hw, skb_inblock, (void *)rx_priv);
|
||||
rwnx_rxdataind_aicwf(rx_priv->sdiodev->rwnx_hw,
|
||||
skb_inblock,
|
||||
(void *)rx_priv);
|
||||
buffer->read = buffer->read + adjust_len;
|
||||
} else {
|
||||
// type : config
|
||||
aggr_len = pkt_len;
|
||||
|
||||
if (aggr_len & (RX_ALIGNMENT - 1))
|
||||
adjust_len = roundup(aggr_len, RX_ALIGNMENT);
|
||||
adjust_len =
|
||||
roundup(aggr_len, RX_ALIGNMENT);
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
msg = kmalloc(aggr_len+4, GFP_KERNEL);
|
||||
msg = kmalloc(aggr_len + 4, GFP_KERNEL);
|
||||
if (msg == NULL) {
|
||||
txrx_err("no more space for msg!\n");
|
||||
aicwf_prealloc_rxbuff_free(buffer, &rx_priv->rxbuff_lock);
|
||||
aicwf_prealloc_rxbuff_free(
|
||||
buffer, &rx_priv->rxbuff_lock);
|
||||
return -EBADE;
|
||||
}
|
||||
|
||||
memcpy(msg, data, aggr_len + 4);
|
||||
if (((*(msg + 2) & 0x7f) == SDIO_TYPE_CFG_CMD_RSP) && (rx_priv->sdiodev->bus_if->state != BUS_DOWN_ST))
|
||||
rwnx_rx_handle_msg(rx_priv->sdiodev->rwnx_hw, (struct ipc_e2a_msg *)(msg + 4));
|
||||
if (((*(msg + 2) & 0x7f) ==
|
||||
SDIO_TYPE_CFG_CMD_RSP) &&
|
||||
(rx_priv->sdiodev->bus_if->state !=
|
||||
BUS_DOWN_ST))
|
||||
rwnx_rx_handle_msg(
|
||||
rx_priv->sdiodev->rwnx_hw,
|
||||
(struct ipc_e2a_msg *)(msg +
|
||||
4));
|
||||
|
||||
if ((*(msg + 2) & 0x7f) == SDIO_TYPE_CFG_DATA_CFM)
|
||||
aicwf_sdio_host_tx_cfm_handler(&(rx_priv->sdiodev->rwnx_hw->sdio_env), (u32 *)(msg + 4));
|
||||
if ((*(msg + 2) & 0x7f) ==
|
||||
SDIO_TYPE_CFG_DATA_CFM)
|
||||
aicwf_sdio_host_tx_cfm_handler(
|
||||
&(rx_priv->sdiodev->rwnx_hw
|
||||
->sdio_env),
|
||||
(u32 *)(msg + 4));
|
||||
|
||||
if ((*(msg + 2) & 0x7f) == SDIO_TYPE_CFG_PRINT)
|
||||
rwnx_rx_handle_print(rx_priv->sdiodev->rwnx_hw, msg + 4, aggr_len);
|
||||
rwnx_rx_handle_print(
|
||||
rx_priv->sdiodev->rwnx_hw,
|
||||
msg + 4, aggr_len);
|
||||
|
||||
buffer->read = buffer->read + (adjust_len + 4);
|
||||
kfree(msg);
|
||||
@@ -360,7 +403,7 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
atomic_dec(&rx_priv->rx_cnt);
|
||||
}
|
||||
|
||||
#else
|
||||
#else
|
||||
|
||||
while (1) {
|
||||
spin_lock_irqsave(&rx_priv->rxqlock, flags);
|
||||
@@ -378,15 +421,19 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
data = skb->data;
|
||||
pkt_len = (*skb->data | (*(skb->data + 1) << 8));
|
||||
|
||||
if ((skb->data[2] & SDIO_TYPE_CFG) != SDIO_TYPE_CFG) { // type : data
|
||||
if ((skb->data[2] & SDIO_TYPE_CFG) !=
|
||||
SDIO_TYPE_CFG) { // type : data
|
||||
aggr_len = pkt_len + RX_HWHRD_LEN;
|
||||
|
||||
if (aggr_len & (RX_ALIGNMENT - 1))
|
||||
adjust_len = roundup(aggr_len, RX_ALIGNMENT);
|
||||
adjust_len =
|
||||
roundup(aggr_len, RX_ALIGNMENT);
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
skb_inblock = __dev_alloc_skb(aggr_len + CCMP_OR_WEP_INFO, GFP_KERNEL);
|
||||
skb_inblock = __dev_alloc_skb(
|
||||
aggr_len + CCMP_OR_WEP_INFO,
|
||||
GFP_KERNEL);
|
||||
if (skb_inblock == NULL) {
|
||||
txrx_err("no more space! skip\n");
|
||||
skb_pull(skb, adjust_len);
|
||||
@@ -395,18 +442,21 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
|
||||
skb_put(skb_inblock, aggr_len);
|
||||
memcpy(skb_inblock->data, data, aggr_len);
|
||||
rwnx_rxdataind_aicwf(rx_priv->sdiodev->rwnx_hw, skb_inblock, (void *)rx_priv);
|
||||
rwnx_rxdataind_aicwf(rx_priv->sdiodev->rwnx_hw,
|
||||
skb_inblock,
|
||||
(void *)rx_priv);
|
||||
skb_pull(skb, adjust_len);
|
||||
} else {
|
||||
// type : config
|
||||
aggr_len = pkt_len;
|
||||
|
||||
if (aggr_len & (RX_ALIGNMENT - 1))
|
||||
adjust_len = roundup(aggr_len, RX_ALIGNMENT);
|
||||
adjust_len =
|
||||
roundup(aggr_len, RX_ALIGNMENT);
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
msg = kmalloc(aggr_len+4, GFP_KERNEL);
|
||||
msg = kmalloc(aggr_len + 4, GFP_KERNEL);
|
||||
if (msg == NULL) {
|
||||
txrx_err("no more space for msg!\n");
|
||||
aicwf_dev_skb_free(skb);
|
||||
@@ -414,16 +464,28 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
}
|
||||
|
||||
memcpy(msg, data, aggr_len + 4);
|
||||
if (((*(msg + 2) & 0x7f) == SDIO_TYPE_CFG_CMD_RSP) && (rx_priv->sdiodev->bus_if->state != BUS_DOWN_ST))
|
||||
rwnx_rx_handle_msg(rx_priv->sdiodev->rwnx_hw, (struct ipc_e2a_msg *)(msg + 4));
|
||||
if (((*(msg + 2) & 0x7f) ==
|
||||
SDIO_TYPE_CFG_CMD_RSP) &&
|
||||
(rx_priv->sdiodev->bus_if->state !=
|
||||
BUS_DOWN_ST))
|
||||
rwnx_rx_handle_msg(
|
||||
rx_priv->sdiodev->rwnx_hw,
|
||||
(struct ipc_e2a_msg *)(msg +
|
||||
4));
|
||||
|
||||
if ((*(msg + 2) & 0x7f) == SDIO_TYPE_CFG_DATA_CFM)
|
||||
aicwf_sdio_host_tx_cfm_handler(&(rx_priv->sdiodev->rwnx_hw->sdio_env), (u32 *)(msg + 4));
|
||||
if ((*(msg + 2) & 0x7f) ==
|
||||
SDIO_TYPE_CFG_DATA_CFM)
|
||||
aicwf_sdio_host_tx_cfm_handler(
|
||||
&(rx_priv->sdiodev->rwnx_hw
|
||||
->sdio_env),
|
||||
(u32 *)(msg + 4));
|
||||
|
||||
if ((*(msg + 2) & 0x7f) == SDIO_TYPE_CFG_PRINT)
|
||||
rwnx_rx_handle_print(rx_priv->sdiodev->rwnx_hw, msg + 4, aggr_len);
|
||||
rwnx_rx_handle_print(
|
||||
rx_priv->sdiodev->rwnx_hw,
|
||||
msg + 4, aggr_len);
|
||||
|
||||
skb_pull(skb, adjust_len+4);
|
||||
skb_pull(skb, adjust_len + 4);
|
||||
kfree(msg);
|
||||
}
|
||||
}
|
||||
@@ -431,11 +493,11 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
dev_kfree_skb(skb);
|
||||
atomic_dec(&rx_priv->rx_cnt);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SDIO_PWRCTRL)
|
||||
#if defined(CONFIG_SDIO_PWRCTRL)
|
||||
aicwf_sdio_pwr_stctl(rx_priv->sdiodev, SDIO_ACTIVE_ST);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
#else //AICWF_USB_SUPPORT
|
||||
@@ -467,17 +529,20 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
if (pkt_len > 1600) {
|
||||
dev_kfree_skb(skb);
|
||||
atomic_dec(&rx_priv->rx_cnt);
|
||||
continue;
|
||||
continue;
|
||||
}
|
||||
|
||||
if ((skb->data[2] & USB_TYPE_CFG) != USB_TYPE_CFG) { // type : data
|
||||
if ((skb->data[2] & USB_TYPE_CFG) !=
|
||||
USB_TYPE_CFG) { // type : data
|
||||
aggr_len = pkt_len + RX_HWHRD_LEN;
|
||||
if (aggr_len & (RX_ALIGNMENT - 1))
|
||||
adjust_len = roundup(aggr_len, RX_ALIGNMENT);
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
skb_inblock = __dev_alloc_skb(aggr_len + CCMP_OR_WEP_INFO, GFP_KERNEL);//8 is for ccmp mic or wep icv
|
||||
skb_inblock = __dev_alloc_skb(
|
||||
aggr_len + CCMP_OR_WEP_INFO,
|
||||
GFP_KERNEL); //8 is for ccmp mic or wep icv
|
||||
if (skb_inblock == NULL) {
|
||||
txrx_err("no more space! skip!\n");
|
||||
skb_pull(skb, adjust_len);
|
||||
@@ -486,7 +551,8 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
|
||||
skb_put(skb_inblock, aggr_len);
|
||||
memcpy(skb_inblock->data, data, aggr_len);
|
||||
rwnx_rxdataind_aicwf(rx_priv->usbdev->rwnx_hw, skb_inblock, (void *)rx_priv);
|
||||
rwnx_rxdataind_aicwf(rx_priv->usbdev->rwnx_hw,
|
||||
skb_inblock, (void *)rx_priv);
|
||||
///TODO: here need to add rx data process
|
||||
|
||||
skb_pull(skb, adjust_len);
|
||||
@@ -497,7 +563,7 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
else
|
||||
adjust_len = aggr_len;
|
||||
|
||||
msg = kmalloc(aggr_len+4, GFP_KERNEL);
|
||||
msg = kmalloc(aggr_len + 4, GFP_KERNEL);
|
||||
if (msg == NULL) {
|
||||
txrx_err("no more space for msg!\n");
|
||||
aicwf_dev_skb_free(skb);
|
||||
@@ -505,10 +571,14 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
}
|
||||
memcpy(msg, data, aggr_len + 4);
|
||||
if ((*(msg + 2) & 0x7f) == USB_TYPE_CFG_CMD_RSP)
|
||||
rwnx_rx_handle_msg(rx_priv->usbdev->rwnx_hw, (struct ipc_e2a_msg *)(msg + 4));
|
||||
rwnx_rx_handle_msg(
|
||||
rx_priv->usbdev->rwnx_hw,
|
||||
(struct ipc_e2a_msg *)(msg + 4));
|
||||
|
||||
if ((*(msg + 2) & 0x7f) == USB_TYPE_CFG_DATA_CFM)
|
||||
aicwf_usb_host_tx_cfm_handler(&(rx_priv->usbdev->rwnx_hw->usb_env), (u32 *)(msg + 4));
|
||||
aicwf_usb_host_tx_cfm_handler(
|
||||
&(rx_priv->usbdev->rwnx_hw->usb_env),
|
||||
(u32 *)(msg + 4));
|
||||
skb_pull(skb, adjust_len + 4);
|
||||
kfree(msg);
|
||||
}
|
||||
@@ -521,12 +591,13 @@ int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv)
|
||||
#endif //AICWF_SDIO_SUPPORT
|
||||
}
|
||||
|
||||
static struct recv_msdu *aicwf_rxframe_queue_init(struct list_head *q, int qsize)
|
||||
static struct recv_msdu *aicwf_rxframe_queue_init(struct list_head *q,
|
||||
int qsize)
|
||||
{
|
||||
int i;
|
||||
struct recv_msdu *req, *reqs;
|
||||
|
||||
reqs = vmalloc(qsize*sizeof(struct recv_msdu));
|
||||
reqs = vmalloc(qsize * sizeof(struct recv_msdu));
|
||||
if (reqs == NULL)
|
||||
return NULL;
|
||||
|
||||
@@ -553,22 +624,23 @@ struct aicwf_rx_priv *aicwf_rx_init(void *arg)
|
||||
rx_priv->usbdev = (struct aic_usb_dev *)arg;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
aicwf_rxframe_queue_init_2(&rx_priv->rxq, MAX_RXQLEN);
|
||||
#else
|
||||
#else
|
||||
aicwf_frame_queue_init(&rx_priv->rxq, 1, MAX_RXQLEN);
|
||||
#endif
|
||||
#endif
|
||||
spin_lock_init(&rx_priv->rxqlock);
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
spin_lock_init(&rx_priv->rxbuff_lock);
|
||||
aicwf_prealloc_init();
|
||||
#endif
|
||||
#endif
|
||||
atomic_set(&rx_priv->rx_cnt, 0);
|
||||
|
||||
#ifdef AICWF_RX_REORDER
|
||||
INIT_LIST_HEAD(&rx_priv->rxframes_freequeue);
|
||||
spin_lock_init(&rx_priv->freeq_lock);
|
||||
rx_priv->recv_frames = aicwf_rxframe_queue_init(&rx_priv->rxframes_freequeue, MAX_REORD_RXFRAME);
|
||||
rx_priv->recv_frames = aicwf_rxframe_queue_init(
|
||||
&rx_priv->rxframes_freequeue, MAX_REORD_RXFRAME);
|
||||
if (!rx_priv->recv_frames) {
|
||||
txrx_err("no enough buffer for free recv frame queue!\n");
|
||||
kfree(rx_priv);
|
||||
@@ -581,12 +653,11 @@ struct aicwf_rx_priv *aicwf_rx_init(void *arg)
|
||||
return rx_priv;
|
||||
}
|
||||
|
||||
|
||||
static void aicwf_recvframe_queue_deinit(struct list_head *q)
|
||||
{
|
||||
struct recv_msdu *req, *next;
|
||||
|
||||
list_for_each_entry_safe(req, next, q, rxframe_list) {
|
||||
list_for_each_entry_safe (req, next, q, rxframe_list) {
|
||||
list_del_init(&req->rxframe_list);
|
||||
}
|
||||
}
|
||||
@@ -598,12 +669,10 @@ void aicwf_rx_deinit(struct aicwf_rx_priv *rx_priv)
|
||||
|
||||
AICWFDBG(LOGINFO, "%s\n", __func__);
|
||||
|
||||
spin_lock_bh(&rx_priv->stas_reord_lock);
|
||||
list_for_each_entry_safe(reord_info, tmp,
|
||||
&rx_priv->stas_reord_list, list) {
|
||||
list_for_each_entry_safe (reord_info, tmp, &rx_priv->stas_reord_list,
|
||||
list) {
|
||||
reord_deinit_sta(rx_priv, reord_info);
|
||||
}
|
||||
spin_unlock_bh(&rx_priv->stas_reord_lock);
|
||||
#endif
|
||||
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
@@ -614,14 +683,14 @@ void aicwf_rx_deinit(struct aicwf_rx_priv *rx_priv)
|
||||
rx_priv->sdiodev->bus_if->busrx_thread = NULL;
|
||||
}
|
||||
#ifdef CONFIG_OOB
|
||||
if(rx_priv->sdiodev->oob_enable){
|
||||
//new oob feature
|
||||
if (rx_priv->sdiodev->bus_if->busirq_thread) {
|
||||
complete_all(&rx_priv->sdiodev->bus_if->busirq_trgg);
|
||||
kthread_stop(rx_priv->sdiodev->bus_if->busirq_thread);
|
||||
rx_priv->sdiodev->bus_if->busirq_thread = NULL;
|
||||
}
|
||||
}
|
||||
if (rx_priv->sdiodev->oob_enable) {
|
||||
//new oob feature
|
||||
if (rx_priv->sdiodev->bus_if->busirq_thread) {
|
||||
complete_all(&rx_priv->sdiodev->bus_if->busirq_trgg);
|
||||
kthread_stop(rx_priv->sdiodev->bus_if->busirq_thread);
|
||||
rx_priv->sdiodev->bus_if->busirq_thread = NULL;
|
||||
}
|
||||
}
|
||||
#endif //CONFIG_OOB
|
||||
#endif
|
||||
#ifdef AICWF_USB_SUPPORT
|
||||
@@ -632,11 +701,11 @@ void aicwf_rx_deinit(struct aicwf_rx_priv *rx_priv)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
rxbuff_queue_flush(rx_priv);
|
||||
#else
|
||||
#else
|
||||
aicwf_frame_queue_flush(&rx_priv->rxq);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef AICWF_RX_REORDER
|
||||
aicwf_recvframe_queue_deinit(&rx_priv->rxframes_freequeue);
|
||||
@@ -644,20 +713,20 @@ void aicwf_rx_deinit(struct aicwf_rx_priv *rx_priv)
|
||||
vfree(rx_priv->recv_frames);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
aicwf_prealloc_exit();
|
||||
#endif
|
||||
#endif
|
||||
kfree(rx_priv);
|
||||
|
||||
AICWFDBG(LOGINFO, "%s exit \n", __func__);
|
||||
}
|
||||
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q, struct sk_buff *pkt)
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt)
|
||||
{
|
||||
return aicwf_frame_enq(dev, q, pkt, 0);
|
||||
}
|
||||
|
||||
|
||||
void aicwf_dev_skb_free(struct sk_buff *skb)
|
||||
{
|
||||
if (!skb)
|
||||
@@ -666,7 +735,8 @@ void aicwf_dev_skb_free(struct sk_buff *skb)
|
||||
dev_kfree_skb_any(skb);
|
||||
}
|
||||
|
||||
static struct sk_buff *aicwf_frame_queue_penq(struct frame_queue *pq, int prio, struct sk_buff *p)
|
||||
static struct sk_buff *aicwf_frame_queue_penq(struct frame_queue *pq, int prio,
|
||||
struct sk_buff *p)
|
||||
{
|
||||
struct sk_buff_head *q;
|
||||
|
||||
@@ -690,7 +760,8 @@ void aicwf_frame_queue_flush(struct frame_queue *pq)
|
||||
|
||||
for (prio = 0; prio < pq->num_prio; prio++) {
|
||||
q = &pq->queuelist[prio];
|
||||
skb_queue_walk_safe(q, p, next) {
|
||||
skb_queue_walk_safe(q, p, next)
|
||||
{
|
||||
skb_unlink(p, q);
|
||||
aicwf_dev_skb_free(p);
|
||||
pq->qcnt--;
|
||||
@@ -702,7 +773,9 @@ void aicwf_frame_queue_init(struct frame_queue *pq, int num_prio, int max_len)
|
||||
{
|
||||
int prio;
|
||||
|
||||
memset(pq, 0, offsetof(struct frame_queue, queuelist) + (sizeof(struct sk_buff_head) * num_prio));
|
||||
memset(pq, 0,
|
||||
offsetof(struct frame_queue, queuelist) +
|
||||
(sizeof(struct sk_buff_head) * num_prio));
|
||||
pq->num_prio = (u16)num_prio;
|
||||
pq->qmax = (u16)max_len;
|
||||
|
||||
@@ -711,7 +784,8 @@ void aicwf_frame_queue_init(struct frame_queue *pq, int num_prio, int max_len)
|
||||
}
|
||||
}
|
||||
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq, int *prio_out)
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq,
|
||||
int *prio_out)
|
||||
{
|
||||
int prio;
|
||||
|
||||
@@ -750,7 +824,8 @@ struct sk_buff *aicwf_frame_dequeue(struct frame_queue *pq)
|
||||
if (pq->qcnt == 0)
|
||||
return NULL;
|
||||
|
||||
while ((prio = pq->hi_prio) > 0 && skb_queue_empty(&pq->queuelist[prio]))
|
||||
while ((prio = pq->hi_prio) > 0 &&
|
||||
skb_queue_empty(&pq->queuelist[prio]))
|
||||
pq->hi_prio--;
|
||||
|
||||
q = &pq->queuelist[prio];
|
||||
@@ -776,9 +851,10 @@ static struct sk_buff *aicwf_skb_dequeue_tail(struct frame_queue *pq, int prio)
|
||||
}
|
||||
#endif
|
||||
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q, struct sk_buff *pkt, int prio)
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt, int prio)
|
||||
{
|
||||
#if 0
|
||||
#if 0
|
||||
struct sk_buff *p = NULL;
|
||||
int prio_modified = -1;
|
||||
|
||||
@@ -807,79 +883,78 @@ bool aicwf_frame_enq(struct device *dev, struct frame_queue *q, struct sk_buff *
|
||||
}
|
||||
|
||||
return p != NULL;
|
||||
#else
|
||||
#else
|
||||
if (q->queuelist[prio].qlen < q->qmax && q->qcnt < q->qmax) {
|
||||
aicwf_frame_queue_penq(q, prio, pkt);
|
||||
return true;
|
||||
} else
|
||||
aicwf_frame_queue_penq(q, prio, pkt);
|
||||
return true;
|
||||
} else
|
||||
return false;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
void rxbuff_free(struct rx_buff *rxbuff)
|
||||
{
|
||||
kfree(rxbuff->data);
|
||||
kfree(rxbuff);
|
||||
kfree(rxbuff->data);
|
||||
kfree(rxbuff);
|
||||
}
|
||||
|
||||
struct rx_buff *rxbuff_queue_penq(struct rx_frame_queue *pq, struct rx_buff *p)
|
||||
{
|
||||
struct list_head *q;
|
||||
if (pq->qcnt >= pq->qmax)
|
||||
return NULL;
|
||||
|
||||
struct list_head *q;
|
||||
if (pq->qcnt >= pq->qmax)
|
||||
return NULL;
|
||||
q = &pq->queuelist;
|
||||
list_add_tail(&p->queue, q);
|
||||
|
||||
q = &pq->queuelist;
|
||||
list_add_tail(&p->queue,q);
|
||||
pq->qcnt++;
|
||||
|
||||
pq->qcnt++;
|
||||
|
||||
return p;
|
||||
return p;
|
||||
}
|
||||
|
||||
struct rx_buff *rxbuff_dequeue(struct rx_frame_queue *pq)
|
||||
{
|
||||
struct rx_buff *p = NULL;
|
||||
struct rx_buff *p = NULL;
|
||||
|
||||
if (pq->qcnt == 0) {
|
||||
printk("%s %d, rxq is empty\n", __func__, __LINE__);
|
||||
return NULL;
|
||||
}
|
||||
if (pq->qcnt == 0) {
|
||||
printk("%s %d, rxq is empty\n", __func__, __LINE__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if(list_empty(&pq->queuelist)) {
|
||||
printk("%s %d, rxq is empty\n", __func__, __LINE__);
|
||||
return NULL;
|
||||
} else {
|
||||
p = list_first_entry(&pq->queuelist, struct rx_buff, queue);
|
||||
list_del_init(&p->queue);
|
||||
pq->qcnt--;
|
||||
}
|
||||
if (list_empty(&pq->queuelist)) {
|
||||
printk("%s %d, rxq is empty\n", __func__, __LINE__);
|
||||
return NULL;
|
||||
} else {
|
||||
p = list_first_entry(&pq->queuelist, struct rx_buff, queue);
|
||||
list_del_init(&p->queue);
|
||||
pq->qcnt--;
|
||||
}
|
||||
|
||||
return p;
|
||||
return p;
|
||||
}
|
||||
|
||||
bool aicwf_rxbuff_enqueue(struct device *dev, struct rx_frame_queue *rxq, struct rx_buff *pkt)
|
||||
bool aicwf_rxbuff_enqueue(struct device *dev, struct rx_frame_queue *rxq,
|
||||
struct rx_buff *pkt)
|
||||
{
|
||||
// struct rx_buff *p = NULL;
|
||||
// struct rx_buff *p = NULL;
|
||||
|
||||
if ((rxq == NULL) || (pkt == NULL)) {
|
||||
printk("%s %d, rxq or pkt is NULL\n", __func__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
if ((rxq == NULL) || (pkt == NULL)) {
|
||||
printk("%s %d, rxq or pkt is NULL\n", __func__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (rxq->qcnt < rxq->qmax) {
|
||||
if (rxbuff_queue_penq(rxq, pkt)) {
|
||||
return true;
|
||||
} else {
|
||||
printk("%s %d, rxbuff enqueue fail\n", __func__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
printk("%s %d, rxq or pkt is full\n", __func__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
if (rxq->qcnt < rxq->qmax) {
|
||||
if (rxbuff_queue_penq(rxq, pkt)) {
|
||||
return true;
|
||||
} else {
|
||||
printk("%s %d, rxbuff enqueue fail\n", __func__,
|
||||
__LINE__);
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
printk("%s %d, rxq or pkt is full\n", __func__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@@ -19,70 +19,70 @@
|
||||
#include "aicwf_usb.h"
|
||||
#endif
|
||||
|
||||
#define CMD_BUF_MAX 1536
|
||||
#define TXPKT_BLOCKSIZE 512
|
||||
#define MAX_AGGR_TXPKT_LEN (1536*64)
|
||||
#define CMD_TX_TIMEOUT 5000
|
||||
#define TX_ALIGNMENT 4
|
||||
#define CMD_BUF_MAX 1536
|
||||
#define TXPKT_BLOCKSIZE 512
|
||||
#define MAX_AGGR_TXPKT_LEN (1536 * 64)
|
||||
#define CMD_TX_TIMEOUT 5000
|
||||
#define TX_ALIGNMENT 4
|
||||
|
||||
#define RX_HWHRD_LEN 60 //58->60 word allined
|
||||
#define CCMP_OR_WEP_INFO 8
|
||||
#define MAX_RXQLEN 2000
|
||||
#define RX_ALIGNMENT 4
|
||||
#define RX_HWHRD_LEN 60 //58->60 word allined
|
||||
#define CCMP_OR_WEP_INFO 8
|
||||
#define MAX_RXQLEN 2000
|
||||
#define RX_ALIGNMENT 4
|
||||
|
||||
#define DEBUG_ERROR_LEVEL 0
|
||||
#define DEBUG_DEBUG_LEVEL 1
|
||||
#define DEBUG_INFO_LEVEL 2
|
||||
#define DEBUG_ERROR_LEVEL 0
|
||||
#define DEBUG_DEBUG_LEVEL 1
|
||||
#define DEBUG_INFO_LEVEL 2
|
||||
|
||||
#define DBG_LEVEL DEBUG_DEBUG_LEVEL
|
||||
#define DBG_LEVEL DEBUG_DEBUG_LEVEL
|
||||
|
||||
#define txrx_err(fmt, ...) pr_err("txrx_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define sdio_err(fmt, ...) pr_err("sdio_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define usb_err(fmt, ...) pr_err("usb_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define txrx_err(fmt, ...) \
|
||||
pr_err("txrx_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define sdio_err(fmt, ...) \
|
||||
pr_err("sdio_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#define usb_err(fmt, ...) \
|
||||
pr_err("usb_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#if DBG_LEVEL >= DEBUG_DEBUG_LEVEL
|
||||
#define txrx_dbg(fmt, ...) printk("txrx: " fmt, ##__VA_ARGS__)
|
||||
#define sdio_dbg(fmt, ...) printk("aicsdio: " fmt, ##__VA_ARGS__)
|
||||
#define usb_dbg(fmt, ...) printk("aicusb: " fmt, ##__VA_ARGS__)
|
||||
#define txrx_dbg(fmt, ...) printk("txrx: " fmt, ##__VA_ARGS__)
|
||||
#define sdio_dbg(fmt, ...) printk("aicsdio: " fmt, ##__VA_ARGS__)
|
||||
#define usb_dbg(fmt, ...) printk("aicusb: " fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define txrx_dbg(fmt, ...)
|
||||
#define sdio_dbg(fmt, ...)
|
||||
#define usb_dbg(fmt, ...)
|
||||
#endif
|
||||
#if DBG_LEVEL >= DEBUG_INFO_LEVEL
|
||||
#define txrx_info(fmt, ...) printk("aicsdio: " fmt, ##__VA_ARGS__)
|
||||
#define sdio_info(fmt, ...) printk("aicsdio: " fmt, ##__VA_ARGS__)
|
||||
#define usb_info(fmt, ...) printk("aicusb: " fmt, ##__VA_ARGS__)
|
||||
#define txrx_info(fmt, ...) printk("aicsdio: " fmt, ##__VA_ARGS__)
|
||||
#define sdio_info(fmt, ...) printk("aicsdio: " fmt, ##__VA_ARGS__)
|
||||
#define usb_info(fmt, ...) printk("aicusb: " fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define txrx_info(fmt, ...)
|
||||
#define sdio_info(fmt, ...)
|
||||
#define usb_info(fmt, ...)
|
||||
#endif
|
||||
|
||||
enum aicwf_bus_state {
|
||||
BUS_DOWN_ST,
|
||||
BUS_UP_ST
|
||||
};
|
||||
enum aicwf_bus_state { BUS_DOWN_ST, BUS_UP_ST };
|
||||
|
||||
struct aicwf_bus_ops {
|
||||
int (*start) (struct device *dev);
|
||||
void (*stop) (struct device *dev);
|
||||
int (*txdata) (struct device *dev, struct sk_buff *skb);
|
||||
int (*txmsg) (struct device *dev, u8 *msg, uint len);
|
||||
int (*start)(struct device *dev);
|
||||
void (*stop)(struct device *dev);
|
||||
int (*txdata)(struct device *dev, struct sk_buff *skb);
|
||||
int (*txmsg)(struct device *dev, u8 *msg, uint len);
|
||||
};
|
||||
|
||||
struct frame_queue {
|
||||
u16 num_prio;
|
||||
u16 hi_prio;
|
||||
u16 qmax; /* max number of queued frames */
|
||||
u16 qcnt;
|
||||
u16 num_prio;
|
||||
u16 hi_prio;
|
||||
u16 qmax; /* max number of queued frames */
|
||||
u16 qcnt;
|
||||
struct sk_buff_head queuelist[8];
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
struct rx_frame_queue {
|
||||
u16 qmax; /* max number of queued frames */
|
||||
u16 qcnt;
|
||||
struct list_head queuelist;
|
||||
u16 qmax; /* max number of queued frames */
|
||||
u16 qcnt;
|
||||
struct list_head queuelist;
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -97,12 +97,26 @@ struct aicwf_bus {
|
||||
u8 *cmd_buf;
|
||||
struct completion bustx_trgg;
|
||||
struct completion busrx_trgg;
|
||||
struct completion busirq_trgg;//new oob feature
|
||||
struct completion busirq_trgg; //new oob feature
|
||||
struct task_struct *bustx_thread;
|
||||
struct task_struct *busrx_thread;
|
||||
struct task_struct *busirq_thread;//new oob feature
|
||||
struct task_struct *busirq_thread; //new oob feature
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SDIO_ADMA
|
||||
#define SDIO_HEADER_LEN 4
|
||||
#define SDIO_DATA_FAKE_LEN 2
|
||||
#define SDIO_MGMT_FAKE_LEN 4
|
||||
#define ALIGN4_ADJ_LEN(x) ((4 - (x & 3)) & 3)
|
||||
|
||||
#define SDIO_TX_SLIST_MAX 136
|
||||
|
||||
/*struct tx_scatterlist {
|
||||
const void *buf;
|
||||
unsigned int len;
|
||||
};*/
|
||||
#endif
|
||||
|
||||
struct aicwf_tx_priv {
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
struct aic_sdio_dev *sdiodev;
|
||||
@@ -128,16 +142,23 @@ struct aicwf_tx_priv {
|
||||
atomic_t aggr_count;
|
||||
u8 *head;
|
||||
u8 *tail;
|
||||
|
||||
#ifdef CONFIG_SDIO_ADMA
|
||||
struct tx_scatterlist sg_list[SDIO_TX_SLIST_MAX];
|
||||
void *free_buf[SDIO_TX_SLIST_MAX];
|
||||
bool copyd[SDIO_TX_SLIST_MAX];
|
||||
u32 aggr_segcnt;
|
||||
u32 len;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
#define DEFRAG_MAX_WAIT 40 //100
|
||||
#define DEFRAG_MAX_WAIT 40 //100
|
||||
#ifdef AICWF_RX_REORDER
|
||||
#define MAX_REORD_RXFRAME 250
|
||||
#define REORDER_UPDATE_TIME 50
|
||||
#define AICWF_REORDER_WINSIZE 64
|
||||
#define SN_LESS(a, b) (((a-b)&0x800) != 0)
|
||||
#define SN_EQUAL(a, b) (a == b)
|
||||
#define MAX_REORD_RXFRAME 250
|
||||
#define REORDER_UPDATE_TIME 50
|
||||
#define AICWF_REORDER_WINSIZE 64
|
||||
#define SN_LESS(a, b) (((a - b) & 0x800) != 0)
|
||||
#define SN_EQUAL(a, b) (a == b)
|
||||
|
||||
struct reord_ctrl {
|
||||
struct aicwf_rx_priv *rx_priv;
|
||||
@@ -157,14 +178,14 @@ struct reord_ctrl_info {
|
||||
};
|
||||
|
||||
struct recv_msdu {
|
||||
struct sk_buff *pkt;
|
||||
u8 tid;
|
||||
u16 seq_num;
|
||||
u8 forward;
|
||||
//uint len;
|
||||
u32 is_amsdu;
|
||||
u8 *rx_data;
|
||||
//for pending rx reorder list
|
||||
struct sk_buff *pkt;
|
||||
u8 tid;
|
||||
u16 seq_num;
|
||||
u8 forward;
|
||||
//uint len;
|
||||
u32 is_amsdu;
|
||||
u8 *rx_data;
|
||||
//for pending rx reorder list
|
||||
struct list_head reord_pending_list;
|
||||
//for total frame list, when rxframe from busif, dequeue, when submit frame to net, enqueue
|
||||
struct list_head rxframe_list;
|
||||
@@ -184,11 +205,11 @@ struct aicwf_rx_priv {
|
||||
atomic_t rx_cnt;
|
||||
u32 data_len;
|
||||
spinlock_t rxqlock;
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
struct rx_frame_queue rxq;
|
||||
#else
|
||||
#else
|
||||
struct frame_queue rxq;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef AICWF_RX_REORDER
|
||||
spinlock_t freeq_lock;
|
||||
@@ -243,19 +264,23 @@ struct aicwf_tx_priv *aicwf_tx_init(void *arg);
|
||||
struct aicwf_rx_priv *aicwf_rx_init(void *arg);
|
||||
void aicwf_frame_queue_init(struct frame_queue *pq, int num_prio, int max_len);
|
||||
void aicwf_frame_queue_flush(struct frame_queue *pq);
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q, struct sk_buff *pkt, int prio);
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q, struct sk_buff *pkt);
|
||||
bool aicwf_frame_enq(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt, int prio);
|
||||
bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q,
|
||||
struct sk_buff *pkt);
|
||||
bool aicwf_is_framequeue_empty(struct frame_queue *pq);
|
||||
void aicwf_frame_tx(void *dev, struct sk_buff *skb);
|
||||
void aicwf_dev_skb_free(struct sk_buff *skb);
|
||||
struct sk_buff *aicwf_frame_dequeue(struct frame_queue *pq);
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq, int *prio_out);
|
||||
struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq,
|
||||
int *prio_out);
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB
|
||||
void rxbuff_queue_flush(struct aicwf_rx_priv* rx_priv);
|
||||
void rxbuff_queue_flush(struct aicwf_rx_priv *rx_priv);
|
||||
void aicwf_rxframe_queue_init_2(struct rx_frame_queue *pq, int max_len);
|
||||
void rxbuff_free(struct rx_buff *rxbuff);
|
||||
struct rx_buff *rxbuff_dequeue(struct rx_frame_queue *pq);
|
||||
bool aicwf_rxbuff_enqueue(struct device *dev, struct rx_frame_queue *rxq, struct rx_buff *pkt);
|
||||
bool aicwf_rxbuff_enqueue(struct device *dev, struct rx_frame_queue *rxq,
|
||||
struct rx_buff *pkt);
|
||||
extern struct aicwf_rx_buff_list aic_rx_buff_list;
|
||||
#endif
|
||||
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
void aicwf_usb_tx_flowctrl(struct rwnx_hw *rwnx_hw, bool state)
|
||||
{
|
||||
struct rwnx_vif *rwnx_vif;
|
||||
list_for_each_entry(rwnx_vif, &rwnx_hw->vifs, list) {
|
||||
list_for_each_entry (rwnx_vif, &rwnx_hw->vifs, list) {
|
||||
if (!rwnx_vif->up)
|
||||
continue;
|
||||
if (!rwnx_vif->ndev)
|
||||
@@ -31,7 +31,9 @@ void aicwf_usb_tx_flowctrl(struct rwnx_hw *rwnx_hw, bool state)
|
||||
}
|
||||
|
||||
static struct aicwf_usb_buf *aicwf_usb_tx_dequeue(struct aic_usb_dev *usb_dev,
|
||||
struct list_head *q, int *counter, spinlock_t *qlock)
|
||||
struct list_head *q,
|
||||
int *counter,
|
||||
spinlock_t *qlock)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct aicwf_usb_buf *usb_buf;
|
||||
@@ -49,9 +51,9 @@ static struct aicwf_usb_buf *aicwf_usb_tx_dequeue(struct aic_usb_dev *usb_dev,
|
||||
return usb_buf;
|
||||
}
|
||||
|
||||
static void aicwf_usb_tx_queue(struct aic_usb_dev *usb_dev,
|
||||
struct list_head *q, struct aicwf_usb_buf *usb_buf, int *counter,
|
||||
spinlock_t *qlock)
|
||||
static void aicwf_usb_tx_queue(struct aic_usb_dev *usb_dev, struct list_head *q,
|
||||
struct aicwf_usb_buf *usb_buf, int *counter,
|
||||
spinlock_t *qlock)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
@@ -70,14 +72,16 @@ static struct aicwf_usb_buf *aicwf_usb_rx_buf_get(struct aic_usb_dev *usb_dev)
|
||||
if (list_empty(&usb_dev->rx_free_list)) {
|
||||
usb_buf = NULL;
|
||||
} else {
|
||||
usb_buf = list_first_entry(&usb_dev->rx_free_list, struct aicwf_usb_buf, list);
|
||||
usb_buf = list_first_entry(&usb_dev->rx_free_list,
|
||||
struct aicwf_usb_buf, list);
|
||||
list_del_init(&usb_buf->list);
|
||||
}
|
||||
spin_unlock_irqrestore(&usb_dev->rx_free_lock, flags);
|
||||
return usb_buf;
|
||||
}
|
||||
|
||||
static void aicwf_usb_rx_buf_put(struct aic_usb_dev *usb_dev, struct aicwf_usb_buf *usb_buf)
|
||||
static void aicwf_usb_rx_buf_put(struct aic_usb_dev *usb_dev,
|
||||
struct aicwf_usb_buf *usb_buf)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
@@ -89,7 +93,7 @@ static void aicwf_usb_rx_buf_put(struct aic_usb_dev *usb_dev, struct aicwf_usb_b
|
||||
static void aicwf_usb_tx_complete(struct urb *urb)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct aicwf_usb_buf *usb_buf = (struct aicwf_usb_buf *) urb->context;
|
||||
struct aicwf_usb_buf *usb_buf = (struct aicwf_usb_buf *)urb->context;
|
||||
struct aic_usb_dev *usb_dev = usb_buf->usbdev;
|
||||
struct sk_buff *skb;
|
||||
u8 *buf;
|
||||
@@ -108,7 +112,7 @@ static void aicwf_usb_tx_complete(struct urb *urb)
|
||||
usb_buf->skb = NULL;
|
||||
|
||||
aicwf_usb_tx_queue(usb_dev, &usb_dev->tx_free_list, usb_buf,
|
||||
&usb_dev->tx_free_count, &usb_dev->tx_free_lock);
|
||||
&usb_dev->tx_free_count, &usb_dev->tx_free_lock);
|
||||
|
||||
spin_lock_irqsave(&usb_dev->tx_flow_lock, flags);
|
||||
if (usb_dev->tx_free_count > AICWF_USB_TX_HIGH_WATER) {
|
||||
@@ -118,11 +122,11 @@ static void aicwf_usb_tx_complete(struct urb *urb)
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&usb_dev->tx_flow_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
static void aicwf_usb_rx_complete(struct urb *urb)
|
||||
{
|
||||
struct aicwf_usb_buf *usb_buf = (struct aicwf_usb_buf *) urb->context;
|
||||
struct aicwf_usb_buf *usb_buf = (struct aicwf_usb_buf *)urb->context;
|
||||
struct aic_usb_dev *usb_dev = usb_buf->usbdev;
|
||||
struct aicwf_rx_priv *rx_priv = usb_dev->rx_priv;
|
||||
struct sk_buff *skb = NULL;
|
||||
@@ -169,7 +173,7 @@ static void aicwf_usb_rx_complete(struct urb *urb)
|
||||
}
|
||||
|
||||
static int aicwf_usb_submit_rx_urb(struct aic_usb_dev *usb_dev,
|
||||
struct aicwf_usb_buf *usb_buf)
|
||||
struct aicwf_usb_buf *usb_buf)
|
||||
{
|
||||
struct sk_buff *skb;
|
||||
int ret;
|
||||
@@ -191,10 +195,9 @@ static int aicwf_usb_submit_rx_urb(struct aic_usb_dev *usb_dev,
|
||||
|
||||
usb_buf->skb = skb;
|
||||
|
||||
usb_fill_bulk_urb(usb_buf->urb,
|
||||
usb_dev->udev,
|
||||
usb_dev->bulk_in_pipe,
|
||||
skb->data, skb_tailroom(skb), aicwf_usb_rx_complete, usb_buf);
|
||||
usb_fill_bulk_urb(usb_buf->urb, usb_dev->udev, usb_dev->bulk_in_pipe,
|
||||
skb->data, skb_tailroom(skb), aicwf_usb_rx_complete,
|
||||
usb_buf);
|
||||
|
||||
usb_buf->usbdev = usb_dev;
|
||||
|
||||
@@ -241,13 +244,15 @@ static void aicwf_usb_tx_prepare(struct aic_usb_dev *usb_dev)
|
||||
|
||||
while (!list_empty(&usb_dev->tx_post_list)) {
|
||||
usb_buf = aicwf_usb_tx_dequeue(usb_dev, &usb_dev->tx_post_list,
|
||||
&usb_dev->tx_post_count, &usb_dev->tx_post_lock);
|
||||
&usb_dev->tx_post_count,
|
||||
&usb_dev->tx_post_lock);
|
||||
if (usb_buf->skb) {
|
||||
dev_kfree_skb(usb_buf->skb);
|
||||
usb_buf->skb = NULL;
|
||||
}
|
||||
aicwf_usb_tx_queue(usb_dev, &usb_dev->tx_free_list, usb_buf,
|
||||
&usb_dev->tx_free_count, &usb_dev->tx_free_lock);
|
||||
&usb_dev->tx_free_count,
|
||||
&usb_dev->tx_free_lock);
|
||||
}
|
||||
}
|
||||
static void aicwf_usb_tx_process(struct aic_usb_dev *usb_dev)
|
||||
@@ -263,7 +268,8 @@ static void aicwf_usb_tx_process(struct aic_usb_dev *usb_dev)
|
||||
}
|
||||
|
||||
usb_buf = aicwf_usb_tx_dequeue(usb_dev, &usb_dev->tx_post_list,
|
||||
&usb_dev->tx_post_count, &usb_dev->tx_post_lock);
|
||||
&usb_dev->tx_post_count,
|
||||
&usb_dev->tx_post_lock);
|
||||
if (!usb_buf) {
|
||||
usb_err("can not get usb_buf from tx_post_list!\n");
|
||||
return;
|
||||
@@ -277,11 +283,12 @@ static void aicwf_usb_tx_process(struct aic_usb_dev *usb_dev)
|
||||
}
|
||||
|
||||
continue;
|
||||
fail:
|
||||
fail:
|
||||
dev_kfree_skb(usb_buf->skb);
|
||||
usb_buf->skb = NULL;
|
||||
aicwf_usb_tx_queue(usb_dev, &usb_dev->tx_free_list, usb_buf,
|
||||
&usb_dev->tx_free_count, &usb_dev->tx_free_lock);
|
||||
&usb_dev->tx_free_count,
|
||||
&usb_dev->tx_free_lock);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -328,7 +335,7 @@ int usb_busrx_thread(void *data)
|
||||
|
||||
static void aicwf_usb_send_msg_complete(struct urb *urb)
|
||||
{
|
||||
struct aic_usb_dev *usb_dev = (struct aic_usb_dev *) urb->context;
|
||||
struct aic_usb_dev *usb_dev = (struct aic_usb_dev *)urb->context;
|
||||
|
||||
usb_dev->msg_finished = true;
|
||||
if (waitqueue_active(&usb_dev->msg_wait))
|
||||
@@ -354,10 +361,9 @@ static int aicwf_usb_bus_txmsg(struct device *dev, u8 *buf, u32 len)
|
||||
|
||||
usb_dev->msg_finished = false;
|
||||
|
||||
usb_fill_bulk_urb(usb_dev->msg_out_urb,
|
||||
usb_dev->udev,
|
||||
usb_dev->bulk_out_pipe,
|
||||
buf, len, (usb_complete_t) aicwf_usb_send_msg_complete, usb_dev);
|
||||
usb_fill_bulk_urb(usb_dev->msg_out_urb, usb_dev->udev,
|
||||
usb_dev->bulk_out_pipe, buf, len,
|
||||
(usb_complete_t)aicwf_usb_send_msg_complete, usb_dev);
|
||||
usb_dev->msg_out_urb->transfer_flags |= URB_ZERO_PACKET;
|
||||
|
||||
ret = usb_submit_urb(usb_dev->msg_out_urb, GFP_ATOMIC);
|
||||
@@ -366,8 +372,8 @@ static int aicwf_usb_bus_txmsg(struct device *dev, u8 *buf, u32 len)
|
||||
goto exit;
|
||||
}
|
||||
|
||||
ret = wait_event_timeout(usb_dev->msg_wait,
|
||||
usb_dev->msg_finished, msecs_to_jiffies(CMD_TX_TIMEOUT));
|
||||
ret = wait_event_timeout(usb_dev->msg_wait, usb_dev->msg_finished,
|
||||
msecs_to_jiffies(CMD_TX_TIMEOUT));
|
||||
if (!ret) {
|
||||
if (usb_dev->msg_out_urb)
|
||||
usb_kill_urb(usb_dev->msg_out_urb);
|
||||
@@ -386,15 +392,14 @@ exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void aicwf_usb_free_urb(struct list_head *q, spinlock_t *qlock)
|
||||
{
|
||||
struct aicwf_usb_buf *usb_buf, *tmp;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(qlock, flags);
|
||||
list_for_each_entry_safe(usb_buf, tmp, q, list) {
|
||||
spin_unlock_irqrestore(qlock, flags);
|
||||
list_for_each_entry_safe (usb_buf, tmp, q, list) {
|
||||
spin_unlock_irqrestore(qlock, flags);
|
||||
if (!usb_buf->urb) {
|
||||
usb_err("bad usb_buf\n");
|
||||
spin_lock_irqsave(qlock, flags);
|
||||
@@ -452,7 +457,6 @@ err:
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
static void aicwf_usb_state_change(struct aic_usb_dev *usb_dev, int state)
|
||||
{
|
||||
int old_state;
|
||||
@@ -484,7 +488,7 @@ static int aicwf_usb_bus_txdata(struct device *dev, struct sk_buff *skb)
|
||||
struct rwnx_txhdr *txhdr = (struct rwnx_txhdr *)skb->data;
|
||||
struct rwnx_hw *rwnx_hw = usb_dev->rwnx_hw;
|
||||
u8 usb_header[4];
|
||||
u8 adj_buf[4] = {0};
|
||||
u8 adj_buf[4] = { 0 };
|
||||
u16 index = 0;
|
||||
bool need_cfm = false;
|
||||
|
||||
@@ -496,9 +500,11 @@ static int aicwf_usb_bus_txdata(struct device *dev, struct sk_buff *skb)
|
||||
}
|
||||
|
||||
usb_buf = aicwf_usb_tx_dequeue(usb_dev, &usb_dev->tx_free_list,
|
||||
&usb_dev->tx_free_count, &usb_dev->tx_free_lock);
|
||||
&usb_dev->tx_free_count,
|
||||
&usb_dev->tx_free_lock);
|
||||
if (!usb_buf) {
|
||||
usb_err("free:%d, post:%d\n", usb_dev->tx_free_count, usb_dev->tx_post_count);
|
||||
usb_err("free:%d, post:%d\n", usb_dev->tx_free_count,
|
||||
usb_dev->tx_post_count);
|
||||
kmem_cache_free(rwnx_hw->sw_txhdr_cache, txhdr->sw_hdr);
|
||||
dev_kfree_skb_any(skb);
|
||||
ret = -ENOMEM;
|
||||
@@ -509,18 +515,20 @@ static int aicwf_usb_bus_txdata(struct device *dev, struct sk_buff *skb)
|
||||
need_cfm = true;
|
||||
buf = kmalloc(skb->len, GFP_KERNEL);
|
||||
index += sizeof(usb_header);
|
||||
memcpy(&buf[index], (u8 *)(long)&txhdr->sw_hdr->desc, sizeof(struct txdesc_api));
|
||||
memcpy(&buf[index], (u8 *)(long)&txhdr->sw_hdr->desc,
|
||||
sizeof(struct txdesc_api));
|
||||
index += sizeof(struct txdesc_api);
|
||||
memcpy(&buf[index], &skb->data[txhdr->sw_hdr->headroom], skb->len - txhdr->sw_hdr->headroom);
|
||||
memcpy(&buf[index], &skb->data[txhdr->sw_hdr->headroom],
|
||||
skb->len - txhdr->sw_hdr->headroom);
|
||||
index += skb->len - txhdr->sw_hdr->headroom;
|
||||
buf_len = index;
|
||||
if (buf_len & (TX_ALIGNMENT - 1)) {
|
||||
adjust_len = roundup(buf_len, TX_ALIGNMENT)-buf_len;
|
||||
adjust_len = roundup(buf_len, TX_ALIGNMENT) - buf_len;
|
||||
memcpy(&buf[buf_len], adj_buf, adjust_len);
|
||||
buf_len += adjust_len;
|
||||
}
|
||||
usb_header[0] = ((buf_len) & 0xff);
|
||||
usb_header[1] = (((buf_len) >> 8)&0x0f);
|
||||
usb_header[0] = ((buf_len)&0xff);
|
||||
usb_header[1] = (((buf_len) >> 8) & 0x0f);
|
||||
usb_header[2] = 0x01; //data
|
||||
usb_header[3] = 0; //reserved
|
||||
memcpy(&buf[0], usb_header, sizeof(usb_header));
|
||||
@@ -528,12 +536,13 @@ static int aicwf_usb_bus_txdata(struct device *dev, struct sk_buff *skb)
|
||||
} else {
|
||||
skb_pull(skb, txhdr->sw_hdr->headroom);
|
||||
skb_push(skb, sizeof(struct txdesc_api));
|
||||
memcpy(&skb->data[0], (u8 *)(long)&txhdr->sw_hdr->desc, sizeof(struct txdesc_api));
|
||||
memcpy(&skb->data[0], (u8 *)(long)&txhdr->sw_hdr->desc,
|
||||
sizeof(struct txdesc_api));
|
||||
kmem_cache_free(rwnx_hw->sw_txhdr_cache, txhdr->sw_hdr);
|
||||
|
||||
skb_push(skb, sizeof(usb_header));
|
||||
usb_header[0] = ((skb->len) & 0xff);
|
||||
usb_header[1] = (((skb->len) >> 8)&0x0f);
|
||||
usb_header[1] = (((skb->len) >> 8) & 0x0f);
|
||||
usb_header[2] = 0x01; //data
|
||||
usb_header[3] = 0; //reserved
|
||||
memcpy(&skb->data[0], usb_header, sizeof(usb_header));
|
||||
@@ -549,15 +558,15 @@ static int aicwf_usb_bus_txdata(struct device *dev, struct sk_buff *skb)
|
||||
else
|
||||
usb_buf->cfm = false;
|
||||
usb_fill_bulk_urb(usb_buf->urb, usb_dev->udev, usb_dev->bulk_out_pipe,
|
||||
buf, buf_len, aicwf_usb_tx_complete, usb_buf);
|
||||
buf, buf_len, aicwf_usb_tx_complete, usb_buf);
|
||||
usb_buf->urb->transfer_flags |= URB_ZERO_PACKET;
|
||||
|
||||
aicwf_usb_tx_queue(usb_dev, &usb_dev->tx_post_list, usb_buf,
|
||||
&usb_dev->tx_post_count, &usb_dev->tx_post_lock);
|
||||
&usb_dev->tx_post_count, &usb_dev->tx_post_lock);
|
||||
complete(&bus_if->bustx_trgg);
|
||||
ret = 0;
|
||||
|
||||
flow_ctrl:
|
||||
flow_ctrl:
|
||||
spin_lock_irqsave(&usb_dev->tx_flow_lock, flags);
|
||||
if (usb_dev->tx_free_count < AICWF_USB_TX_LOW_WATER) {
|
||||
usb_dev->tbusy = true;
|
||||
@@ -591,7 +600,7 @@ static void aicwf_usb_cancel_all_urbs(struct aic_usb_dev *usb_dev)
|
||||
usb_kill_urb(usb_dev->msg_out_urb);
|
||||
|
||||
spin_lock_irqsave(&usb_dev->tx_post_lock, flags);
|
||||
list_for_each_entry_safe(usb_buf, tmp, &usb_dev->tx_post_list, list) {
|
||||
list_for_each_entry_safe (usb_buf, tmp, &usb_dev->tx_post_list, list) {
|
||||
spin_unlock_irqrestore(&usb_dev->tx_post_lock, flags);
|
||||
if (!usb_buf->urb) {
|
||||
usb_err("bad usb_buf\n");
|
||||
@@ -632,7 +641,8 @@ static void aicwf_usb_deinit(struct aic_usb_dev *usbdev)
|
||||
|
||||
static void aicwf_usb_rx_urb_work(struct work_struct *work)
|
||||
{
|
||||
struct aic_usb_dev *usb_dev = container_of(work, struct aic_usb_dev, rx_urb_work);
|
||||
struct aic_usb_dev *usb_dev =
|
||||
container_of(work, struct aic_usb_dev, rx_urb_work);
|
||||
|
||||
aicwf_usb_rx_submit_all_urb(usb_dev);
|
||||
}
|
||||
@@ -659,16 +669,15 @@ static int aicwf_usb_init(struct aic_usb_dev *usb_dev)
|
||||
usb_dev->tx_free_count = 0;
|
||||
usb_dev->tx_post_count = 0;
|
||||
|
||||
ret = aicwf_usb_alloc_rx_urb(usb_dev);
|
||||
ret = aicwf_usb_alloc_rx_urb(usb_dev);
|
||||
if (ret) {
|
||||
goto error;
|
||||
}
|
||||
ret = aicwf_usb_alloc_tx_urb(usb_dev);
|
||||
ret = aicwf_usb_alloc_tx_urb(usb_dev);
|
||||
if (ret) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
||||
usb_dev->msg_out_urb = usb_alloc_urb(0, GFP_ATOMIC);
|
||||
if (!usb_dev->msg_out_urb) {
|
||||
usb_err("usb_alloc_urb (msg out) failed\n");
|
||||
@@ -679,14 +688,14 @@ static int aicwf_usb_init(struct aic_usb_dev *usb_dev)
|
||||
INIT_WORK(&usb_dev->rx_urb_work, aicwf_usb_rx_urb_work);
|
||||
|
||||
return ret;
|
||||
error:
|
||||
error:
|
||||
usb_err("failed!\n");
|
||||
aicwf_usb_deinit(usb_dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static int aicwf_parse_usb(struct aic_usb_dev *usb_dev, struct usb_interface *interface)
|
||||
static int aicwf_parse_usb(struct aic_usb_dev *usb_dev,
|
||||
struct usb_interface *interface)
|
||||
{
|
||||
struct usb_interface_descriptor *interface_desc;
|
||||
struct usb_host_interface *host_interface;
|
||||
@@ -706,7 +715,7 @@ static int aicwf_parse_usb(struct aic_usb_dev *usb_dev, struct usb_interface *in
|
||||
/* Check device configuration */
|
||||
if (usb->descriptor.bNumConfigurations != 1) {
|
||||
usb_err("Number of configurations: %d not supported\n",
|
||||
usb->descriptor.bNumConfigurations);
|
||||
usb->descriptor.bNumConfigurations);
|
||||
ret = -ENODEV;
|
||||
goto exit;
|
||||
}
|
||||
@@ -715,7 +724,7 @@ static int aicwf_parse_usb(struct aic_usb_dev *usb_dev, struct usb_interface *in
|
||||
#ifndef CONFIG_USB_BT
|
||||
if (usb->descriptor.bDeviceClass != 0x00) {
|
||||
usb_err("DeviceClass %d not supported\n",
|
||||
usb->descriptor.bDeviceClass);
|
||||
usb->descriptor.bDeviceClass);
|
||||
ret = -ENODEV;
|
||||
goto exit;
|
||||
}
|
||||
@@ -727,18 +736,20 @@ static int aicwf_parse_usb(struct aic_usb_dev *usb_dev, struct usb_interface *in
|
||||
#else
|
||||
if (usb->actconfig->desc.bNumInterfaces != 1) {
|
||||
#endif
|
||||
usb_err("Number of interfaces: %d not supported\n",
|
||||
usb->actconfig->desc.bNumInterfaces);
|
||||
ret = -ENODEV;
|
||||
goto exit;
|
||||
usb_err("Number of interfaces: %d not supported\n",
|
||||
usb->actconfig->desc.bNumInterfaces);
|
||||
ret = -ENODEV;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if ((interface_desc->bInterfaceClass != USB_CLASS_VENDOR_SPEC) ||
|
||||
(interface_desc->bInterfaceSubClass != 0xff) ||
|
||||
(interface_desc->bInterfaceProtocol != 0xff)) {
|
||||
(interface_desc->bInterfaceSubClass != 0xff) ||
|
||||
(interface_desc->bInterfaceProtocol != 0xff)) {
|
||||
usb_err("non WLAN interface %d: 0x%x:0x%x:0x%x\n",
|
||||
interface_desc->bInterfaceNumber, interface_desc->bInterfaceClass,
|
||||
interface_desc->bInterfaceSubClass, interface_desc->bInterfaceProtocol);
|
||||
interface_desc->bInterfaceNumber,
|
||||
interface_desc->bInterfaceClass,
|
||||
interface_desc->bInterfaceSubClass,
|
||||
interface_desc->bInterfaceProtocol);
|
||||
ret = -ENODEV;
|
||||
goto exit;
|
||||
}
|
||||
@@ -748,16 +759,18 @@ static int aicwf_parse_usb(struct aic_usb_dev *usb_dev, struct usb_interface *in
|
||||
endpoint_num = usb_endpoint_num(endpoint);
|
||||
|
||||
if (usb_endpoint_dir_in(endpoint) &&
|
||||
usb_endpoint_xfer_bulk(endpoint)) {
|
||||
usb_endpoint_xfer_bulk(endpoint)) {
|
||||
if (!usb_dev->bulk_in_pipe) {
|
||||
usb_dev->bulk_in_pipe = usb_rcvbulkpipe(usb, endpoint_num);
|
||||
usb_dev->bulk_in_pipe =
|
||||
usb_rcvbulkpipe(usb, endpoint_num);
|
||||
}
|
||||
}
|
||||
|
||||
if (usb_endpoint_dir_out(endpoint) &&
|
||||
usb_endpoint_xfer_bulk(endpoint)) {
|
||||
usb_endpoint_xfer_bulk(endpoint)) {
|
||||
if (!usb_dev->bulk_out_pipe) {
|
||||
usb_dev->bulk_out_pipe = usb_sndbulkpipe(usb, endpoint_num);
|
||||
usb_dev->bulk_out_pipe =
|
||||
usb_sndbulkpipe(usb, endpoint_num);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -778,12 +791,10 @@ static int aicwf_parse_usb(struct aic_usb_dev *usb_dev, struct usb_interface *in
|
||||
else
|
||||
printk("Aic full speed USB device detected\n");
|
||||
|
||||
exit:
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static struct aicwf_bus_ops aicwf_usb_bus_ops = {
|
||||
.start = aicwf_usb_bus_start,
|
||||
.stop = aicwf_usb_bus_stop,
|
||||
@@ -791,11 +802,12 @@ static struct aicwf_bus_ops aicwf_usb_bus_ops = {
|
||||
.txmsg = aicwf_usb_bus_txmsg,
|
||||
};
|
||||
|
||||
static int aicwf_usb_probe(struct usb_interface *intf, const struct usb_device_id *id)
|
||||
static int aicwf_usb_probe(struct usb_interface *intf,
|
||||
const struct usb_device_id *id)
|
||||
{
|
||||
int ret = 0;
|
||||
struct usb_device *usb = interface_to_usbdev(intf);
|
||||
struct aicwf_bus *bus_if ;
|
||||
struct aicwf_bus *bus_if;
|
||||
struct device *dev = NULL;
|
||||
struct aicwf_rx_priv *rx_priv = NULL;
|
||||
struct aic_usb_dev *usb_dev = NULL;
|
||||
@@ -874,7 +886,7 @@ out_free:
|
||||
static void aicwf_usb_disconnect(struct usb_interface *intf)
|
||||
{
|
||||
struct aic_usb_dev *usb_dev =
|
||||
(struct aic_usb_dev *) usb_get_intfdata(intf);
|
||||
(struct aic_usb_dev *)usb_get_intfdata(intf);
|
||||
|
||||
if (!usb_dev)
|
||||
return;
|
||||
@@ -892,7 +904,7 @@ static void aicwf_usb_disconnect(struct usb_interface *intf)
|
||||
static int aicwf_usb_suspend(struct usb_interface *intf, pm_message_t state)
|
||||
{
|
||||
struct aic_usb_dev *usb_dev =
|
||||
(struct aic_usb_dev *) usb_get_intfdata(intf);
|
||||
(struct aic_usb_dev *)usb_get_intfdata(intf);
|
||||
|
||||
aicwf_usb_state_change(usb_dev, USB_SLEEP_ST);
|
||||
aicwf_bus_stop(usb_dev->bus_if);
|
||||
@@ -902,7 +914,7 @@ static int aicwf_usb_suspend(struct usb_interface *intf, pm_message_t state)
|
||||
static int aicwf_usb_resume(struct usb_interface *intf)
|
||||
{
|
||||
struct aic_usb_dev *usb_dev =
|
||||
(struct aic_usb_dev *) usb_get_intfdata(intf);
|
||||
(struct aic_usb_dev *)usb_get_intfdata(intf);
|
||||
|
||||
if (usb_dev->state == USB_UP_ST)
|
||||
return 0;
|
||||
@@ -918,9 +930,10 @@ static int aicwf_usb_reset_resume(struct usb_interface *intf)
|
||||
|
||||
static struct usb_device_id aicwf_usb_id_table[] = {
|
||||
#ifndef CONFIG_USB_BT
|
||||
{USB_DEVICE(USB_VENDOR_ID_AIC, USB_PRODUCT_ID_AIC)},
|
||||
{ USB_DEVICE(USB_VENDOR_ID_AIC, USB_PRODUCT_ID_AIC) },
|
||||
#else
|
||||
{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_AIC, USB_PRODUCT_ID_AIC, 0xff, 0xff, 0xff)},
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_AIC, USB_PRODUCT_ID_AIC,
|
||||
0xff, 0xff, 0xff) },
|
||||
#endif
|
||||
{}
|
||||
};
|
||||
|
||||
@@ -15,32 +15,28 @@
|
||||
#ifdef AICWF_USB_SUPPORT
|
||||
|
||||
/* USB Device ID */
|
||||
#define USB_VENDOR_ID_AIC 0xA69C
|
||||
#define USB_VENDOR_ID_AIC 0xA69C
|
||||
|
||||
#ifndef CONFIG_USB_BT
|
||||
#define USB_PRODUCT_ID_AIC 0x8800
|
||||
#define USB_PRODUCT_ID_AIC 0x8800
|
||||
#else
|
||||
#define USB_PRODUCT_ID_AIC 0x8801
|
||||
#define USB_PRODUCT_ID_AIC 0x8801
|
||||
#endif
|
||||
|
||||
#define AICWF_USB_RX_URBS (200)
|
||||
#define AICWF_USB_TX_URBS (100)
|
||||
#define AICWF_USB_TX_LOW_WATER (AICWF_USB_TX_URBS/4)
|
||||
#define AICWF_USB_TX_HIGH_WATER (AICWF_USB_TX_LOW_WATER*3)
|
||||
#define AICWF_USB_MAX_PKT_SIZE (2048)
|
||||
#define AICWF_USB_RX_URBS (200)
|
||||
#define AICWF_USB_TX_URBS (100)
|
||||
#define AICWF_USB_TX_LOW_WATER (AICWF_USB_TX_URBS / 4)
|
||||
#define AICWF_USB_TX_HIGH_WATER (AICWF_USB_TX_LOW_WATER * 3)
|
||||
#define AICWF_USB_MAX_PKT_SIZE (2048)
|
||||
|
||||
typedef enum {
|
||||
USB_TYPE_DATA = 0X00,
|
||||
USB_TYPE_CFG = 0X10,
|
||||
USB_TYPE_CFG_CMD_RSP = 0X11,
|
||||
USB_TYPE_DATA = 0X00,
|
||||
USB_TYPE_CFG = 0X10,
|
||||
USB_TYPE_CFG_CMD_RSP = 0X11,
|
||||
USB_TYPE_CFG_DATA_CFM = 0X12
|
||||
} usb_type;
|
||||
|
||||
enum aicwf_usb_state {
|
||||
USB_DOWN_ST,
|
||||
USB_UP_ST,
|
||||
USB_SLEEP_ST
|
||||
};
|
||||
enum aicwf_usb_state { USB_DOWN_ST, USB_UP_ST, USB_SLEEP_ST };
|
||||
|
||||
struct aicwf_usb_buf {
|
||||
struct list_head list;
|
||||
|
||||
+285
@@ -0,0 +1,285 @@
|
||||
/*
|
||||
*
|
||||
* Generic Bluetooth SDIO driver
|
||||
*
|
||||
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
|
||||
* Copyright (C) 2007 Marcel Holtmann <marcel@holtmann.org>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/skbuff.h>
|
||||
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/sdio_ids.h>
|
||||
#include <linux/mmc/sdio_func.h>
|
||||
|
||||
#include <net/bluetooth/bluetooth.h>
|
||||
|
||||
#include "aic_btsdio.h"
|
||||
#include "rwnx_msg_tx.h"
|
||||
|
||||
#include <net/bluetooth/hci_core.h>
|
||||
|
||||
#define VERSION "0.1"
|
||||
#if CONFIG_BLUEDROID == 0
|
||||
struct btsdio_data {
|
||||
struct hci_dev *hdev;
|
||||
|
||||
struct work_struct work;
|
||||
|
||||
struct sk_buff_head txq;
|
||||
};
|
||||
struct hci_dev *ghdev = NULL;
|
||||
|
||||
void bt_data_dump(char *tag, void *data, unsigned long len)
|
||||
{
|
||||
unsigned long i = 0;
|
||||
uint8_t *data_ = (uint8_t *)data;
|
||||
|
||||
printk("%s %s len:(%lu)\r\n", __func__, tag, len);
|
||||
|
||||
for (i = 0; i < len; i += 16) {
|
||||
printk("%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\r\n",
|
||||
data_[0 + i], data_[1 + i], data_[2 + i], data_[3 + i],
|
||||
data_[4 + i], data_[5 + i], data_[6 + i], data_[7 + i],
|
||||
data_[8 + i], data_[9 + i], data_[10 + i], data_[11 + i],
|
||||
data_[12 + i], data_[13 + i], data_[14 + i],
|
||||
data_[15 + i]);
|
||||
}
|
||||
}
|
||||
|
||||
static int btsdio_tx_packet(struct btsdio_data *data, struct sk_buff *skb)
|
||||
{
|
||||
int err;
|
||||
|
||||
AICBT_INFO("%s", data->hdev->name);
|
||||
|
||||
/* Prepend Type-A header */
|
||||
skb_push(skb, 1);
|
||||
skb->data[0] = hci_skb_pkt_type(skb);
|
||||
|
||||
//bt_data_dump("btwrite", skb->data, skb->len);
|
||||
err = rwnx_sdio_bt_send_req(g_rwnx_plat->sdiodev->rwnx_hw, skb->len,
|
||||
skb);
|
||||
if (err < 0) {
|
||||
printk("%s rwnx_sdio_bt_send_req error %d", __func__, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
data->hdev->stat.byte_tx += skb->len;
|
||||
|
||||
kfree_skb(skb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void btsdio_work(struct work_struct *work)
|
||||
{
|
||||
struct btsdio_data *data = container_of(work, struct btsdio_data, work);
|
||||
struct sk_buff *skb;
|
||||
int err;
|
||||
|
||||
AICBT_INFO("%s,%s", data->hdev->name, __func__);
|
||||
|
||||
while ((skb = skb_dequeue(&data->txq))) {
|
||||
err = btsdio_tx_packet(data, skb);
|
||||
if (err < 0) {
|
||||
data->hdev->stat.err_tx++;
|
||||
skb_queue_head(&data->txq, skb);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Get HCI device by index.
|
||||
* Device is held on return. */
|
||||
struct hci_dev *hci_dev_get(int index)
|
||||
{
|
||||
if (index != 0)
|
||||
return NULL;
|
||||
|
||||
return ghdev;
|
||||
}
|
||||
|
||||
int bt_sdio_recv(u8 *data, u32 data_len)
|
||||
{
|
||||
struct sk_buff *skb;
|
||||
int type = data[0];
|
||||
struct hci_dev *hdev;
|
||||
u32 len = data_len;
|
||||
int ret = 0;
|
||||
hdev = hci_dev_get(0);
|
||||
if (!hdev) {
|
||||
AICWFDBG(LOGERROR, "%s: Failed to get hci dev[NULL]", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
skb = alloc_skb(len - 1, GFP_ATOMIC);
|
||||
if (!skb) {
|
||||
AICWFDBG(LOGERROR, "alloc skb fail %s \n", __func__);
|
||||
}
|
||||
memcpy(skb_put(skb, len - 1), (data + 1), len - 1);
|
||||
hdev->stat.byte_rx += len;
|
||||
hci_skb_pkt_type(skb) = type;
|
||||
//if(bt_bypass_event(skb)){
|
||||
//kfree_skb(skb);
|
||||
///return 0;
|
||||
//}
|
||||
AICBT_INFO("skb type %d", type);
|
||||
//bt_data_dump("bt_skb", skb, skb->len);
|
||||
ret = hci_recv_frame(hdev, skb);
|
||||
if (ret < 0) {
|
||||
AICWFDBG(LOGERROR, "hci_recv_frame fail %d\n", ret);
|
||||
hdev->stat.err_rx++;
|
||||
kfree_skb(skb);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int btsdio_open(struct hci_dev *hdev)
|
||||
{
|
||||
//struct btsdio_data *data = hci_get_drvdata(hdev);
|
||||
int err = 0;
|
||||
|
||||
AICBT_INFO("%s", hdev->name);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int btsdio_close(struct hci_dev *hdev)
|
||||
{
|
||||
//struct btsdio_data *data = hci_get_drvdata(hdev);
|
||||
|
||||
AICBT_INFO("%s,%s", hdev->name, __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int btsdio_flush(struct hci_dev *hdev)
|
||||
{
|
||||
struct btsdio_data *data = hci_get_drvdata(hdev);
|
||||
|
||||
AICBT_INFO("%s,%s", hdev->name, __func__);
|
||||
|
||||
skb_queue_purge(&data->txq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int btsdio_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
|
||||
{
|
||||
struct btsdio_data *data = hci_get_drvdata(hdev);
|
||||
|
||||
AICBT_INFO("%s,%s", hdev->name, __func__);
|
||||
|
||||
switch (hci_skb_pkt_type(skb)) {
|
||||
case HCI_COMMAND_PKT:
|
||||
hdev->stat.cmd_tx++;
|
||||
break;
|
||||
|
||||
case HCI_ACLDATA_PKT:
|
||||
hdev->stat.acl_tx++;
|
||||
break;
|
||||
|
||||
case HCI_SCODATA_PKT:
|
||||
hdev->stat.sco_tx++;
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EILSEQ;
|
||||
}
|
||||
|
||||
skb_queue_tail(&data->txq, skb);
|
||||
|
||||
schedule_work(&data->work);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int btsdio_init(void)
|
||||
{
|
||||
struct btsdio_data *data;
|
||||
struct hci_dev *hdev;
|
||||
int err;
|
||||
|
||||
AICBT_INFO("%s", __func__);
|
||||
|
||||
data = kzalloc(sizeof(struct btsdio_data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_WORK(&data->work, btsdio_work);
|
||||
|
||||
skb_queue_head_init(&data->txq);
|
||||
|
||||
hdev = hci_alloc_dev();
|
||||
if (!hdev)
|
||||
return -ENOMEM;
|
||||
|
||||
hdev->bus = HCI_SDIO;
|
||||
hci_set_drvdata(hdev, data);
|
||||
|
||||
hdev->dev_type = HCI_PRIMARY;
|
||||
|
||||
data->hdev = hdev;
|
||||
|
||||
hdev->open = btsdio_open;
|
||||
hdev->close = btsdio_close;
|
||||
hdev->flush = btsdio_flush;
|
||||
hdev->send = btsdio_send_frame;
|
||||
|
||||
err = hci_register_dev(hdev);
|
||||
if (err < 0) {
|
||||
hci_free_dev(hdev);
|
||||
return err;
|
||||
}
|
||||
ghdev = hdev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void btsdio_remove(void)
|
||||
{
|
||||
struct btsdio_data *data;
|
||||
struct hci_dev *hdev;
|
||||
hdev = hci_dev_get(0);
|
||||
if (!hdev) {
|
||||
AICBT_ERR("%s: Failed to get hci dev[Null]", __func__);
|
||||
return;
|
||||
}
|
||||
data = hci_get_drvdata(hdev);
|
||||
|
||||
AICBT_INFO("btsdio_remove");
|
||||
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
kfree(data);
|
||||
|
||||
hci_unregister_dev(hdev);
|
||||
|
||||
hci_free_dev(hdev);
|
||||
}
|
||||
#endif
|
||||
@@ -19,10 +19,10 @@
|
||||
|
||||
/* Rate and policy table */
|
||||
|
||||
#define N_CCK 8
|
||||
#define N_CCK 8
|
||||
#define N_OFDM 8
|
||||
#define N_HT (8 * 2 * 2 * 4)
|
||||
#define N_VHT (10 * 4 * 2 * 8)
|
||||
#define N_HT (8 * 2 * 2 * 4)
|
||||
#define N_VHT (10 * 4 * 2 * 8)
|
||||
#define N_HE_SU (12 * 4 * 3 * 8)
|
||||
#define N_HE_MU (12 * 6 * 3 * 8)
|
||||
#define N_HE_ER (3 * 3 + 3) //RU242 + RU106
|
||||
@@ -33,51 +33,63 @@ extern const int chnl2bw[];
|
||||
/* conversion table from MACHW to NL80211 enum */
|
||||
extern const int bw2chnl[];
|
||||
|
||||
/* Rate cntrl info */
|
||||
#define MCS_INDEX_TX_RCX_OFT 0
|
||||
#define MCS_INDEX_TX_RCX_MASK (0x7F << MCS_INDEX_TX_RCX_OFT)
|
||||
#define BW_TX_RCX_OFT 7
|
||||
#define BW_TX_RCX_MASK (0x3 << BW_TX_RCX_OFT)
|
||||
#define SHORT_GI_TX_RCX_OFT 9
|
||||
#define SHORT_GI_TX_RCX_MASK (0x1 << SHORT_GI_TX_RCX_OFT)
|
||||
#define PRE_TYPE_TX_RCX_OFT 10
|
||||
#define PRE_TYPE_TX_RCX_MASK (0x1 << PRE_TYPE_TX_RCX_OFT)
|
||||
#define FORMAT_MOD_TX_RCX_OFT 11
|
||||
#define FORMAT_MOD_TX_RCX_MASK (0x7 << FORMAT_MOD_TX_RCX_OFT)
|
||||
|
||||
/* Values for formatModTx */
|
||||
#define FORMATMOD_NON_HT 0
|
||||
#define FORMATMOD_NON_HT 0
|
||||
#define FORMATMOD_NON_HT_DUP_OFDM 1
|
||||
#define FORMATMOD_HT_MF 2
|
||||
#define FORMATMOD_HT_GF 3
|
||||
#define FORMATMOD_VHT 4
|
||||
#define FORMATMOD_HE_SU 5
|
||||
#define FORMATMOD_HE_MU 6
|
||||
#define FORMATMOD_HE_ER 7
|
||||
#define FORMATMOD_HE_TB 8
|
||||
#define FORMATMOD_HT_MF 2
|
||||
#define FORMATMOD_HT_GF 3
|
||||
#define FORMATMOD_VHT 4
|
||||
#define FORMATMOD_HE_SU 5
|
||||
#define FORMATMOD_HE_MU 6
|
||||
#define FORMATMOD_HE_ER 7
|
||||
#define FORMATMOD_HE_TB 8
|
||||
|
||||
/* Values for navProtFrmEx */
|
||||
#define NAV_PROT_NO_PROT_BIT 0
|
||||
#define NAV_PROT_SELF_CTS_BIT 1
|
||||
#define NAV_PROT_RTS_CTS_BIT 2
|
||||
#define NAV_PROT_RTS_CTS_WITH_QAP_BIT 3
|
||||
#define NAV_PROT_STBC_BIT 4
|
||||
#define NAV_PROT_NO_PROT_BIT 0
|
||||
#define NAV_PROT_SELF_CTS_BIT 1
|
||||
#define NAV_PROT_RTS_CTS_BIT 2
|
||||
#define NAV_PROT_RTS_CTS_WITH_QAP_BIT 3
|
||||
#define NAV_PROT_STBC_BIT 4
|
||||
|
||||
/* THD MACCTRLINFO2 fields, used in struct umacdesc umac.flags */
|
||||
/// WhichDescriptor definition - contains aMPDU bit and position value
|
||||
/// Offset of WhichDescriptor field in the MAC CONTROL INFO 2 word
|
||||
#define WHICHDESC_OFT 19
|
||||
#define WHICHDESC_OFT 19
|
||||
/// Mask of the WhichDescriptor field
|
||||
#define WHICHDESC_MSK (0x07 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_MSK (0x07 << WHICHDESC_OFT)
|
||||
/// Only 1 THD possible, describing an unfragmented MSDU
|
||||
#define WHICHDESC_UNFRAGMENTED_MSDU (0x00 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_UNFRAGMENTED_MSDU (0x00 << WHICHDESC_OFT)
|
||||
/// THD describing the first MPDU of a fragmented MSDU
|
||||
#define WHICHDESC_FRAGMENTED_MSDU_FIRST (0x01 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_FRAGMENTED_MSDU_FIRST (0x01 << WHICHDESC_OFT)
|
||||
/// THD describing intermediate MPDUs of a fragmented MSDU
|
||||
#define WHICHDESC_FRAGMENTED_MSDU_INT (0x02 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_FRAGMENTED_MSDU_INT (0x02 << WHICHDESC_OFT)
|
||||
/// THD describing the last MPDU of a fragmented MSDU
|
||||
#define WHICHDESC_FRAGMENTED_MSDU_LAST (0x03 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_FRAGMENTED_MSDU_LAST (0x03 << WHICHDESC_OFT)
|
||||
/// THD for extra descriptor starting an AMPDU
|
||||
#define WHICHDESC_AMPDU_EXTRA (0x04 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_AMPDU_EXTRA (0x04 << WHICHDESC_OFT)
|
||||
/// THD describing the first MPDU of an A-MPDU
|
||||
#define WHICHDESC_AMPDU_FIRST (0x05 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_AMPDU_FIRST (0x05 << WHICHDESC_OFT)
|
||||
/// THD describing intermediate MPDUs of an A-MPDU
|
||||
#define WHICHDESC_AMPDU_INT (0x06 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_AMPDU_INT (0x06 << WHICHDESC_OFT)
|
||||
/// THD describing the last MPDU of an A-MPDU
|
||||
#define WHICHDESC_AMPDU_LAST (0x07 << WHICHDESC_OFT)
|
||||
#define WHICHDESC_AMPDU_LAST (0x07 << WHICHDESC_OFT)
|
||||
|
||||
/// aMPDU bit offset
|
||||
#define AMPDU_OFT 21
|
||||
#define AMPDU_OFT 21
|
||||
/// aMPDU bit
|
||||
#define AMPDU_BIT CO_BIT(AMPDU_OFT)
|
||||
#define AMPDU_BIT CO_BIT(AMPDU_OFT)
|
||||
|
||||
union rwnx_mcs_index {
|
||||
struct {
|
||||
@@ -95,40 +107,56 @@ union rwnx_mcs_index {
|
||||
u32 legacy : 7;
|
||||
};
|
||||
|
||||
enum {
|
||||
HW_RATE_1MBPS = 0,
|
||||
HW_RATE_2MBPS = 1,
|
||||
HW_RATE_5_5MBPS = 2,
|
||||
HW_RATE_11MBPS = 3,
|
||||
HW_RATE_6MBPS = 4,
|
||||
HW_RATE_9MBPS = 5,
|
||||
HW_RATE_12MBPS = 6,
|
||||
HW_RATE_18MBPS = 7,
|
||||
HW_RATE_24MBPS = 8,
|
||||
HW_RATE_36MBPS = 9,
|
||||
HW_RATE_48MBPS = 10,
|
||||
HW_RATE_54MBPS = 11,
|
||||
HW_RATE_MAX
|
||||
};
|
||||
|
||||
/* c.f RW-WLAN-nX-MAC-HW-UM */
|
||||
union rwnx_rate_ctrl_info {
|
||||
struct {
|
||||
u32 mcsIndexTx : 7;
|
||||
u32 bwTx : 2;
|
||||
u32 giAndPreTypeTx : 2;
|
||||
u32 formatModTx : 3;
|
||||
u32 navProtFrmEx : 3;
|
||||
u32 mcsIndexProtTx : 7;
|
||||
u32 bwProtTx : 2;
|
||||
u32 mcsIndexTx : 7;
|
||||
u32 bwTx : 2;
|
||||
u32 giAndPreTypeTx : 2;
|
||||
u32 formatModTx : 3;
|
||||
u32 navProtFrmEx : 3;
|
||||
u32 mcsIndexProtTx : 7;
|
||||
u32 bwProtTx : 2;
|
||||
u32 formatModProtTx : 3;
|
||||
u32 nRetry : 3;
|
||||
u32 nRetry : 3;
|
||||
};
|
||||
u32 value;
|
||||
};
|
||||
|
||||
/* c.f RW-WLAN-nX-MAC-HW-UM */
|
||||
struct rwnx_power_ctrl_info {
|
||||
u32 txPwrLevelPT : 8;
|
||||
u32 txPwrLevelProtPT : 8;
|
||||
u32 reserved :16;
|
||||
u32 txPwrLevelPT : 8;
|
||||
u32 txPwrLevelProtPT : 8;
|
||||
u32 reserved : 16;
|
||||
};
|
||||
|
||||
/* c.f RW-WLAN-nX-MAC-HW-UM */
|
||||
union rwnx_pol_phy_ctrl_info_1 {
|
||||
struct {
|
||||
u32 rsvd1 : 3;
|
||||
u32 bfFrmEx : 1;
|
||||
u32 rsvd1 : 3;
|
||||
u32 bfFrmEx : 1;
|
||||
u32 numExtnSS : 2;
|
||||
u32 fecCoding : 1;
|
||||
u32 stbc : 2;
|
||||
u32 rsvd2 : 5;
|
||||
u32 nTx : 3;
|
||||
u32 nTxProt : 3;
|
||||
u32 stbc : 2;
|
||||
u32 rsvd2 : 5;
|
||||
u32 nTx : 3;
|
||||
u32 nTxProt : 3;
|
||||
};
|
||||
u32 value;
|
||||
};
|
||||
@@ -137,7 +165,7 @@ union rwnx_pol_phy_ctrl_info_1 {
|
||||
union rwnx_pol_phy_ctrl_info_2 {
|
||||
struct {
|
||||
u32 antennaSet : 8;
|
||||
u32 smmIndex : 8;
|
||||
u32 smmIndex : 8;
|
||||
u32 beamFormed : 1;
|
||||
};
|
||||
u32 value;
|
||||
@@ -146,7 +174,7 @@ union rwnx_pol_phy_ctrl_info_2 {
|
||||
/* c.f RW-WLAN-nX-MAC-HW-UM */
|
||||
union rwnx_pol_mac_ctrl_info_1 {
|
||||
struct {
|
||||
u32 keySRamIndex : 10;
|
||||
u32 keySRamIndex : 10;
|
||||
u32 keySRamIndexRA : 10;
|
||||
};
|
||||
u32 value;
|
||||
@@ -155,14 +183,14 @@ union rwnx_pol_mac_ctrl_info_1 {
|
||||
/* c.f RW-WLAN-nX-MAC-HW-UM */
|
||||
union rwnx_pol_mac_ctrl_info_2 {
|
||||
struct {
|
||||
u32 longRetryLimit : 8;
|
||||
u32 longRetryLimit : 8;
|
||||
u32 shortRetryLimit : 8;
|
||||
u32 rtsThreshold : 12;
|
||||
u32 rtsThreshold : 12;
|
||||
};
|
||||
u32 value;
|
||||
};
|
||||
|
||||
#define POLICY_TABLE_PATTERN 0xBADCAB1E
|
||||
#define POLICY_TABLE_PATTERN 0xBADCAB1E
|
||||
|
||||
struct tx_policy_tbl {
|
||||
/* Unique Pattern at the start of Policy Table */
|
||||
@@ -176,7 +204,7 @@ struct tx_policy_tbl {
|
||||
/* MAC Control 2 Information used by MAC HW */
|
||||
union rwnx_pol_mac_ctrl_info_2 macctrlinfo_2;
|
||||
|
||||
union rwnx_rate_ctrl_info ratectrlinfos[NX_TX_MAX_RATES];
|
||||
union rwnx_rate_ctrl_info ratectrlinfos[NX_TX_MAX_RATES];
|
||||
struct rwnx_power_ctrl_info powerctrlinfos[NX_TX_MAX_RATES];
|
||||
};
|
||||
|
||||
@@ -194,11 +222,11 @@ struct tx_policy_tbl {
|
||||
*/
|
||||
union rwnx_hw_txstatus {
|
||||
struct {
|
||||
u32 tx_done : 1;
|
||||
u32 retry_required : 1;
|
||||
u32 sw_retry_required : 1;
|
||||
u32 acknowledged : 1;
|
||||
u32 reserved :28;
|
||||
u32 tx_done : 1;
|
||||
u32 retry_required : 1;
|
||||
u32 sw_retry_required : 1;
|
||||
u32 acknowledged : 1;
|
||||
u32 reserved : 28;
|
||||
};
|
||||
u32 value;
|
||||
};
|
||||
@@ -220,7 +248,7 @@ union rwnx_hw_txstatus {
|
||||
* @status: transmission status
|
||||
*/
|
||||
struct tx_cfm_tag {
|
||||
/*
|
||||
/*
|
||||
u16_l pn[4];
|
||||
u16_l sn;
|
||||
u16_l timestamp;
|
||||
@@ -231,7 +259,7 @@ struct tx_cfm_tag {
|
||||
u16_l amsdu_size;
|
||||
#endif
|
||||
union rwnx_hw_txstatus status;
|
||||
u32_l hostid;
|
||||
u32_l hostid;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -247,107 +275,108 @@ struct rwnx_hw_txhdr {
|
||||
|
||||
/* Modem */
|
||||
|
||||
#define MDM_PHY_CONFIG_TRIDENT 0
|
||||
#define MDM_PHY_CONFIG_ELMA 1
|
||||
#define MDM_PHY_CONFIG_KARST 2
|
||||
#define MDM_PHY_CONFIG_TRIDENT 0
|
||||
#define MDM_PHY_CONFIG_ELMA 1
|
||||
#define MDM_PHY_CONFIG_KARST 2
|
||||
|
||||
// MODEM features (from reg_mdm_stat.h)
|
||||
/// MUMIMOTX field bit
|
||||
#define MDM_MUMIMOTX_BIT ((u32)0x80000000)
|
||||
#define MDM_MUMIMOTX_BIT ((u32)0x80000000)
|
||||
/// MUMIMOTX field position
|
||||
#define MDM_MUMIMOTX_POS 31
|
||||
#define MDM_MUMIMOTX_POS 31
|
||||
/// MUMIMORX field bit
|
||||
#define MDM_MUMIMORX_BIT ((u32)0x40000000)
|
||||
#define MDM_MUMIMORX_BIT ((u32)0x40000000)
|
||||
/// MUMIMORX field position
|
||||
#define MDM_MUMIMORX_POS 30
|
||||
#define MDM_MUMIMORX_POS 30
|
||||
/// BFMER field bit
|
||||
#define MDM_BFMER_BIT ((u32)0x20000000)
|
||||
#define MDM_BFMER_BIT ((u32)0x20000000)
|
||||
/// BFMER field position
|
||||
#define MDM_BFMER_POS 29
|
||||
#define MDM_BFMER_POS 29
|
||||
/// BFMEE field bit
|
||||
#define MDM_BFMEE_BIT ((u32)0x10000000)
|
||||
#define MDM_BFMEE_BIT ((u32)0x10000000)
|
||||
/// BFMEE field position
|
||||
#define MDM_BFMEE_POS 28
|
||||
#define MDM_BFMEE_POS 28
|
||||
/// LDPCDEC field bit
|
||||
#define MDM_LDPCDEC_BIT ((u32)0x08000000)
|
||||
#define MDM_LDPCDEC_BIT ((u32)0x08000000)
|
||||
/// LDPCDEC field position
|
||||
#define MDM_LDPCDEC_POS 27
|
||||
#define MDM_LDPCDEC_POS 27
|
||||
/// LDPCENC field bit
|
||||
#define MDM_LDPCENC_BIT ((u32)0x04000000)
|
||||
#define MDM_LDPCENC_BIT ((u32)0x04000000)
|
||||
/// LDPCENC field position
|
||||
#define MDM_LDPCENC_POS 26
|
||||
#define MDM_LDPCENC_POS 26
|
||||
/// CHBW field mask
|
||||
#define MDM_CHBW_MASK ((u32)0x03000000)
|
||||
#define MDM_CHBW_MASK ((u32)0x03000000)
|
||||
/// CHBW field LSB position
|
||||
#define MDM_CHBW_LSB 24
|
||||
#define MDM_CHBW_LSB 24
|
||||
/// CHBW field width
|
||||
#define MDM_CHBW_WIDTH ((u32)0x00000002)
|
||||
#define MDM_CHBW_WIDTH ((u32)0x00000002)
|
||||
/// DSSSCCK field bit
|
||||
#define MDM_DSSSCCK_BIT ((u32)0x00800000)
|
||||
#define MDM_DSSSCCK_BIT ((u32)0x00800000)
|
||||
/// DSSSCCK field position
|
||||
#define MDM_DSSSCCK_POS 23
|
||||
#define MDM_DSSSCCK_POS 23
|
||||
/// VHT field bit
|
||||
#define MDM_VHT_BIT ((u32)0x00400000)
|
||||
#define MDM_VHT_BIT ((u32)0x00400000)
|
||||
/// VHT field position
|
||||
#define MDM_VHT_POS 22
|
||||
#define MDM_VHT_POS 22
|
||||
/// HE field bit
|
||||
#define MDM_HE_BIT ((u32)0x00200000)
|
||||
#define MDM_HE_BIT ((u32)0x00200000)
|
||||
/// HE field position
|
||||
#define MDM_HE_POS 21
|
||||
#define MDM_HE_POS 21
|
||||
/// ESS field bit
|
||||
#define MDM_ESS_BIT ((u32)0x00100000)
|
||||
#define MDM_ESS_BIT ((u32)0x00100000)
|
||||
/// ESS field position
|
||||
#define MDM_ESS_POS 20
|
||||
#define MDM_ESS_POS 20
|
||||
/// RFMODE field mask
|
||||
#define MDM_RFMODE_MASK ((u32)0x000F0000)
|
||||
#define MDM_RFMODE_MASK ((u32)0x000F0000)
|
||||
/// RFMODE field LSB position
|
||||
#define MDM_RFMODE_LSB 16
|
||||
#define MDM_RFMODE_LSB 16
|
||||
/// RFMODE field width
|
||||
#define MDM_RFMODE_WIDTH ((u32)0x00000004)
|
||||
#define MDM_RFMODE_WIDTH ((u32)0x00000004)
|
||||
/// NSTS field mask
|
||||
#define MDM_NSTS_MASK ((u32)0x0000F000)
|
||||
#define MDM_NSTS_MASK ((u32)0x0000F000)
|
||||
/// NSTS field LSB position
|
||||
#define MDM_NSTS_LSB 12
|
||||
#define MDM_NSTS_LSB 12
|
||||
/// NSTS field width
|
||||
#define MDM_NSTS_WIDTH ((u32)0x00000004)
|
||||
#define MDM_NSTS_WIDTH ((u32)0x00000004)
|
||||
/// NSS field mask
|
||||
#define MDM_NSS_MASK ((u32)0x00000F00)
|
||||
#define MDM_NSS_MASK ((u32)0x00000F00)
|
||||
/// NSS field LSB position
|
||||
#define MDM_NSS_LSB 8
|
||||
#define MDM_NSS_LSB 8
|
||||
/// NSS field width
|
||||
#define MDM_NSS_WIDTH ((u32)0x00000004)
|
||||
#define MDM_NSS_WIDTH ((u32)0x00000004)
|
||||
/// NTX field mask
|
||||
#define MDM_NTX_MASK ((u32)0x000000F0)
|
||||
#define MDM_NTX_MASK ((u32)0x000000F0)
|
||||
/// NTX field LSB position
|
||||
#define MDM_NTX_LSB 4
|
||||
#define MDM_NTX_LSB 4
|
||||
/// NTX field width
|
||||
#define MDM_NTX_WIDTH ((u32)0x00000004)
|
||||
#define MDM_NTX_WIDTH ((u32)0x00000004)
|
||||
/// NRX field mask
|
||||
#define MDM_NRX_MASK ((u32)0x0000000F)
|
||||
#define MDM_NRX_MASK ((u32)0x0000000F)
|
||||
/// NRX field LSB position
|
||||
#define MDM_NRX_LSB 0
|
||||
#define MDM_NRX_LSB 0
|
||||
/// NRX field width
|
||||
#define MDM_NRX_WIDTH ((u32)0x00000004)
|
||||
#define MDM_NRX_WIDTH ((u32)0x00000004)
|
||||
|
||||
#define __MDM_PHYCFG_FROM_VERS(v) (((v) & MDM_RFMODE_MASK) >> MDM_RFMODE_LSB)
|
||||
#define __MDM_PHYCFG_FROM_VERS(v) (((v)&MDM_RFMODE_MASK) >> MDM_RFMODE_LSB)
|
||||
|
||||
#define RIU_FCU_PRESENT_MASK ((u32)0xFF000000)
|
||||
#define RIU_FCU_PRESENT_LSB 24
|
||||
#define RIU_FCU_PRESENT_MASK ((u32)0xFF000000)
|
||||
#define RIU_FCU_PRESENT_LSB 24
|
||||
|
||||
#define __RIU_FCU_PRESENT(v) (((v) & RIU_FCU_PRESENT_MASK) >> RIU_FCU_PRESENT_LSB == 5)
|
||||
#define __RIU_FCU_PRESENT(v) \
|
||||
(((v)&RIU_FCU_PRESENT_MASK) >> RIU_FCU_PRESENT_LSB == 5)
|
||||
|
||||
/// AGC load version field mask
|
||||
#define RIU_AGC_LOAD_MASK ((u32)0x00C00000)
|
||||
#define RIU_AGC_LOAD_MASK ((u32)0x00C00000)
|
||||
/// AGC load version field LSB position
|
||||
#define RIU_AGC_LOAD_LSB 22
|
||||
#define RIU_AGC_LOAD_LSB 22
|
||||
|
||||
#define __RIU_AGCLOAD_FROM_VERS(v) (((v) & RIU_AGC_LOAD_MASK) >> RIU_AGC_LOAD_LSB)
|
||||
#define __RIU_AGCLOAD_FROM_VERS(v) (((v)&RIU_AGC_LOAD_MASK) >> RIU_AGC_LOAD_LSB)
|
||||
|
||||
#define __FPGA_TYPE(v) (((v) & 0xFFFF0000) >> 16)
|
||||
|
||||
#define __MDM_MAJOR_VERSION(v) (((v) & 0xFF000000) >> 24)
|
||||
#define __MDM_MINOR_VERSION(v) (((v) & 0x00FF0000) >> 16)
|
||||
#define __MDM_VERSION(v) ((__MDM_MAJOR_VERSION(v) + 2) * 10 + __MDM_MINOR_VERSION(v))
|
||||
#define __FPGA_TYPE(v) (((v)&0xFFFF0000) >> 16)
|
||||
|
||||
#define __MDM_MAJOR_VERSION(v) (((v)&0xFF000000) >> 24)
|
||||
#define __MDM_MINOR_VERSION(v) (((v)&0x00FF0000) >> 16)
|
||||
#define __MDM_VERSION(v) \
|
||||
((__MDM_MAJOR_VERSION(v) + 2) * 10 + __MDM_MINOR_VERSION(v))
|
||||
|
||||
#endif // _HAL_DESC_H_
|
||||
|
||||
@@ -15,11 +15,12 @@
|
||||
|
||||
#define __ALIGN4 __aligned(4)
|
||||
|
||||
#define ASSERT_ERR(condition) \
|
||||
do { \
|
||||
if (unlikely(!(condition))) { \
|
||||
printk(KERN_ERR "%s:%d:ASSERT_ERR(" #condition ")\n", __FILE__, __LINE__); \
|
||||
} \
|
||||
#define ASSERT_ERR(condition) \
|
||||
do { \
|
||||
if (unlikely(!(condition))) { \
|
||||
printk(KERN_ERR "%s:%d:ASSERT_ERR(" #condition ")\n", \
|
||||
__FILE__, __LINE__); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#endif /* _IPC_H_ */
|
||||
|
||||
@@ -30,13 +30,10 @@
|
||||
*/
|
||||
|
||||
const int nx_txdesc_cnt[] = {
|
||||
NX_TXDESC_CNT0,
|
||||
NX_TXDESC_CNT1,
|
||||
NX_TXDESC_CNT2,
|
||||
NX_TXDESC_CNT3,
|
||||
#if NX_TXQ_CNT == 5
|
||||
NX_TXDESC_CNT0, NX_TXDESC_CNT1, NX_TXDESC_CNT2, NX_TXDESC_CNT3,
|
||||
#if NX_TXQ_CNT == 5
|
||||
NX_TXDESC_CNT4,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
const int nx_txuser_cnt[] = {
|
||||
@@ -44,9 +41,7 @@ const int nx_txuser_cnt[] = {
|
||||
CONFIG_USER_MAX,
|
||||
CONFIG_USER_MAX,
|
||||
CONFIG_USER_MAX,
|
||||
#if NX_TXQ_CNT == 5
|
||||
#if NX_TXQ_CNT == 5
|
||||
1,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -57,15 +57,14 @@ struct ipc_host_cb_tag {
|
||||
|
||||
/// WLAN driver call-back function: sec_tbtt_ind
|
||||
void (*sec_tbtt_ind)(void *pthis);
|
||||
|
||||
};
|
||||
|
||||
/*
|
||||
* Struct used to store information about host buffers (DMA Address and local pointer)
|
||||
*/
|
||||
struct ipc_hostbuf {
|
||||
void *hostid; ///< ptr to hostbuf client (ipc_host client) structure
|
||||
uint32_t dma_addr; ///< ptr to real hostbuf dma address
|
||||
void *hostid; ///< ptr to hostbuf client (ipc_host client) structure
|
||||
uint32_t dma_addr; ///< ptr to real hostbuf dma address
|
||||
};
|
||||
|
||||
/// Definition of the IPC Host environment structure.
|
||||
@@ -76,14 +75,14 @@ struct ipc_host_env_tag {
|
||||
/// Pointer to the shared environment
|
||||
struct ipc_shared_env_tag *shared;
|
||||
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
// Array used to store the descriptor addresses
|
||||
struct ipc_hostbuf ipc_host_rxdesc_array[IPC_RXDESC_CNT];
|
||||
// Index of the host RX descriptor array (ipc_shared environment)
|
||||
uint8_t ipc_host_rxdesc_idx;
|
||||
/// Store the number of RX Descriptors
|
||||
uint8_t rxdesc_nb;
|
||||
#endif //(CONFIG_RWNX_FULLMAC)
|
||||
#endif //(CONFIG_RWNX_FULLMAC)
|
||||
|
||||
/// Fields for Data Rx handling
|
||||
// Index used for ipc_host_rxbuf_array to point to current buffer
|
||||
@@ -125,10 +124,10 @@ struct ipc_host_env_tag {
|
||||
void *tx_host_id2[CONFIG_USER_MAX][NX_TXDESC_CNT2];
|
||||
// Array storing the currently pushed host ids for the VO queue
|
||||
void *tx_host_id3[CONFIG_USER_MAX][NX_TXDESC_CNT3];
|
||||
#if NX_TXQ_CNT == 5
|
||||
#if NX_TXQ_CNT == 5
|
||||
// Array storing the currently pushed host ids for the BCN queue
|
||||
void *tx_host_id4[1][NX_TXDESC_CNT4];
|
||||
#endif
|
||||
#endif
|
||||
// Pointer to the different host ids arrays, per IPC queue
|
||||
void **tx_host_id[IPC_TXQUEUE_CNT][CONFIG_USER_MAX];
|
||||
// Pointer to the different TX descriptor arrays, per IPC queue
|
||||
|
||||
@@ -24,71 +24,72 @@
|
||||
* DEFINES AND MACROS
|
||||
****************************************************************************************
|
||||
*/
|
||||
#define CO_BIT(pos) (1U<<(pos))
|
||||
#define CO_BIT(pos) (1U << (pos))
|
||||
|
||||
#define IPC_TXQUEUE_CNT NX_TXQ_CNT
|
||||
#define NX_TXDESC_CNT0 8
|
||||
#define NX_TXDESC_CNT1 64
|
||||
#define NX_TXDESC_CNT2 64
|
||||
#define NX_TXDESC_CNT3 32
|
||||
#define IPC_TXQUEUE_CNT NX_TXQ_CNT
|
||||
#define NX_TXDESC_CNT0 8
|
||||
#define NX_TXDESC_CNT1 64
|
||||
#define NX_TXDESC_CNT2 64
|
||||
#define NX_TXDESC_CNT3 32
|
||||
#if NX_TXQ_CNT == 5
|
||||
#define NX_TXDESC_CNT4 8
|
||||
#define NX_TXDESC_CNT4 8
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Number of Host buffers available for Data Rx handling (through DMA)
|
||||
*/
|
||||
#define IPC_RXBUF_CNT 128
|
||||
#define IPC_RXBUF_CNT 128
|
||||
|
||||
/*
|
||||
* Number of shared descriptors available for Data RX handling
|
||||
*/
|
||||
#define IPC_RXDESC_CNT 128
|
||||
#define IPC_RXDESC_CNT 128
|
||||
|
||||
/*
|
||||
* Number of Host buffers available for Radar events handling (through DMA)
|
||||
*/
|
||||
#define IPC_RADARBUF_CNT 16
|
||||
#define IPC_RADARBUF_CNT 16
|
||||
|
||||
/*
|
||||
* Number of Host buffers available for unsupported Rx vectors handling (through DMA)
|
||||
*/
|
||||
#define IPC_UNSUPRXVECBUF_CNT 8
|
||||
#define IPC_UNSUPRXVECBUF_CNT 8
|
||||
|
||||
/*
|
||||
* Size of RxVector
|
||||
*/
|
||||
#define IPC_RXVEC_SIZE 16
|
||||
#define IPC_RXVEC_SIZE 16
|
||||
|
||||
/*
|
||||
* Number of Host buffers available for Emb->App MSGs sending (through DMA)
|
||||
*/
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
#define IPC_MSGE2A_BUF_CNT 64
|
||||
#define IPC_MSGE2A_BUF_CNT 64
|
||||
#endif
|
||||
/*
|
||||
* Number of Host buffers available for Debug Messages sending (through DMA)
|
||||
*/
|
||||
#define IPC_DBGBUF_CNT 32
|
||||
#define IPC_DBGBUF_CNT 32
|
||||
|
||||
/*
|
||||
* Length used in MSGs structures
|
||||
*/
|
||||
#define IPC_A2E_MSG_BUF_SIZE 127 // size in 4-byte words
|
||||
#define IPC_A2E_MSG_BUF_SIZE 127 // size in 4-byte words
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
#define IPC_E2A_MSG_SIZE_BASE 256 // size in 4-byte words
|
||||
#define IPC_E2A_MSG_SIZE_BASE 256 // size in 4-byte words
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RWNX_TL4
|
||||
#define IPC_E2A_MSG_PARAM_SIZE (IPC_E2A_MSG_SIZE_BASE + (IPC_E2A_MSG_SIZE_BASE / 2))
|
||||
#define IPC_E2A_MSG_PARAM_SIZE \
|
||||
(IPC_E2A_MSG_SIZE_BASE + (IPC_E2A_MSG_SIZE_BASE / 2))
|
||||
#else
|
||||
#define IPC_E2A_MSG_PARAM_SIZE IPC_E2A_MSG_SIZE_BASE
|
||||
#define IPC_E2A_MSG_PARAM_SIZE IPC_E2A_MSG_SIZE_BASE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Debug messages buffers size (in bytes)
|
||||
*/
|
||||
#define IPC_DBG_PARAM_SIZE 256
|
||||
#define IPC_DBG_PARAM_SIZE 256
|
||||
|
||||
/*
|
||||
* Define used for Rx hostbuf validity.
|
||||
@@ -111,21 +112,21 @@
|
||||
/*
|
||||
* Length of the receive vectors, in bytes
|
||||
*/
|
||||
#define DMA_HDR_PHYVECT_LEN 36
|
||||
#define DMA_HDR_PHYVECT_LEN 36
|
||||
|
||||
/*
|
||||
* Maximum number of payload addresses and lengths present in the descriptor
|
||||
*/
|
||||
#ifdef CONFIG_RWNX_SPLIT_TX_BUF
|
||||
#define NX_TX_PAYLOAD_MAX 6
|
||||
#define NX_TX_PAYLOAD_MAX 6
|
||||
#else
|
||||
#define NX_TX_PAYLOAD_MAX 1
|
||||
#define NX_TX_PAYLOAD_MAX 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Message struct/ID API version
|
||||
*/
|
||||
#define MSG_API_VER 33
|
||||
#define MSG_API_VER 33
|
||||
|
||||
/*
|
||||
****************************************************************************************
|
||||
@@ -139,7 +140,7 @@ struct hostdesc {
|
||||
u16_l packet_len;
|
||||
u16_l flags_ext;
|
||||
|
||||
u32_l hostid;
|
||||
u32_l hostid;
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
/// Address of the status descriptor in host memory (used for confirmation upload)
|
||||
//u32_l status_desc_addr;
|
||||
@@ -193,7 +194,6 @@ struct txdesc_api {
|
||||
struct hostdesc host;
|
||||
};
|
||||
|
||||
|
||||
struct txdesc_host {
|
||||
u32_l ready;
|
||||
|
||||
@@ -206,21 +206,21 @@ struct txdesc_host {
|
||||
struct dma_desc {
|
||||
/** Application subsystem address which is used as source address for DMA payload
|
||||
* transfer*/
|
||||
u32_l src;
|
||||
u32_l src;
|
||||
/** Points to the start of the embedded data buffer associated with this descriptor.
|
||||
* This address acts as the destination address for the DMA payload transfer*/
|
||||
u32_l dest;
|
||||
u32_l dest;
|
||||
/// Complete length of the buffer in memory
|
||||
u16_l length;
|
||||
u16_l length;
|
||||
/// Control word for the DMA engine (e.g. for interrupt generation)
|
||||
u16_l ctrl;
|
||||
u16_l ctrl;
|
||||
/// Pointer to the next element of the chained list
|
||||
u32_l next;
|
||||
u32_l next;
|
||||
};
|
||||
|
||||
// Comes from la.h
|
||||
/// Length of the configuration data of a logic analyzer
|
||||
#define LA_CONF_LEN 10
|
||||
#define LA_CONF_LEN 10
|
||||
|
||||
/// Structure containing the configuration data of a logic analyzer
|
||||
struct la_conf_tag {
|
||||
@@ -230,7 +230,7 @@ struct la_conf_tag {
|
||||
};
|
||||
|
||||
/// Size of a logic analyzer memory
|
||||
#define LA_MEM_LEN (1024 * 1024)
|
||||
#define LA_MEM_LEN (1024 * 1024)
|
||||
|
||||
/// Type of errors
|
||||
enum {
|
||||
@@ -241,25 +241,25 @@ enum {
|
||||
};
|
||||
|
||||
/// Maximum length of the SW diag trace
|
||||
#define DBG_SW_DIAG_MAX_LEN 1024
|
||||
#define DBG_SW_DIAG_MAX_LEN 1024
|
||||
|
||||
/// Maximum length of the error trace
|
||||
#define DBG_ERROR_TRACE_SIZE 256
|
||||
#define DBG_ERROR_TRACE_SIZE 256
|
||||
|
||||
/// Number of MAC diagnostic port banks
|
||||
#define DBG_DIAGS_MAC_MAX 48
|
||||
#define DBG_DIAGS_MAC_MAX 48
|
||||
|
||||
/// Number of PHY diagnostic port banks
|
||||
#define DBG_DIAGS_PHY_MAX 32
|
||||
#define DBG_DIAGS_PHY_MAX 32
|
||||
|
||||
/// Maximum size of the RX header descriptor information in the debug dump
|
||||
#define DBG_RHD_MEM_LEN (5 * 1024)
|
||||
#define DBG_RHD_MEM_LEN (5 * 1024)
|
||||
|
||||
/// Maximum size of the RX buffer descriptor information in the debug dump
|
||||
#define DBG_RBD_MEM_LEN (5 * 1024)
|
||||
#define DBG_RBD_MEM_LEN (5 * 1024)
|
||||
|
||||
/// Maximum size of the TX header descriptor information in the debug dump
|
||||
#define DBG_THD_MEM_LEN (10 * 1024)
|
||||
#define DBG_THD_MEM_LEN (10 * 1024)
|
||||
|
||||
/// Structure containing the information about the PHY channel that is used
|
||||
struct phy_channel_info {
|
||||
@@ -288,11 +288,11 @@ struct dbg_debug_info_tag {
|
||||
/// MAC HW diag configuration
|
||||
u32_l hw_diag;
|
||||
/// Error message
|
||||
u32_l error[DBG_ERROR_TRACE_SIZE/4];
|
||||
u32_l error[DBG_ERROR_TRACE_SIZE / 4];
|
||||
/// SW diag configuration length
|
||||
u32_l sw_diag_len;
|
||||
/// SW diag configuration
|
||||
u32_l sw_diag[DBG_SW_DIAG_MAX_LEN/4];
|
||||
u32_l sw_diag[DBG_SW_DIAG_MAX_LEN / 4];
|
||||
/// PHY channel information
|
||||
struct phy_channel_info chan_info;
|
||||
/// Embedded LA configuration
|
||||
@@ -313,21 +313,20 @@ struct dbg_debug_dump_tag {
|
||||
struct dbg_debug_info_tag dbg_info;
|
||||
|
||||
/// RX header descriptor memory
|
||||
u32_l rhd_mem[DBG_RHD_MEM_LEN/4];
|
||||
u32_l rhd_mem[DBG_RHD_MEM_LEN / 4];
|
||||
|
||||
/// RX buffer descriptor memory
|
||||
u32_l rbd_mem[DBG_RBD_MEM_LEN/4];
|
||||
u32_l rbd_mem[DBG_RBD_MEM_LEN / 4];
|
||||
|
||||
/// TX header descriptor memory
|
||||
u32_l thd_mem[NX_TXQ_CNT][DBG_THD_MEM_LEN/4];
|
||||
u32_l thd_mem[NX_TXQ_CNT][DBG_THD_MEM_LEN / 4];
|
||||
|
||||
/// Logic analyzer memory
|
||||
u32_l la_mem[LA_MEM_LEN/4];
|
||||
u32_l la_mem[LA_MEM_LEN / 4];
|
||||
};
|
||||
|
||||
|
||||
/// Number of pulses in a radar event structure
|
||||
#define RADAR_PULSE_MAX 4
|
||||
#define RADAR_PULSE_MAX 4
|
||||
|
||||
/// Definition of an array of radar pulses
|
||||
struct radar_pulse_array_desc {
|
||||
@@ -341,10 +340,10 @@ struct radar_pulse_array_desc {
|
||||
|
||||
/// Bit mapping inside a radar pulse element
|
||||
struct radar_pulse {
|
||||
s32_l freq:6; /** Freq (resolution is 2Mhz range is [-Fadc/4 .. Fadc/4]) */
|
||||
u32_l fom:4; /** Figure of Merit */
|
||||
u32_l len:6; /** Length of the current radar pulse (resolution is 2us) */
|
||||
u32_l rep:16; /** Time interval between the previous radar event
|
||||
s32_l freq : 6; /** Freq (resolution is 2Mhz range is [-Fadc/4 .. Fadc/4]) */
|
||||
u32_l fom : 4; /** Figure of Merit */
|
||||
u32_l len : 6; /** Length of the current radar pulse (resolution is 2us) */
|
||||
u32_l rep : 16; /** Time interval between the previous radar event
|
||||
and the current one (in us) */
|
||||
};
|
||||
|
||||
@@ -354,7 +353,7 @@ struct rx_vector_desc {
|
||||
struct phy_channel_info phy_info;
|
||||
|
||||
/// RX vector 1
|
||||
u32_l rx_vect1[IPC_RXVEC_SIZE/4];
|
||||
u32_l rx_vect1[IPC_RXVEC_SIZE / 4];
|
||||
|
||||
/// Used to print a valid rx vector
|
||||
u32_l pattern;
|
||||
@@ -384,7 +383,6 @@ struct rxdesc_tag {
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @addtogroup IPC_TX IPC Tx path
|
||||
@@ -477,8 +475,6 @@ struct rxdesc_tag {
|
||||
|
||||
/// @} IPC_RX
|
||||
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @defgroup IPC_MISC IPC Misc
|
||||
@@ -503,24 +499,24 @@ struct ipc_msg_elt {
|
||||
|
||||
/// Message structure for MSGs from Emb to App
|
||||
struct ipc_e2a_msg {
|
||||
u16_l id; ///< Message id.
|
||||
u16_l id; ///< Message id.
|
||||
u16_l dummy_dest_id;
|
||||
u16_l dummy_src_id;
|
||||
u16_l param_len; ///< Parameter embedded struct length.
|
||||
u32_l pattern; ///< Used to stamp a valid MSG buffer
|
||||
u32_l param[IPC_E2A_MSG_PARAM_SIZE]; ///< Parameter embedded struct. Must be word-aligned.
|
||||
u16_l param_len; ///< Parameter embedded struct length.
|
||||
u32_l pattern; ///< Used to stamp a valid MSG buffer
|
||||
u32_l param[IPC_E2A_MSG_PARAM_SIZE]; ///< Parameter embedded struct. Must be word-aligned.
|
||||
};
|
||||
|
||||
/// Message structure for Debug messages from Emb to App
|
||||
struct ipc_dbg_msg {
|
||||
u32_l string[IPC_DBG_PARAM_SIZE/4]; ///< Debug string
|
||||
u32_l pattern; ///< Used to stamp a valid buffer
|
||||
u32_l string[IPC_DBG_PARAM_SIZE / 4]; ///< Debug string
|
||||
u32_l pattern; ///< Used to stamp a valid buffer
|
||||
};
|
||||
|
||||
/// Message structure for MSGs from App to Emb.
|
||||
/// Actually a sub-structure will be used when filling the messages.
|
||||
struct ipc_a2e_msg {
|
||||
u32_l dummy_word; // used to cope with kernel message structure
|
||||
u32_l dummy_word; // used to cope with kernel message structure
|
||||
u32_l msg[IPC_A2E_MSG_BUF_SIZE]; // body of the msg
|
||||
};
|
||||
|
||||
@@ -573,42 +569,51 @@ struct compatibility_tag {
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
// Indexes are defined in the MIB shared structure
|
||||
struct ipc_shared_env_tag {
|
||||
volatile struct compatibility_tag comp_info; //FW characteristics
|
||||
|
||||
volatile struct ipc_a2e_msg msg_a2e_buf; // room for MSG to be sent from App to Emb
|
||||
volatile struct ipc_a2e_msg
|
||||
msg_a2e_buf; // room for MSG to be sent from App to Emb
|
||||
|
||||
// Fields for MSGs sending from Emb to App
|
||||
volatile struct ipc_e2a_msg msg_e2a_buf; // room to build the MSG to be DMA Xferred
|
||||
volatile struct dma_desc msg_dma_desc; // DMA descriptor for Emb->App MSGs Xfers
|
||||
volatile u32_l msg_e2a_hostbuf_addr[IPC_MSGE2A_BUF_CNT]; // buffers @ for DMA Xfers
|
||||
volatile struct ipc_e2a_msg
|
||||
msg_e2a_buf; // room to build the MSG to be DMA Xferred
|
||||
volatile struct dma_desc
|
||||
msg_dma_desc; // DMA descriptor for Emb->App MSGs Xfers
|
||||
volatile u32_l msg_e2a_hostbuf_addr
|
||||
[IPC_MSGE2A_BUF_CNT]; // buffers @ for DMA Xfers
|
||||
|
||||
// Fields for Debug MSGs sending from Emb to App
|
||||
volatile struct ipc_dbg_msg dbg_buf; // room to build the MSG to be DMA Xferred
|
||||
volatile struct dma_desc dbg_dma_desc; // DMA descriptor for Emb->App MSGs Xfers
|
||||
volatile u32_l dbg_hostbuf_addr[IPC_DBGBUF_CNT]; // buffers @ for MSGs DMA Xfers
|
||||
volatile u32_l la_dbginfo_addr; // Host buffer address for the debug information
|
||||
volatile u32_l pattern_addr;
|
||||
volatile u32_l radarbuf_hostbuf[IPC_RADARBUF_CNT]; // buffers @ for Radar Events
|
||||
volatile u32_l unsuprxvecbuf_hostbuf[IPC_UNSUPRXVECBUF_CNT]; // buffers @ for unsupported Rx vectors
|
||||
volatile struct ipc_dbg_msg
|
||||
dbg_buf; // room to build the MSG to be DMA Xferred
|
||||
volatile struct dma_desc
|
||||
dbg_dma_desc; // DMA descriptor for Emb->App MSGs Xfers
|
||||
volatile u32_l
|
||||
dbg_hostbuf_addr[IPC_DBGBUF_CNT]; // buffers @ for MSGs DMA Xfers
|
||||
volatile u32_l
|
||||
la_dbginfo_addr; // Host buffer address for the debug information
|
||||
volatile u32_l pattern_addr;
|
||||
volatile u32_l
|
||||
radarbuf_hostbuf[IPC_RADARBUF_CNT]; // buffers @ for Radar Events
|
||||
volatile u32_l unsuprxvecbuf_hostbuf
|
||||
[IPC_UNSUPRXVECBUF_CNT]; // buffers @ for unsupported Rx vectors
|
||||
volatile struct txdesc_host txdesc0[CONFIG_USER_MAX][NX_TXDESC_CNT0];
|
||||
volatile struct txdesc_host txdesc1[CONFIG_USER_MAX][NX_TXDESC_CNT1];
|
||||
volatile struct txdesc_host txdesc2[CONFIG_USER_MAX][NX_TXDESC_CNT2];
|
||||
volatile struct txdesc_host txdesc3[CONFIG_USER_MAX][NX_TXDESC_CNT3];
|
||||
#if NX_TXQ_CNT == 5
|
||||
#if NX_TXQ_CNT == 5
|
||||
volatile struct txdesc_host txdesc4[1][NX_TXDESC_CNT4];
|
||||
#endif
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
#endif
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
// RX Descriptors Array
|
||||
volatile struct ipc_shared_rx_desc host_rxdesc[IPC_RXDESC_CNT];
|
||||
// RX Buffers Array
|
||||
volatile struct ipc_shared_rx_buf host_rxbuf[IPC_RXBUF_CNT];
|
||||
#else
|
||||
volatile struct ipc_shared_rx_buf host_rxbuf[IPC_RXBUF_CNT];
|
||||
#else
|
||||
// buffers @ for Data Rx
|
||||
volatile u32_l host_rxbuf[IPC_RXBUF_CNT];
|
||||
#endif /* CONFIG_RWNX_FULLMAC */
|
||||
#endif /* CONFIG_RWNX_FULLMAC */
|
||||
|
||||
u32_l buffered[NX_REMOTE_STA_MAX][TID_MAX];
|
||||
|
||||
@@ -623,7 +628,6 @@ struct ipc_shared_env_tag {
|
||||
|
||||
extern struct ipc_shared_env_tag ipc_shared_env;
|
||||
|
||||
|
||||
/*
|
||||
* TYPE and STRUCT DEFINITIONS
|
||||
****************************************************************************************
|
||||
@@ -637,62 +641,63 @@ extern struct ipc_shared_env_tag ipc_shared_env;
|
||||
#endif
|
||||
/// Interrupts bits used
|
||||
#if CONFIG_USER_MAX > 3
|
||||
#define IPC_IRQ_A2E_USER_MSK 0xF
|
||||
#define IPC_IRQ_A2E_USER_MSK 0xF
|
||||
#elif CONFIG_USER_MAX > 2
|
||||
#define IPC_IRQ_A2E_USER_MSK 0x7
|
||||
#define IPC_IRQ_A2E_USER_MSK 0x7
|
||||
#else
|
||||
#define IPC_IRQ_A2E_USER_MSK 0x3
|
||||
#define IPC_IRQ_A2E_USER_MSK 0x3
|
||||
#endif
|
||||
|
||||
/// Offset of the interrupts for AC0
|
||||
#define IPC_IRQ_A2E_AC0_OFT 8
|
||||
#define IPC_IRQ_A2E_AC0_OFT 8
|
||||
/// Mask of the interrupts for AC0
|
||||
#define IPC_IRQ_A2E_AC0_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC0_OFT)
|
||||
#define IPC_IRQ_A2E_AC0_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC0_OFT)
|
||||
/// Offset of the interrupts for AC1
|
||||
#define IPC_IRQ_A2E_AC1_OFT (IPC_IRQ_A2E_AC0_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_A2E_AC1_OFT (IPC_IRQ_A2E_AC0_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for AC1
|
||||
#define IPC_IRQ_A2E_AC1_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC1_OFT)
|
||||
#define IPC_IRQ_A2E_AC1_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC1_OFT)
|
||||
/// Offset of the interrupts for AC2
|
||||
#define IPC_IRQ_A2E_AC2_OFT (IPC_IRQ_A2E_AC1_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_A2E_AC2_OFT (IPC_IRQ_A2E_AC1_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for AC2
|
||||
#define IPC_IRQ_A2E_AC2_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC2_OFT)
|
||||
#define IPC_IRQ_A2E_AC2_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC2_OFT)
|
||||
/// Offset of the interrupts for AC3
|
||||
#define IPC_IRQ_A2E_AC3_OFT (IPC_IRQ_A2E_AC2_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_A2E_AC3_OFT (IPC_IRQ_A2E_AC2_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for AC3
|
||||
#define IPC_IRQ_A2E_AC3_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC3_OFT)
|
||||
#define IPC_IRQ_A2E_AC3_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC3_OFT)
|
||||
/// Offset of the interrupts for BCN
|
||||
#define IPC_IRQ_A2E_BCN_OFT (IPC_IRQ_A2E_AC3_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_A2E_BCN_OFT (IPC_IRQ_A2E_AC3_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for BCN
|
||||
#define IPC_IRQ_A2E_BCN_MSK CO_BIT(IPC_IRQ_A2E_BCN_OFT)
|
||||
#define IPC_IRQ_A2E_BCN_MSK CO_BIT(IPC_IRQ_A2E_BCN_OFT)
|
||||
|
||||
#define IPC_IRQ_A2E_AC_TXDESC (IPC_IRQ_A2E_AC0_MSK | IPC_IRQ_A2E_AC1_MSK | \
|
||||
IPC_IRQ_A2E_AC2_MSK | IPC_IRQ_A2E_AC3_MSK)
|
||||
#define IPC_IRQ_A2E_AC_TXDESC \
|
||||
(IPC_IRQ_A2E_AC0_MSK | IPC_IRQ_A2E_AC1_MSK | IPC_IRQ_A2E_AC2_MSK | \
|
||||
IPC_IRQ_A2E_AC3_MSK)
|
||||
|
||||
/// Interrupts bits used for the TX descriptors of the BCN queue
|
||||
#if NX_TXQ_CNT < 5
|
||||
#define IPC_IRQ_A2E_BCN_TXDESC 0
|
||||
#define IPC_IRQ_A2E_BCN_TXDESC 0
|
||||
#else
|
||||
#define IPC_IRQ_A2E_BCN_TXDESC (0x01 << IPC_IRQ_A2E_BCN_OFT)
|
||||
#define IPC_IRQ_A2E_BCN_TXDESC (0x01 << IPC_IRQ_A2E_BCN_OFT)
|
||||
#endif
|
||||
|
||||
/// IPC TX descriptor interrupt mask
|
||||
#define IPC_IRQ_A2E_TXDESC (IPC_IRQ_A2E_AC_TXDESC | IPC_IRQ_A2E_BCN_TXDESC)
|
||||
#define IPC_IRQ_A2E_TXDESC (IPC_IRQ_A2E_AC_TXDESC | IPC_IRQ_A2E_BCN_TXDESC)
|
||||
#else
|
||||
/// IPC TX descriptor interrupt mask
|
||||
#define IPC_IRQ_A2E_TXDESC 0xFF00
|
||||
#define IPC_IRQ_A2E_TXDESC 0xFF00
|
||||
#endif
|
||||
|
||||
#define IPC_IRQ_A2E_TXDESC_FIRSTBIT (8)
|
||||
#define IPC_IRQ_A2E_RXBUF_BACK CO_BIT(5)
|
||||
#define IPC_IRQ_A2E_RXDESC_BACK CO_BIT(4)
|
||||
#define IPC_IRQ_A2E_RXBUF_BACK CO_BIT(5)
|
||||
#define IPC_IRQ_A2E_RXDESC_BACK CO_BIT(4)
|
||||
|
||||
#define IPC_IRQ_A2E_MSG CO_BIT(1)
|
||||
#define IPC_IRQ_A2E_DBG CO_BIT(0)
|
||||
#define IPC_IRQ_A2E_MSG CO_BIT(1)
|
||||
#define IPC_IRQ_A2E_DBG CO_BIT(0)
|
||||
|
||||
#define IPC_IRQ_A2E_ALL (IPC_IRQ_A2E_TXDESC|IPC_IRQ_A2E_MSG|IPC_IRQ_A2E_DBG)
|
||||
#define IPC_IRQ_A2E_ALL (IPC_IRQ_A2E_TXDESC | IPC_IRQ_A2E_MSG | IPC_IRQ_A2E_DBG)
|
||||
|
||||
// IRQs from emb to app
|
||||
#define IPC_IRQ_E2A_TXCFM_POS 7
|
||||
#define IPC_IRQ_E2A_TXCFM_POS 7
|
||||
|
||||
#ifdef CONFIG_RWNX_MUMIMO_TX
|
||||
#ifdef CONFIG_RWNX_OLD_IPC
|
||||
@@ -700,76 +705,71 @@ extern struct ipc_shared_env_tag ipc_shared_env;
|
||||
#endif
|
||||
/// Interrupts bits used
|
||||
#if CONFIG_USER_MAX > 3
|
||||
#define IPC_IRQ_E2A_USER_MSK 0xF
|
||||
#define IPC_IRQ_E2A_USER_MSK 0xF
|
||||
#elif CONFIG_USER_MAX > 2
|
||||
#define IPC_IRQ_E2A_USER_MSK 0x7
|
||||
#define IPC_IRQ_E2A_USER_MSK 0x7
|
||||
#else
|
||||
#define IPC_IRQ_E2A_USER_MSK 0x3
|
||||
#define IPC_IRQ_E2A_USER_MSK 0x3
|
||||
#endif
|
||||
|
||||
/// Offset of the interrupts for AC0
|
||||
#define IPC_IRQ_E2A_AC0_OFT IPC_IRQ_E2A_TXCFM_POS
|
||||
#define IPC_IRQ_E2A_AC0_OFT IPC_IRQ_E2A_TXCFM_POS
|
||||
/// Mask of the interrupts for AC0
|
||||
#define IPC_IRQ_E2A_AC0_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC0_OFT)
|
||||
#define IPC_IRQ_E2A_AC0_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC0_OFT)
|
||||
/// Offset of the interrupts for AC1
|
||||
#define IPC_IRQ_E2A_AC1_OFT (IPC_IRQ_E2A_AC0_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_E2A_AC1_OFT (IPC_IRQ_E2A_AC0_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for AC1
|
||||
#define IPC_IRQ_E2A_AC1_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC1_OFT)
|
||||
#define IPC_IRQ_E2A_AC1_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC1_OFT)
|
||||
/// Offset of the interrupts for AC2
|
||||
#define IPC_IRQ_E2A_AC2_OFT (IPC_IRQ_E2A_AC1_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_E2A_AC2_OFT (IPC_IRQ_E2A_AC1_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for AC2
|
||||
#define IPC_IRQ_E2A_AC2_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC2_OFT)
|
||||
#define IPC_IRQ_E2A_AC2_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC2_OFT)
|
||||
/// Offset of the interrupts for AC3
|
||||
#define IPC_IRQ_E2A_AC3_OFT (IPC_IRQ_E2A_AC2_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_E2A_AC3_OFT (IPC_IRQ_E2A_AC2_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for AC3
|
||||
#define IPC_IRQ_E2A_AC3_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC3_OFT)
|
||||
#define IPC_IRQ_E2A_AC3_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC3_OFT)
|
||||
/// Offset of the interrupts for BCN
|
||||
#define IPC_IRQ_E2A_BCN_OFT (IPC_IRQ_E2A_AC3_OFT + CONFIG_USER_MAX)
|
||||
#define IPC_IRQ_E2A_BCN_OFT (IPC_IRQ_E2A_AC3_OFT + CONFIG_USER_MAX)
|
||||
/// Mask of the interrupts for BCN
|
||||
#define IPC_IRQ_E2A_BCN_MSK CO_BIT(IPC_IRQ_E2A_BCN_OFT)
|
||||
#define IPC_IRQ_E2A_BCN_MSK CO_BIT(IPC_IRQ_E2A_BCN_OFT)
|
||||
|
||||
#define IPC_IRQ_E2A_AC_TXCFM (IPC_IRQ_E2A_AC0_MSK | IPC_IRQ_E2A_AC1_MSK | \
|
||||
IPC_IRQ_E2A_AC2_MSK | IPC_IRQ_E2A_AC3_MSK)
|
||||
#define IPC_IRQ_E2A_AC_TXCFM \
|
||||
(IPC_IRQ_E2A_AC0_MSK | IPC_IRQ_E2A_AC1_MSK | IPC_IRQ_E2A_AC2_MSK | \
|
||||
IPC_IRQ_E2A_AC3_MSK)
|
||||
|
||||
/// Interrupts bits used for the TX descriptors of the BCN queue
|
||||
#if NX_TXQ_CNT < 5
|
||||
#define IPC_IRQ_E2A_BCN_TXCFM 0
|
||||
#define IPC_IRQ_E2A_BCN_TXCFM 0
|
||||
#else
|
||||
#define IPC_IRQ_E2A_BCN_TXCFM (0x01 << IPC_IRQ_E2A_BCN_OFT)
|
||||
#define IPC_IRQ_E2A_BCN_TXCFM (0x01 << IPC_IRQ_E2A_BCN_OFT)
|
||||
#endif
|
||||
|
||||
/// IPC TX descriptor interrupt mask
|
||||
#define IPC_IRQ_E2A_TXCFM (IPC_IRQ_E2A_AC_TXCFM | IPC_IRQ_E2A_BCN_TXCFM)
|
||||
#define IPC_IRQ_E2A_TXCFM (IPC_IRQ_E2A_AC_TXCFM | IPC_IRQ_E2A_BCN_TXCFM)
|
||||
|
||||
#else
|
||||
|
||||
#define IPC_IRQ_E2A_TXCFM (((1 << NX_TXQ_CNT) - 1) << IPC_IRQ_E2A_TXCFM_POS)
|
||||
#define IPC_IRQ_E2A_TXCFM (((1 << NX_TXQ_CNT) - 1) << IPC_IRQ_E2A_TXCFM_POS)
|
||||
|
||||
#endif /* CONFIG_RWNX_MUMIMO_TX */
|
||||
|
||||
#define IPC_IRQ_E2A_UNSUP_RX_VEC CO_BIT(7)
|
||||
#define IPC_IRQ_E2A_RADAR CO_BIT(6)
|
||||
#define IPC_IRQ_E2A_TBTT_SEC CO_BIT(5)
|
||||
#define IPC_IRQ_E2A_TBTT_PRIM CO_BIT(4)
|
||||
#define IPC_IRQ_E2A_RXDESC CO_BIT(3)
|
||||
#define IPC_IRQ_E2A_MSG_ACK CO_BIT(2)
|
||||
#define IPC_IRQ_E2A_MSG CO_BIT(1)
|
||||
#define IPC_IRQ_E2A_DBG CO_BIT(0)
|
||||
#define IPC_IRQ_E2A_UNSUP_RX_VEC CO_BIT(7)
|
||||
#define IPC_IRQ_E2A_RADAR CO_BIT(6)
|
||||
#define IPC_IRQ_E2A_TBTT_SEC CO_BIT(5)
|
||||
#define IPC_IRQ_E2A_TBTT_PRIM CO_BIT(4)
|
||||
#define IPC_IRQ_E2A_RXDESC CO_BIT(3)
|
||||
#define IPC_IRQ_E2A_MSG_ACK CO_BIT(2)
|
||||
#define IPC_IRQ_E2A_MSG CO_BIT(1)
|
||||
#define IPC_IRQ_E2A_DBG CO_BIT(0)
|
||||
|
||||
#define IPC_IRQ_E2A_ALL (IPC_IRQ_E2A_TXCFM \
|
||||
| IPC_IRQ_E2A_RXDESC \
|
||||
| IPC_IRQ_E2A_MSG_ACK \
|
||||
| IPC_IRQ_E2A_MSG \
|
||||
| IPC_IRQ_E2A_DBG \
|
||||
| IPC_IRQ_E2A_TBTT_PRIM \
|
||||
| IPC_IRQ_E2A_TBTT_SEC \
|
||||
| IPC_IRQ_E2A_RADAR \
|
||||
| IPC_IRQ_E2A_UNSUP_RX_VEC)
|
||||
#define IPC_IRQ_E2A_ALL \
|
||||
(IPC_IRQ_E2A_TXCFM | IPC_IRQ_E2A_RXDESC | IPC_IRQ_E2A_MSG_ACK | \
|
||||
IPC_IRQ_E2A_MSG | IPC_IRQ_E2A_DBG | IPC_IRQ_E2A_TBTT_PRIM | \
|
||||
IPC_IRQ_E2A_TBTT_SEC | IPC_IRQ_E2A_RADAR | IPC_IRQ_E2A_UNSUP_RX_VEC)
|
||||
|
||||
// FLAGS for RX desc
|
||||
#define IPC_RX_FORWARD CO_BIT(1)
|
||||
#define IPC_RX_INTRABSS CO_BIT(0)
|
||||
|
||||
#define IPC_RX_FORWARD CO_BIT(1)
|
||||
#define IPC_RX_INTRABSS CO_BIT(0)
|
||||
|
||||
// IPC message TYPE
|
||||
enum {
|
||||
@@ -782,4 +782,3 @@ enum {
|
||||
};
|
||||
|
||||
#endif // _IPC_SHARED_H_
|
||||
|
||||
|
||||
@@ -42,7 +42,7 @@ enum mac_vif_type {
|
||||
/// MAC address structure.
|
||||
struct mac_addr {
|
||||
/// Array of 16-bit words that make up the MAC address.
|
||||
u16_l array[MAC_ADDR_LEN/2];
|
||||
u16_l array[MAC_ADDR_LEN / 2];
|
||||
};
|
||||
|
||||
/// SSID maximum length.
|
||||
@@ -241,29 +241,29 @@ struct mac_scan_result {
|
||||
/// Legacy rate 802.11 definitions
|
||||
enum mac_legacy_rates {
|
||||
/// DSSS/CCK 1Mbps
|
||||
MAC_RATE_1MBPS = 2,
|
||||
MAC_RATE_1MBPS = 2,
|
||||
/// DSSS/CCK 2Mbps
|
||||
MAC_RATE_2MBPS = 4,
|
||||
MAC_RATE_2MBPS = 4,
|
||||
/// DSSS/CCK 5.5Mbps
|
||||
MAC_RATE_5_5MBPS = 11,
|
||||
MAC_RATE_5_5MBPS = 11,
|
||||
/// OFDM 6Mbps
|
||||
MAC_RATE_6MBPS = 12,
|
||||
MAC_RATE_6MBPS = 12,
|
||||
/// OFDM 9Mbps
|
||||
MAC_RATE_9MBPS = 18,
|
||||
MAC_RATE_9MBPS = 18,
|
||||
/// DSSS/CCK 11Mbps
|
||||
MAC_RATE_11MBPS = 22,
|
||||
MAC_RATE_11MBPS = 22,
|
||||
/// OFDM 12Mbps
|
||||
MAC_RATE_12MBPS = 24,
|
||||
MAC_RATE_12MBPS = 24,
|
||||
/// OFDM 18Mbps
|
||||
MAC_RATE_18MBPS = 36,
|
||||
MAC_RATE_18MBPS = 36,
|
||||
/// OFDM 24Mbps
|
||||
MAC_RATE_24MBPS = 48,
|
||||
MAC_RATE_24MBPS = 48,
|
||||
/// OFDM 36Mbps
|
||||
MAC_RATE_36MBPS = 72,
|
||||
MAC_RATE_36MBPS = 72,
|
||||
/// OFDM 48Mbps
|
||||
MAC_RATE_48MBPS = 96,
|
||||
MAC_RATE_48MBPS = 96,
|
||||
/// OFDM 54Mbps
|
||||
MAC_RATE_54MBPS = 108
|
||||
MAC_RATE_54MBPS = 108
|
||||
};
|
||||
|
||||
/// BSS Membership Selector definitions
|
||||
@@ -286,14 +286,14 @@ struct mac_rateset {
|
||||
};
|
||||
|
||||
/// MAC Security Key maximum length
|
||||
#define MAC_SEC_KEY_LEN 32 // TKIP keys 256 bits (max length) with MIC keys
|
||||
#define MAC_SEC_KEY_LEN 32 // TKIP keys 256 bits (max length) with MIC keys
|
||||
|
||||
/// Structure defining a security key
|
||||
struct mac_sec_key {
|
||||
/// Key material length
|
||||
u8_l length;
|
||||
/// Key material
|
||||
u32_l array[MAC_SEC_KEY_LEN/4];
|
||||
u32_l array[MAC_SEC_KEY_LEN / 4];
|
||||
};
|
||||
|
||||
/// Access Category enumeration
|
||||
@@ -435,38 +435,38 @@ enum mac_connection_flags {
|
||||
};
|
||||
|
||||
#ifdef CONFIG_HE_FOR_OLD_KERNEL
|
||||
#define IEEE80211_HE_MAC_CAP2_ALL_ACK 0x02
|
||||
#define IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G 0x02
|
||||
#define IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G 0x04
|
||||
#define IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD 0x20
|
||||
#define IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US 0x40
|
||||
#define IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS 0x80
|
||||
#define IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS 0x01
|
||||
#define IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US 0x02
|
||||
#define IEEE80211_HE_PHY_CAP2_DOPPLER_RX 0x20
|
||||
#define IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ 0x08
|
||||
#define IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM 0x18
|
||||
#define IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1 0x00
|
||||
#define IEEE80211_HE_PHY_CAP3_RX_HE_MU_PPDU_FROM_NON_AP_STA 0x40
|
||||
#define IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE 0x01
|
||||
#define IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 0x0c
|
||||
#define IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK 0x40
|
||||
#define IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK 0x80
|
||||
#define IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU 0x01
|
||||
#define IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU 0x02
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB 0x04
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB 0x08
|
||||
#define IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT 0x80
|
||||
#define IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO 0x40
|
||||
#define IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI 0x04
|
||||
#define IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G 0x02
|
||||
#define IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB 0x10
|
||||
#define IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB 0x20
|
||||
#define IEEE80211_HE_MAC_CAP2_ALL_ACK 0x02
|
||||
#define IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G 0x02
|
||||
#define IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G 0x04
|
||||
#define IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD 0x20
|
||||
#define IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US 0x40
|
||||
#define IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS 0x80
|
||||
#define IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS 0x01
|
||||
#define IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US 0x02
|
||||
#define IEEE80211_HE_PHY_CAP2_DOPPLER_RX 0x20
|
||||
#define IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ 0x08
|
||||
#define IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM 0x18
|
||||
#define IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1 0x00
|
||||
#define IEEE80211_HE_PHY_CAP3_RX_HE_MU_PPDU_FROM_NON_AP_STA 0x40
|
||||
#define IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE 0x01
|
||||
#define IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 0x0c
|
||||
#define IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK 0x40
|
||||
#define IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK 0x80
|
||||
#define IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU 0x01
|
||||
#define IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU 0x02
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB 0x04
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB 0x08
|
||||
#define IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT 0x80
|
||||
#define IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO 0x40
|
||||
#define IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI 0x04
|
||||
#define IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G 0x02
|
||||
#define IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB 0x10
|
||||
#define IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB 0x20
|
||||
|
||||
#define IEEE80211_HE_PPE_THRES_MAX_LEN 25
|
||||
#define IEEE80211_HE_PPE_THRES_MAX_LEN 25
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)
|
||||
#define WLAN_EID_EXTENSION 255
|
||||
#define WLAN_EID_EXTENSION 255
|
||||
/* Element ID Extensions for Element ID 255 */
|
||||
|
||||
enum ieee80211_eid_ext {
|
||||
@@ -487,30 +487,29 @@ enum ieee80211_eid_ext {
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)
|
||||
#define WLAN_EID_EXT_HE_CAPABILITY 35
|
||||
#define WLAN_EID_EXT_HE_OPERATION 36
|
||||
#define WLAN_EID_EXT_UORA 37
|
||||
#define WLAN_EID_EXT_HE_MU_EDCA 38
|
||||
#define WLAN_EID_EXT_HE_SPR 39
|
||||
#define WLAN_EID_EXT_NDP_FEEDBACK_REPORT_PARAMSET 41
|
||||
#define WLAN_EID_EXT_BSS_COLOR_CHG_ANN 42
|
||||
#define WLAN_EID_EXT_QUIET_TIME_PERIOD_SETUP 43
|
||||
#define WLAN_EID_EXT_ESS_REPORT 45
|
||||
#define WLAN_EID_EXT_OPS 46
|
||||
#define WLAN_EID_EXT_HE_BSS_LOAD 47
|
||||
#define WLAN_EID_EXT_MAX_CHANNEL_SWITCH_TIME 52
|
||||
#define WLAN_EID_EXT_MULTIPLE_BSSID_CONFIGURATION 55
|
||||
#define WLAN_EID_EXT_NON_INHERITANCE 56
|
||||
#define WLAN_EID_EXT_KNOWN_BSSID 57
|
||||
#define WLAN_EID_EXT_SHORT_SSID_LIST 58
|
||||
#define WLAN_EID_EXT_HE_6GHZ_CAPA 59
|
||||
#define WLAN_EID_EXT_UL_MU_POWER_CAPA 60
|
||||
#define WLAN_EID_EXT_EHT_OPERATION 106
|
||||
#define WLAN_EID_EXT_EHT_MULTI_LINK 107
|
||||
#define WLAN_EID_EXT_EHT_CAPABILITY 108
|
||||
#define WLAN_EID_EXT_HE_CAPABILITY 35
|
||||
#define WLAN_EID_EXT_HE_OPERATION 36
|
||||
#define WLAN_EID_EXT_UORA 37
|
||||
#define WLAN_EID_EXT_HE_MU_EDCA 38
|
||||
#define WLAN_EID_EXT_HE_SPR 39
|
||||
#define WLAN_EID_EXT_NDP_FEEDBACK_REPORT_PARAMSET 41
|
||||
#define WLAN_EID_EXT_BSS_COLOR_CHG_ANN 42
|
||||
#define WLAN_EID_EXT_QUIET_TIME_PERIOD_SETUP 43
|
||||
#define WLAN_EID_EXT_ESS_REPORT 45
|
||||
#define WLAN_EID_EXT_OPS 46
|
||||
#define WLAN_EID_EXT_HE_BSS_LOAD 47
|
||||
#define WLAN_EID_EXT_MAX_CHANNEL_SWITCH_TIME 52
|
||||
#define WLAN_EID_EXT_MULTIPLE_BSSID_CONFIGURATION 55
|
||||
#define WLAN_EID_EXT_NON_INHERITANCE 56
|
||||
#define WLAN_EID_EXT_KNOWN_BSSID 57
|
||||
#define WLAN_EID_EXT_SHORT_SSID_LIST 58
|
||||
#define WLAN_EID_EXT_HE_6GHZ_CAPA 59
|
||||
#define WLAN_EID_EXT_UL_MU_POWER_CAPA 60
|
||||
#define WLAN_EID_EXT_EHT_OPERATION 106
|
||||
#define WLAN_EID_EXT_EHT_MULTI_LINK 107
|
||||
#define WLAN_EID_EXT_EHT_CAPABILITY 108
|
||||
#endif
|
||||
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)
|
||||
#include <linux/ieee80211.h>
|
||||
#else
|
||||
@@ -541,7 +540,8 @@ struct ieee80211_sband_iftype_data {
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0) || defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0) || \
|
||||
defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
struct ieee80211_vht_mcs_info {
|
||||
__le16 rx_mcs_map;
|
||||
__le16 rx_highest;
|
||||
@@ -553,7 +553,7 @@ struct ieee80211_vht_cap {
|
||||
__le32 vht_cap_info;
|
||||
struct ieee80211_vht_mcs_info supp_mcs;
|
||||
};
|
||||
#define WLAN_EID_VHT_CAPABILITY 191
|
||||
#define WLAN_EID_VHT_CAPABILITY 191
|
||||
|
||||
struct ieee80211_sta_vht_cap {
|
||||
bool vht_supported;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -16,7 +16,6 @@
|
||||
#ifndef _LMAC_INT_H_
|
||||
#define _LMAC_INT_H_
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @addtogroup CO_INT
|
||||
@@ -27,7 +26,6 @@
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* DEFINES
|
||||
****************************************************************************************
|
||||
@@ -56,7 +54,5 @@ typedef uint32_t u32_l;
|
||||
typedef int32_t s32_l;
|
||||
typedef uint64_t u64_l;
|
||||
|
||||
|
||||
|
||||
/// @} CO_INT
|
||||
#endif // _LMAC_INT_H_
|
||||
|
||||
@@ -1,161 +1,154 @@
|
||||
#include <linux/memory.h>
|
||||
#include "md5.h"
|
||||
|
||||
unsigned char PADDING[]={0x80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
|
||||
|
||||
unsigned char PADDING[] = { 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
|
||||
|
||||
void MD5Init(MD5_CTX *context)
|
||||
{
|
||||
context->count[0] = 0;
|
||||
context->count[1] = 0;
|
||||
context->state[0] = 0x67452301;
|
||||
context->state[1] = 0xEFCDAB89;
|
||||
context->state[2] = 0x98BADCFE;
|
||||
context->state[3] = 0x10325476;
|
||||
context->count[0] = 0;
|
||||
context->count[1] = 0;
|
||||
context->state[0] = 0x67452301;
|
||||
context->state[1] = 0xEFCDAB89;
|
||||
context->state[2] = 0x98BADCFE;
|
||||
context->state[3] = 0x10325476;
|
||||
}
|
||||
void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen)
|
||||
void MD5Update(MD5_CTX *context, unsigned char *input, unsigned int inputlen)
|
||||
{
|
||||
unsigned int i = 0,index = 0,partlen = 0;
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
partlen = 64 - index;
|
||||
context->count[0] += inputlen << 3;
|
||||
if(context->count[0] < (inputlen << 3))
|
||||
context->count[1]++;
|
||||
context->count[1] += inputlen >> 29;
|
||||
|
||||
if(inputlen >= partlen)
|
||||
{
|
||||
memcpy(&context->buffer[index],input,partlen);
|
||||
MD5Transform(context->state,context->buffer);
|
||||
for(i = partlen;i+64 <= inputlen;i+=64)
|
||||
MD5Transform(context->state,&input[i]);
|
||||
index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
i = 0;
|
||||
}
|
||||
memcpy(&context->buffer[index],&input[i],inputlen-i);
|
||||
unsigned int i = 0, index = 0, partlen = 0;
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
partlen = 64 - index;
|
||||
context->count[0] += inputlen << 3;
|
||||
if (context->count[0] < (inputlen << 3))
|
||||
context->count[1]++;
|
||||
context->count[1] += inputlen >> 29;
|
||||
|
||||
if (inputlen >= partlen) {
|
||||
memcpy(&context->buffer[index], input, partlen);
|
||||
MD5Transform(context->state, context->buffer);
|
||||
for (i = partlen; i + 64 <= inputlen; i += 64)
|
||||
MD5Transform(context->state, &input[i]);
|
||||
index = 0;
|
||||
} else {
|
||||
i = 0;
|
||||
}
|
||||
memcpy(&context->buffer[index], &input[i], inputlen - i);
|
||||
}
|
||||
void MD5Final(MD5_CTX *context,unsigned char digest[16])
|
||||
void MD5Final(MD5_CTX *context, unsigned char digest[16])
|
||||
{
|
||||
unsigned int index = 0,padlen = 0;
|
||||
unsigned char bits[8];
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
padlen = (index < 56)?(56-index):(120-index);
|
||||
MD5Encode(bits,context->count,8);
|
||||
MD5Update(context,PADDING,padlen);
|
||||
MD5Update(context,bits,8);
|
||||
MD5Encode(digest,context->state,16);
|
||||
unsigned int index = 0, padlen = 0;
|
||||
unsigned char bits[8];
|
||||
index = (context->count[0] >> 3) & 0x3F;
|
||||
padlen = (index < 56) ? (56 - index) : (120 - index);
|
||||
MD5Encode(bits, context->count, 8);
|
||||
MD5Update(context, PADDING, padlen);
|
||||
MD5Update(context, bits, 8);
|
||||
MD5Encode(digest, context->state, 16);
|
||||
}
|
||||
void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len)
|
||||
void MD5Encode(unsigned char *output, unsigned int *input, unsigned int len)
|
||||
{
|
||||
unsigned int i = 0,j = 0;
|
||||
while(j < len)
|
||||
{
|
||||
output[j] = input[i] & 0xFF;
|
||||
output[j+1] = (input[i] >> 8) & 0xFF;
|
||||
output[j+2] = (input[i] >> 16) & 0xFF;
|
||||
output[j+3] = (input[i] >> 24) & 0xFF;
|
||||
i++;
|
||||
j+=4;
|
||||
}
|
||||
unsigned int i = 0, j = 0;
|
||||
while (j < len) {
|
||||
output[j] = input[i] & 0xFF;
|
||||
output[j + 1] = (input[i] >> 8) & 0xFF;
|
||||
output[j + 2] = (input[i] >> 16) & 0xFF;
|
||||
output[j + 3] = (input[i] >> 24) & 0xFF;
|
||||
i++;
|
||||
j += 4;
|
||||
}
|
||||
}
|
||||
void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len)
|
||||
void MD5Decode(unsigned int *output, unsigned char *input, unsigned int len)
|
||||
{
|
||||
unsigned int i = 0,j = 0;
|
||||
while(j < len)
|
||||
{
|
||||
output[i] = (input[j]) |
|
||||
(input[j+1] << 8) |
|
||||
(input[j+2] << 16) |
|
||||
(input[j+3] << 24);
|
||||
i++;
|
||||
j+=4;
|
||||
}
|
||||
unsigned int i = 0, j = 0;
|
||||
while (j < len) {
|
||||
output[i] = (input[j]) | (input[j + 1] << 8) |
|
||||
(input[j + 2] << 16) | (input[j + 3] << 24);
|
||||
i++;
|
||||
j += 4;
|
||||
}
|
||||
}
|
||||
void MD5Transform(unsigned int state[4],unsigned char block[64])
|
||||
void MD5Transform(unsigned int state[4], unsigned char block[64])
|
||||
{
|
||||
unsigned int a = state[0];
|
||||
unsigned int b = state[1];
|
||||
unsigned int c = state[2];
|
||||
unsigned int d = state[3];
|
||||
unsigned int x[64];
|
||||
MD5Decode(x,block,64);
|
||||
FF(a, b, c, d, x[ 0], 7, 0xd76aa478); /* 1 */
|
||||
FF(d, a, b, c, x[ 1], 12, 0xe8c7b756); /* 2 */
|
||||
FF(c, d, a, b, x[ 2], 17, 0x242070db); /* 3 */
|
||||
FF(b, c, d, a, x[ 3], 22, 0xc1bdceee); /* 4 */
|
||||
FF(a, b, c, d, x[ 4], 7, 0xf57c0faf); /* 5 */
|
||||
FF(d, a, b, c, x[ 5], 12, 0x4787c62a); /* 6 */
|
||||
FF(c, d, a, b, x[ 6], 17, 0xa8304613); /* 7 */
|
||||
FF(b, c, d, a, x[ 7], 22, 0xfd469501); /* 8 */
|
||||
FF(a, b, c, d, x[ 8], 7, 0x698098d8); /* 9 */
|
||||
FF(d, a, b, c, x[ 9], 12, 0x8b44f7af); /* 10 */
|
||||
FF(c, d, a, b, x[10], 17, 0xffff5bb1); /* 11 */
|
||||
FF(b, c, d, a, x[11], 22, 0x895cd7be); /* 12 */
|
||||
FF(a, b, c, d, x[12], 7, 0x6b901122); /* 13 */
|
||||
FF(d, a, b, c, x[13], 12, 0xfd987193); /* 14 */
|
||||
FF(c, d, a, b, x[14], 17, 0xa679438e); /* 15 */
|
||||
FF(b, c, d, a, x[15], 22, 0x49b40821); /* 16 */
|
||||
|
||||
/* Round 2 */
|
||||
GG(a, b, c, d, x[ 1], 5, 0xf61e2562); /* 17 */
|
||||
GG(d, a, b, c, x[ 6], 9, 0xc040b340); /* 18 */
|
||||
GG(c, d, a, b, x[11], 14, 0x265e5a51); /* 19 */
|
||||
GG(b, c, d, a, x[ 0], 20, 0xe9b6c7aa); /* 20 */
|
||||
GG(a, b, c, d, x[ 5], 5, 0xd62f105d); /* 21 */
|
||||
GG(d, a, b, c, x[10], 9, 0x2441453); /* 22 */
|
||||
GG(c, d, a, b, x[15], 14, 0xd8a1e681); /* 23 */
|
||||
GG(b, c, d, a, x[ 4], 20, 0xe7d3fbc8); /* 24 */
|
||||
GG(a, b, c, d, x[ 9], 5, 0x21e1cde6); /* 25 */
|
||||
GG(d, a, b, c, x[14], 9, 0xc33707d6); /* 26 */
|
||||
GG(c, d, a, b, x[ 3], 14, 0xf4d50d87); /* 27 */
|
||||
GG(b, c, d, a, x[ 8], 20, 0x455a14ed); /* 28 */
|
||||
GG(a, b, c, d, x[13], 5, 0xa9e3e905); /* 29 */
|
||||
GG(d, a, b, c, x[ 2], 9, 0xfcefa3f8); /* 30 */
|
||||
GG(c, d, a, b, x[ 7], 14, 0x676f02d9); /* 31 */
|
||||
GG(b, c, d, a, x[12], 20, 0x8d2a4c8a); /* 32 */
|
||||
|
||||
/* Round 3 */
|
||||
HH(a, b, c, d, x[ 5], 4, 0xfffa3942); /* 33 */
|
||||
HH(d, a, b, c, x[ 8], 11, 0x8771f681); /* 34 */
|
||||
HH(c, d, a, b, x[11], 16, 0x6d9d6122); /* 35 */
|
||||
HH(b, c, d, a, x[14], 23, 0xfde5380c); /* 36 */
|
||||
HH(a, b, c, d, x[ 1], 4, 0xa4beea44); /* 37 */
|
||||
HH(d, a, b, c, x[ 4], 11, 0x4bdecfa9); /* 38 */
|
||||
HH(c, d, a, b, x[ 7], 16, 0xf6bb4b60); /* 39 */
|
||||
HH(b, c, d, a, x[10], 23, 0xbebfbc70); /* 40 */
|
||||
HH(a, b, c, d, x[13], 4, 0x289b7ec6); /* 41 */
|
||||
HH(d, a, b, c, x[ 0], 11, 0xeaa127fa); /* 42 */
|
||||
HH(c, d, a, b, x[ 3], 16, 0xd4ef3085); /* 43 */
|
||||
HH(b, c, d, a, x[ 6], 23, 0x4881d05); /* 44 */
|
||||
HH(a, b, c, d, x[ 9], 4, 0xd9d4d039); /* 45 */
|
||||
HH(d, a, b, c, x[12], 11, 0xe6db99e5); /* 46 */
|
||||
HH(c, d, a, b, x[15], 16, 0x1fa27cf8); /* 47 */
|
||||
HH(b, c, d, a, x[ 2], 23, 0xc4ac5665); /* 48 */
|
||||
|
||||
/* Round 4 */
|
||||
II(a, b, c, d, x[ 0], 6, 0xf4292244); /* 49 */
|
||||
II(d, a, b, c, x[ 7], 10, 0x432aff97); /* 50 */
|
||||
II(c, d, a, b, x[14], 15, 0xab9423a7); /* 51 */
|
||||
II(b, c, d, a, x[ 5], 21, 0xfc93a039); /* 52 */
|
||||
II(a, b, c, d, x[12], 6, 0x655b59c3); /* 53 */
|
||||
II(d, a, b, c, x[ 3], 10, 0x8f0ccc92); /* 54 */
|
||||
II(c, d, a, b, x[10], 15, 0xffeff47d); /* 55 */
|
||||
II(b, c, d, a, x[ 1], 21, 0x85845dd1); /* 56 */
|
||||
II(a, b, c, d, x[ 8], 6, 0x6fa87e4f); /* 57 */
|
||||
II(d, a, b, c, x[15], 10, 0xfe2ce6e0); /* 58 */
|
||||
II(c, d, a, b, x[ 6], 15, 0xa3014314); /* 59 */
|
||||
II(b, c, d, a, x[13], 21, 0x4e0811a1); /* 60 */
|
||||
II(a, b, c, d, x[ 4], 6, 0xf7537e82); /* 61 */
|
||||
II(d, a, b, c, x[11], 10, 0xbd3af235); /* 62 */
|
||||
II(c, d, a, b, x[ 2], 15, 0x2ad7d2bb); /* 63 */
|
||||
II(b, c, d, a, x[ 9], 21, 0xeb86d391); /* 64 */
|
||||
state[0] += a;
|
||||
state[1] += b;
|
||||
state[2] += c;
|
||||
state[3] += d;
|
||||
unsigned int a = state[0];
|
||||
unsigned int b = state[1];
|
||||
unsigned int c = state[2];
|
||||
unsigned int d = state[3];
|
||||
unsigned int x[64];
|
||||
MD5Decode(x, block, 64);
|
||||
FF(a, b, c, d, x[0], 7, 0xd76aa478); /* 1 */
|
||||
FF(d, a, b, c, x[1], 12, 0xe8c7b756); /* 2 */
|
||||
FF(c, d, a, b, x[2], 17, 0x242070db); /* 3 */
|
||||
FF(b, c, d, a, x[3], 22, 0xc1bdceee); /* 4 */
|
||||
FF(a, b, c, d, x[4], 7, 0xf57c0faf); /* 5 */
|
||||
FF(d, a, b, c, x[5], 12, 0x4787c62a); /* 6 */
|
||||
FF(c, d, a, b, x[6], 17, 0xa8304613); /* 7 */
|
||||
FF(b, c, d, a, x[7], 22, 0xfd469501); /* 8 */
|
||||
FF(a, b, c, d, x[8], 7, 0x698098d8); /* 9 */
|
||||
FF(d, a, b, c, x[9], 12, 0x8b44f7af); /* 10 */
|
||||
FF(c, d, a, b, x[10], 17, 0xffff5bb1); /* 11 */
|
||||
FF(b, c, d, a, x[11], 22, 0x895cd7be); /* 12 */
|
||||
FF(a, b, c, d, x[12], 7, 0x6b901122); /* 13 */
|
||||
FF(d, a, b, c, x[13], 12, 0xfd987193); /* 14 */
|
||||
FF(c, d, a, b, x[14], 17, 0xa679438e); /* 15 */
|
||||
FF(b, c, d, a, x[15], 22, 0x49b40821); /* 16 */
|
||||
|
||||
/* Round 2 */
|
||||
GG(a, b, c, d, x[1], 5, 0xf61e2562); /* 17 */
|
||||
GG(d, a, b, c, x[6], 9, 0xc040b340); /* 18 */
|
||||
GG(c, d, a, b, x[11], 14, 0x265e5a51); /* 19 */
|
||||
GG(b, c, d, a, x[0], 20, 0xe9b6c7aa); /* 20 */
|
||||
GG(a, b, c, d, x[5], 5, 0xd62f105d); /* 21 */
|
||||
GG(d, a, b, c, x[10], 9, 0x2441453); /* 22 */
|
||||
GG(c, d, a, b, x[15], 14, 0xd8a1e681); /* 23 */
|
||||
GG(b, c, d, a, x[4], 20, 0xe7d3fbc8); /* 24 */
|
||||
GG(a, b, c, d, x[9], 5, 0x21e1cde6); /* 25 */
|
||||
GG(d, a, b, c, x[14], 9, 0xc33707d6); /* 26 */
|
||||
GG(c, d, a, b, x[3], 14, 0xf4d50d87); /* 27 */
|
||||
GG(b, c, d, a, x[8], 20, 0x455a14ed); /* 28 */
|
||||
GG(a, b, c, d, x[13], 5, 0xa9e3e905); /* 29 */
|
||||
GG(d, a, b, c, x[2], 9, 0xfcefa3f8); /* 30 */
|
||||
GG(c, d, a, b, x[7], 14, 0x676f02d9); /* 31 */
|
||||
GG(b, c, d, a, x[12], 20, 0x8d2a4c8a); /* 32 */
|
||||
|
||||
/* Round 3 */
|
||||
HH(a, b, c, d, x[5], 4, 0xfffa3942); /* 33 */
|
||||
HH(d, a, b, c, x[8], 11, 0x8771f681); /* 34 */
|
||||
HH(c, d, a, b, x[11], 16, 0x6d9d6122); /* 35 */
|
||||
HH(b, c, d, a, x[14], 23, 0xfde5380c); /* 36 */
|
||||
HH(a, b, c, d, x[1], 4, 0xa4beea44); /* 37 */
|
||||
HH(d, a, b, c, x[4], 11, 0x4bdecfa9); /* 38 */
|
||||
HH(c, d, a, b, x[7], 16, 0xf6bb4b60); /* 39 */
|
||||
HH(b, c, d, a, x[10], 23, 0xbebfbc70); /* 40 */
|
||||
HH(a, b, c, d, x[13], 4, 0x289b7ec6); /* 41 */
|
||||
HH(d, a, b, c, x[0], 11, 0xeaa127fa); /* 42 */
|
||||
HH(c, d, a, b, x[3], 16, 0xd4ef3085); /* 43 */
|
||||
HH(b, c, d, a, x[6], 23, 0x4881d05); /* 44 */
|
||||
HH(a, b, c, d, x[9], 4, 0xd9d4d039); /* 45 */
|
||||
HH(d, a, b, c, x[12], 11, 0xe6db99e5); /* 46 */
|
||||
HH(c, d, a, b, x[15], 16, 0x1fa27cf8); /* 47 */
|
||||
HH(b, c, d, a, x[2], 23, 0xc4ac5665); /* 48 */
|
||||
|
||||
/* Round 4 */
|
||||
II(a, b, c, d, x[0], 6, 0xf4292244); /* 49 */
|
||||
II(d, a, b, c, x[7], 10, 0x432aff97); /* 50 */
|
||||
II(c, d, a, b, x[14], 15, 0xab9423a7); /* 51 */
|
||||
II(b, c, d, a, x[5], 21, 0xfc93a039); /* 52 */
|
||||
II(a, b, c, d, x[12], 6, 0x655b59c3); /* 53 */
|
||||
II(d, a, b, c, x[3], 10, 0x8f0ccc92); /* 54 */
|
||||
II(c, d, a, b, x[10], 15, 0xffeff47d); /* 55 */
|
||||
II(b, c, d, a, x[1], 21, 0x85845dd1); /* 56 */
|
||||
II(a, b, c, d, x[8], 6, 0x6fa87e4f); /* 57 */
|
||||
II(d, a, b, c, x[15], 10, 0xfe2ce6e0); /* 58 */
|
||||
II(c, d, a, b, x[6], 15, 0xa3014314); /* 59 */
|
||||
II(b, c, d, a, x[13], 21, 0x4e0811a1); /* 60 */
|
||||
II(a, b, c, d, x[4], 6, 0xf7537e82); /* 61 */
|
||||
II(d, a, b, c, x[11], 10, 0xbd3af235); /* 62 */
|
||||
II(c, d, a, b, x[2], 15, 0x2ad7d2bb); /* 63 */
|
||||
II(b, c, d, a, x[9], 21, 0xeb86d391); /* 64 */
|
||||
state[0] += a;
|
||||
state[1] += b;
|
||||
state[2] += c;
|
||||
state[3] += d;
|
||||
}
|
||||
|
||||
@@ -1,48 +1,46 @@
|
||||
#ifndef MD5_H
|
||||
#define MD5_H
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int count[2];
|
||||
unsigned int state[4];
|
||||
unsigned char buffer[64];
|
||||
}MD5_CTX;
|
||||
|
||||
|
||||
#define F(x,y,z) ((x & y) | (~x & z))
|
||||
#define G(x,y,z) ((x & z) | (y & ~z))
|
||||
#define H(x,y,z) (x^y^z)
|
||||
#define I(x,y,z) (y ^ (x | ~z))
|
||||
#define ROTATE_LEFT(x,n) ((x << n) | (x >> (32-n)))
|
||||
#define FF(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += F(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
#define GG(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += G(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
#define HH(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += H(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
#define II(a,b,c,d,x,s,ac) \
|
||||
{ \
|
||||
a += I(b,c,d) + x + ac; \
|
||||
a = ROTATE_LEFT(a,s); \
|
||||
a += b; \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
unsigned int count[2];
|
||||
unsigned int state[4];
|
||||
unsigned char buffer[64];
|
||||
} MD5_CTX;
|
||||
|
||||
#define F(x, y, z) ((x & y) | (~x & z))
|
||||
#define G(x, y, z) ((x & z) | (y & ~z))
|
||||
#define H(x, y, z) (x ^ y ^ z)
|
||||
#define I(x, y, z) (y ^ (x | ~z))
|
||||
#define ROTATE_LEFT(x, n) ((x << n) | (x >> (32 - n)))
|
||||
#define FF(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += F(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
#define GG(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += G(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
#define HH(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += H(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
#define II(a, b, c, d, x, s, ac) \
|
||||
{ \
|
||||
a += I(b, c, d) + x + ac; \
|
||||
a = ROTATE_LEFT(a, s); \
|
||||
a += b; \
|
||||
}
|
||||
void MD5Init(MD5_CTX *context);
|
||||
void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen);
|
||||
void MD5Final(MD5_CTX *context,unsigned char digest[16]);
|
||||
void MD5Transform(unsigned int state[4],unsigned char block[64]);
|
||||
void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len);
|
||||
void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len);
|
||||
|
||||
void MD5Update(MD5_CTX *context, unsigned char *input, unsigned int inputlen);
|
||||
void MD5Final(MD5_CTX *context, unsigned char digest[16]);
|
||||
void MD5Transform(unsigned int state[4], unsigned char block[64]);
|
||||
void MD5Encode(unsigned char *output, unsigned int *input, unsigned int len);
|
||||
void MD5Decode(unsigned int *output, unsigned char *input, unsigned int len);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -17,132 +17,132 @@
|
||||
* Addresses within RWNX_ADDR_SYSTEM
|
||||
*****************************************************************************/
|
||||
/* Shard RAM */
|
||||
#define SHARED_RAM_START_ADDR 0x00000000
|
||||
#define SHARED_RAM_START_ADDR 0x00000000
|
||||
|
||||
/* IPC registers */
|
||||
#define IPC_REG_BASE_ADDR 0x00800000
|
||||
#define IPC_REG_BASE_ADDR 0x00800000
|
||||
|
||||
/* System Controller Registers */
|
||||
#define SYSCTRL_SIGNATURE_ADDR 0x00900000
|
||||
#define SYSCTRL_SIGNATURE_ADDR 0x00900000
|
||||
// old diag register name
|
||||
#define SYSCTRL_DIAG_CONF_ADDR 0x00900068
|
||||
#define SYSCTRL_PHYDIAG_CONF_ADDR 0x00900074
|
||||
#define SYSCTRL_RIUDIAG_CONF_ADDR 0x00900078
|
||||
#define SYSCTRL_DIAG_CONF_ADDR 0x00900068
|
||||
#define SYSCTRL_PHYDIAG_CONF_ADDR 0x00900074
|
||||
#define SYSCTRL_RIUDIAG_CONF_ADDR 0x00900078
|
||||
// new diag register name
|
||||
#define SYSCTRL_DIAG_CONF0 0x00900064
|
||||
#define SYSCTRL_DIAG_CONF1 0x00900068
|
||||
#define SYSCTRL_DIAG_CONF2 0x00900074
|
||||
#define SYSCTRL_DIAG_CONF3 0x00900078
|
||||
#define SYSCTRL_MISC_CNTL_ADDR 0x009000E0
|
||||
#define BOOTROM_ENABLE BIT(4)
|
||||
#define FPGA_B_RESET BIT(1)
|
||||
#define SOFT_RESET BIT(0)
|
||||
#define SYSCTRL_DIAG_CONF0 0x00900064
|
||||
#define SYSCTRL_DIAG_CONF1 0x00900068
|
||||
#define SYSCTRL_DIAG_CONF2 0x00900074
|
||||
#define SYSCTRL_DIAG_CONF3 0x00900078
|
||||
#define SYSCTRL_MISC_CNTL_ADDR 0x009000E0
|
||||
#define BOOTROM_ENABLE BIT(4)
|
||||
#define FPGA_B_RESET BIT(1)
|
||||
#define SOFT_RESET BIT(0)
|
||||
|
||||
/* MAC platform */
|
||||
#define NXMAC_VERSION_1_ADDR 0x00B00004
|
||||
#define NXMAC_MU_MIMO_TX_BIT BIT(19)
|
||||
#define NXMAC_BFMER_BIT BIT(18)
|
||||
#define NXMAC_BFMEE_BIT BIT(17)
|
||||
#define NXMAC_MAC_80211MH_FORMAT_BIT BIT(16)
|
||||
#define NXMAC_COEX_BIT BIT(14)
|
||||
#define NXMAC_WAPI_BIT BIT(13)
|
||||
#define NXMAC_TPC_BIT BIT(12)
|
||||
#define NXMAC_VHT_BIT BIT(11)
|
||||
#define NXMAC_HT_BIT BIT(10)
|
||||
#define NXMAC_RCE_BIT BIT(8)
|
||||
#define NXMAC_CCMP_BIT BIT(7)
|
||||
#define NXMAC_TKIP_BIT BIT(6)
|
||||
#define NXMAC_WEP_BIT BIT(5)
|
||||
#define NXMAC_SECURITY_BIT BIT(4)
|
||||
#define NXMAC_SME_BIT BIT(3)
|
||||
#define NXMAC_HCCA_BIT BIT(2)
|
||||
#define NXMAC_EDCA_BIT BIT(1)
|
||||
#define NXMAC_QOS_BIT BIT(0)
|
||||
#define NXMAC_VERSION_1_ADDR 0x00B00004
|
||||
#define NXMAC_MU_MIMO_TX_BIT BIT(19)
|
||||
#define NXMAC_BFMER_BIT BIT(18)
|
||||
#define NXMAC_BFMEE_BIT BIT(17)
|
||||
#define NXMAC_MAC_80211MH_FORMAT_BIT BIT(16)
|
||||
#define NXMAC_COEX_BIT BIT(14)
|
||||
#define NXMAC_WAPI_BIT BIT(13)
|
||||
#define NXMAC_TPC_BIT BIT(12)
|
||||
#define NXMAC_VHT_BIT BIT(11)
|
||||
#define NXMAC_HT_BIT BIT(10)
|
||||
#define NXMAC_RCE_BIT BIT(8)
|
||||
#define NXMAC_CCMP_BIT BIT(7)
|
||||
#define NXMAC_TKIP_BIT BIT(6)
|
||||
#define NXMAC_WEP_BIT BIT(5)
|
||||
#define NXMAC_SECURITY_BIT BIT(4)
|
||||
#define NXMAC_SME_BIT BIT(3)
|
||||
#define NXMAC_HCCA_BIT BIT(2)
|
||||
#define NXMAC_EDCA_BIT BIT(1)
|
||||
#define NXMAC_QOS_BIT BIT(0)
|
||||
|
||||
#define NXMAC_RX_CNTRL_ADDR 0x00B00060
|
||||
#define NXMAC_EN_DUPLICATE_DETECTION_BIT BIT(31)
|
||||
#define NXMAC_ACCEPT_UNKNOWN_BIT BIT(30)
|
||||
#define NXMAC_ACCEPT_OTHER_DATA_FRAMES_BIT BIT(29)
|
||||
#define NXMAC_ACCEPT_QO_S_NULL_BIT BIT(28)
|
||||
#define NXMAC_ACCEPT_QCFWO_DATA_BIT BIT(27)
|
||||
#define NXMAC_ACCEPT_Q_DATA_BIT BIT(26)
|
||||
#define NXMAC_ACCEPT_CFWO_DATA_BIT BIT(25)
|
||||
#define NXMAC_ACCEPT_DATA_BIT BIT(24)
|
||||
#define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_BIT BIT(23)
|
||||
#define NXMAC_ACCEPT_CF_END_BIT BIT(22)
|
||||
#define NXMAC_ACCEPT_ACK_BIT BIT(21)
|
||||
#define NXMAC_ACCEPT_CTS_BIT BIT(20)
|
||||
#define NXMAC_ACCEPT_RTS_BIT BIT(19)
|
||||
#define NXMAC_ACCEPT_PS_POLL_BIT BIT(18)
|
||||
#define NXMAC_ACCEPT_BA_BIT BIT(17)
|
||||
#define NXMAC_ACCEPT_BAR_BIT BIT(16)
|
||||
#define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_BIT BIT(15)
|
||||
#define NXMAC_ACCEPT_BFMEE_FRAMES_BIT BIT(14)
|
||||
#define NXMAC_ACCEPT_ALL_BEACON_BIT BIT(13)
|
||||
#define NXMAC_ACCEPT_NOT_EXPECTED_BA_BIT BIT(12)
|
||||
#define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_BIT BIT(11)
|
||||
#define NXMAC_ACCEPT_BEACON_BIT BIT(10)
|
||||
#define NXMAC_ACCEPT_PROBE_RESP_BIT BIT(9)
|
||||
#define NXMAC_ACCEPT_PROBE_REQ_BIT BIT(8)
|
||||
#define NXMAC_ACCEPT_MY_UNICAST_BIT BIT(7)
|
||||
#define NXMAC_ACCEPT_UNICAST_BIT BIT(6)
|
||||
#define NXMAC_ACCEPT_ERROR_FRAMES_BIT BIT(5)
|
||||
#define NXMAC_ACCEPT_OTHER_BSSID_BIT BIT(4)
|
||||
#define NXMAC_ACCEPT_BROADCAST_BIT BIT(3)
|
||||
#define NXMAC_ACCEPT_MULTICAST_BIT BIT(2)
|
||||
#define NXMAC_DONT_DECRYPT_BIT BIT(1)
|
||||
#define NXMAC_EXC_UNENCRYPTED_BIT BIT(0)
|
||||
#define NXMAC_RX_CNTRL_ADDR 0x00B00060
|
||||
#define NXMAC_EN_DUPLICATE_DETECTION_BIT BIT(31)
|
||||
#define NXMAC_ACCEPT_UNKNOWN_BIT BIT(30)
|
||||
#define NXMAC_ACCEPT_OTHER_DATA_FRAMES_BIT BIT(29)
|
||||
#define NXMAC_ACCEPT_QO_S_NULL_BIT BIT(28)
|
||||
#define NXMAC_ACCEPT_QCFWO_DATA_BIT BIT(27)
|
||||
#define NXMAC_ACCEPT_Q_DATA_BIT BIT(26)
|
||||
#define NXMAC_ACCEPT_CFWO_DATA_BIT BIT(25)
|
||||
#define NXMAC_ACCEPT_DATA_BIT BIT(24)
|
||||
#define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_BIT BIT(23)
|
||||
#define NXMAC_ACCEPT_CF_END_BIT BIT(22)
|
||||
#define NXMAC_ACCEPT_ACK_BIT BIT(21)
|
||||
#define NXMAC_ACCEPT_CTS_BIT BIT(20)
|
||||
#define NXMAC_ACCEPT_RTS_BIT BIT(19)
|
||||
#define NXMAC_ACCEPT_PS_POLL_BIT BIT(18)
|
||||
#define NXMAC_ACCEPT_BA_BIT BIT(17)
|
||||
#define NXMAC_ACCEPT_BAR_BIT BIT(16)
|
||||
#define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_BIT BIT(15)
|
||||
#define NXMAC_ACCEPT_BFMEE_FRAMES_BIT BIT(14)
|
||||
#define NXMAC_ACCEPT_ALL_BEACON_BIT BIT(13)
|
||||
#define NXMAC_ACCEPT_NOT_EXPECTED_BA_BIT BIT(12)
|
||||
#define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_BIT BIT(11)
|
||||
#define NXMAC_ACCEPT_BEACON_BIT BIT(10)
|
||||
#define NXMAC_ACCEPT_PROBE_RESP_BIT BIT(9)
|
||||
#define NXMAC_ACCEPT_PROBE_REQ_BIT BIT(8)
|
||||
#define NXMAC_ACCEPT_MY_UNICAST_BIT BIT(7)
|
||||
#define NXMAC_ACCEPT_UNICAST_BIT BIT(6)
|
||||
#define NXMAC_ACCEPT_ERROR_FRAMES_BIT BIT(5)
|
||||
#define NXMAC_ACCEPT_OTHER_BSSID_BIT BIT(4)
|
||||
#define NXMAC_ACCEPT_BROADCAST_BIT BIT(3)
|
||||
#define NXMAC_ACCEPT_MULTICAST_BIT BIT(2)
|
||||
#define NXMAC_DONT_DECRYPT_BIT BIT(1)
|
||||
#define NXMAC_EXC_UNENCRYPTED_BIT BIT(0)
|
||||
|
||||
#define NXMAC_DEBUG_PORT_SEL_ADDR 0x00B00510
|
||||
#define NXMAC_SW_SET_PROFILING_ADDR 0x00B08564
|
||||
#define NXMAC_SW_CLEAR_PROFILING_ADDR 0x00B08568
|
||||
#define NXMAC_DEBUG_PORT_SEL_ADDR 0x00B00510
|
||||
#define NXMAC_SW_SET_PROFILING_ADDR 0x00B08564
|
||||
#define NXMAC_SW_CLEAR_PROFILING_ADDR 0x00B08568
|
||||
|
||||
/* Modem Status */
|
||||
#define MDM_HDMCONFIG_ADDR 0x00C00000
|
||||
#define MDM_HDMCONFIG_ADDR 0x00C00000
|
||||
|
||||
/* Clock gating configuration */
|
||||
#define MDM_MEMCLKCTRL0_ADDR 0x00C00848
|
||||
#define MDM_CLKGATEFCTRL0_ADDR 0x00C00874
|
||||
#define CRM_CLKGATEFCTRL0_ADDR 0x00940010
|
||||
#define MDM_MEMCLKCTRL0_ADDR 0x00C00848
|
||||
#define MDM_CLKGATEFCTRL0_ADDR 0x00C00874
|
||||
#define CRM_CLKGATEFCTRL0_ADDR 0x00940010
|
||||
|
||||
/* AGC (trident) */
|
||||
#define AGC_RWNXAGCCNTL_ADDR 0x00C02060
|
||||
#define AGC_RWNXAGCCNTL_ADDR 0x00C02060
|
||||
|
||||
/* LDPC RAM*/
|
||||
#define PHY_LDPC_RAM_ADDR 0x00C09000
|
||||
#define PHY_LDPC_RAM_ADDR 0x00C09000
|
||||
|
||||
/* FCU (elma )*/
|
||||
#define FCU_RWNXFCAGCCNTL_ADDR 0x00C09034
|
||||
#define FCU_RWNXFCAGCCNTL_ADDR 0x00C09034
|
||||
|
||||
/* AGC RAM */
|
||||
#define PHY_AGC_UCODE_ADDR 0x00C0A000
|
||||
#define PHY_AGC_UCODE_ADDR 0x00C0A000
|
||||
|
||||
/* RIU */
|
||||
#define RIU_RWNXVERSION_ADDR 0x00C0B000
|
||||
#define RIU_RWNXDYNAMICCONFIG_ADDR 0x00C0B008
|
||||
#define RIU_AGCMEMBISTSTAT_ADDR 0x00C0B238
|
||||
#define RIU_AGCMEMSIGNATURESTAT_ADDR 0x00C0B23C
|
||||
#define RIU_RWNXAGCCNTL_ADDR 0x00C0B390
|
||||
#define RIU_RWNXVERSION_ADDR 0x00C0B000
|
||||
#define RIU_RWNXDYNAMICCONFIG_ADDR 0x00C0B008
|
||||
#define RIU_AGCMEMBISTSTAT_ADDR 0x00C0B238
|
||||
#define RIU_AGCMEMSIGNATURESTAT_ADDR 0x00C0B23C
|
||||
#define RIU_RWNXAGCCNTL_ADDR 0x00C0B390
|
||||
|
||||
/* FCU RAM */
|
||||
#define PHY_FCU_UCODE_ADDR 0x00C0E000
|
||||
#define PHY_FCU_UCODE_ADDR 0x00C0E000
|
||||
|
||||
/* RF ITF */
|
||||
#define FPGAB_MPIF_SEL_ADDR 0x00C10030
|
||||
#define RF_V6_DIAGPORT_CONF1_ADDR 0x00C10010
|
||||
#define RF_v6_PHYDIAG_CONF1_ADDR 0x00C10018
|
||||
#define FPGAB_MPIF_SEL_ADDR 0x00C10030
|
||||
#define RF_V6_DIAGPORT_CONF1_ADDR 0x00C10010
|
||||
#define RF_v6_PHYDIAG_CONF1_ADDR 0x00C10018
|
||||
|
||||
#define RF_V7_DIAGPORT_CONF1_ADDR 0x00F10010
|
||||
#define RF_v7_PHYDIAG_CONF1_ADDR 0x00F10018
|
||||
#define RF_V7_DIAGPORT_CONF1_ADDR 0x00F10010
|
||||
#define RF_v7_PHYDIAG_CONF1_ADDR 0x00F10018
|
||||
|
||||
/*****************************************************************************
|
||||
* Macros for generated register files
|
||||
*****************************************************************************/
|
||||
/* Macros for IPC registers access (used in reg_ipc_app.h) */
|
||||
#define REG_IPC_APP_RD(env, INDEX) \
|
||||
#define REG_IPC_APP_RD(env, INDEX) \
|
||||
(*(volatile u32 *)((u8 *)env + IPC_REG_BASE_ADDR + 4 * (INDEX)))
|
||||
|
||||
#define REG_IPC_APP_WR(env, INDEX, value) \
|
||||
#define REG_IPC_APP_WR(env, INDEX, value) \
|
||||
(*(volatile u32 *)((u8 *)env + IPC_REG_BASE_ADDR + 4 * (INDEX)) = value)
|
||||
|
||||
#endif /* REG_ACCESS_H_ */
|
||||
|
||||
@@ -5,15 +5,14 @@
|
||||
//#include "regdb.h"
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)
|
||||
#define REG_RULE_EXT(start, end, bw, gain, eirp, dfs_cac, reg_flags) \
|
||||
{ \
|
||||
.freq_range.start_freq_khz = MHZ_TO_KHZ(start), \
|
||||
.freq_range.end_freq_khz = MHZ_TO_KHZ(end), \
|
||||
.freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw), \
|
||||
.power_rule.max_antenna_gain = DBI_TO_MBI(gain),\
|
||||
.power_rule.max_eirp = DBM_TO_MBM(eirp), \
|
||||
.flags = reg_flags, \
|
||||
}
|
||||
#define REG_RULE_EXT(start, end, bw, gain, eirp, dfs_cac, reg_flags) \
|
||||
{ \
|
||||
.freq_range.start_freq_khz = MHZ_TO_KHZ(start), \
|
||||
.freq_range.end_freq_khz = MHZ_TO_KHZ(end), \
|
||||
.freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw), \
|
||||
.power_rule.max_antenna_gain = DBI_TO_MBI(gain), \
|
||||
.power_rule.max_eirp = DBM_TO_MBM(eirp), .flags = reg_flags, \
|
||||
}
|
||||
#define NL80211_RRF_AUTO_BW 0
|
||||
#endif
|
||||
|
||||
@@ -687,24 +686,25 @@ static const struct ieee80211_regdomain regdom_CZ = {
|
||||
};
|
||||
|
||||
static const struct ieee80211_regdomain regdom_DE = {
|
||||
.alpha2 = "DE",
|
||||
.dfs_region = NL80211_DFS_ETSI,
|
||||
.reg_rules = {
|
||||
REG_RULE_EXT(2400, 2483, 40, 0, 20, 0, 0),
|
||||
REG_RULE_EXT(5150, 5250, 80, 0, 20, 0,
|
||||
NL80211_RRF_NO_OUTDOOR |
|
||||
NL80211_RRF_AUTO_BW | 0),
|
||||
REG_RULE_EXT(5250, 5350, 80, 0, 20, 0,
|
||||
NL80211_RRF_NO_OUTDOOR |
|
||||
NL80211_RRF_DFS |
|
||||
NL80211_RRF_AUTO_BW | 0),
|
||||
REG_RULE_EXT(5470, 5695, 160, 0, 27, 0,
|
||||
NL80211_RRF_DFS | 0),
|
||||
/*REG_RULE_EXT(5470, 5725, 160, 0, 27, 0,
|
||||
NL80211_RRF_DFS | 0),*/
|
||||
REG_RULE_EXT(57000, 66000, 2160, 0, 40, 0, 0),
|
||||
},
|
||||
.n_reg_rules = 5
|
||||
.alpha2 = "DE",
|
||||
.dfs_region = NL80211_DFS_ETSI,
|
||||
.reg_rules = {
|
||||
REG_RULE_EXT(2400, 2483, 40, 0, 20, 0, 0),
|
||||
REG_RULE_EXT(5150, 5250, 80, 0, 20, 0, NL80211_RRF_AUTO_BW|
|
||||
NL80211_RRF_NO_OUTDOOR|
|
||||
0),
|
||||
REG_RULE_EXT(5250, 5350, 80, 0, 20, 0, NL80211_RRF_AUTO_BW|
|
||||
NL80211_RRF_DFS|
|
||||
NL80211_RRF_NO_OUTDOOR|
|
||||
0),
|
||||
REG_RULE_EXT(5470, 5725, 160, 0, 20, 0, NL80211_RRF_DFS|
|
||||
0),
|
||||
REG_RULE_EXT(5725, 5875, 80, 0, 20, 0, 0),
|
||||
REG_RULE_EXT(5945, 6425, 160, 0, 20, 0, NL80211_RRF_NO_OUTDOOR|
|
||||
0),
|
||||
REG_RULE_EXT(57000, 66000, 2160, 0, 20, 0, 0),
|
||||
},
|
||||
.n_reg_rules = 7
|
||||
};
|
||||
|
||||
static const struct ieee80211_regdomain regdom_DK = {
|
||||
@@ -1825,6 +1825,18 @@ static const struct ieee80211_regdomain regdom_MY = {
|
||||
.n_reg_rules = 4
|
||||
};
|
||||
|
||||
static const struct ieee80211_regdomain regdom_NG = {
|
||||
.alpha2 = "NG",
|
||||
.dfs_region = NL80211_DFS_ETSI,
|
||||
.reg_rules = {
|
||||
REG_RULE_EXT(2402, 2482, 40, 0, 20, 0, 0),
|
||||
REG_RULE_EXT(5250, 5330, 80, 0, 20, 0, NL80211_RRF_DFS|
|
||||
0),
|
||||
REG_RULE_EXT(5735, 5835, 80, 0, 20, 0, 0),
|
||||
},
|
||||
.n_reg_rules = 3
|
||||
};
|
||||
|
||||
static const struct ieee80211_regdomain regdom_NI = {
|
||||
.alpha2 = "NI",
|
||||
.dfs_region = NL80211_DFS_FCC,
|
||||
@@ -2722,178 +2734,35 @@ static const struct ieee80211_regdomain regdom_ZW = {
|
||||
};
|
||||
|
||||
const struct ieee80211_regdomain *reg_regdb[] = {
|
||||
®dom_00,
|
||||
®dom_AD,
|
||||
®dom_AE,
|
||||
®dom_AF,
|
||||
®dom_AI,
|
||||
®dom_AL,
|
||||
®dom_AM,
|
||||
®dom_AN,
|
||||
®dom_AR,
|
||||
®dom_AS,
|
||||
®dom_AT,
|
||||
®dom_AU,
|
||||
®dom_AW,
|
||||
®dom_AZ,
|
||||
®dom_BA,
|
||||
®dom_BB,
|
||||
®dom_BD,
|
||||
®dom_BE,
|
||||
®dom_BF,
|
||||
®dom_BG,
|
||||
®dom_BH,
|
||||
®dom_BL,
|
||||
®dom_BM,
|
||||
®dom_BN,
|
||||
®dom_BO,
|
||||
®dom_BR,
|
||||
®dom_BS,
|
||||
®dom_BT,
|
||||
®dom_BY,
|
||||
®dom_BZ,
|
||||
®dom_CA,
|
||||
®dom_CF,
|
||||
®dom_CH,
|
||||
®dom_CI,
|
||||
®dom_CL,
|
||||
®dom_CN,
|
||||
®dom_CO,
|
||||
®dom_CR,
|
||||
®dom_CX,
|
||||
®dom_CY,
|
||||
®dom_CZ,
|
||||
®dom_DE,
|
||||
®dom_DK,
|
||||
®dom_DM,
|
||||
®dom_DO,
|
||||
®dom_DZ,
|
||||
®dom_EC,
|
||||
®dom_EE,
|
||||
®dom_EG,
|
||||
®dom_ES,
|
||||
®dom_ET,
|
||||
®dom_FI,
|
||||
®dom_FM,
|
||||
®dom_FR,
|
||||
®dom_GB,
|
||||
®dom_GD,
|
||||
®dom_GE,
|
||||
®dom_GF,
|
||||
®dom_GH,
|
||||
®dom_GL,
|
||||
®dom_GP,
|
||||
®dom_GR,
|
||||
®dom_GT,
|
||||
®dom_GU,
|
||||
®dom_GY,
|
||||
®dom_HK,
|
||||
®dom_HN,
|
||||
®dom_HR,
|
||||
®dom_HT,
|
||||
®dom_HU,
|
||||
®dom_ID,
|
||||
®dom_IE,
|
||||
®dom_IL,
|
||||
®dom_IN,
|
||||
®dom_IR,
|
||||
®dom_IS,
|
||||
®dom_IT,
|
||||
®dom_JM,
|
||||
®dom_JO,
|
||||
®dom_JP,
|
||||
®dom_KE,
|
||||
®dom_KH,
|
||||
®dom_KN,
|
||||
®dom_KP,
|
||||
®dom_KR,
|
||||
®dom_KW,
|
||||
®dom_KY,
|
||||
®dom_KZ,
|
||||
®dom_LB,
|
||||
®dom_LC,
|
||||
®dom_LI,
|
||||
®dom_LK,
|
||||
®dom_LS,
|
||||
®dom_LT,
|
||||
®dom_LU,
|
||||
®dom_LV,
|
||||
®dom_MA,
|
||||
®dom_MC,
|
||||
®dom_MD,
|
||||
®dom_ME,
|
||||
®dom_MF,
|
||||
®dom_MH,
|
||||
®dom_MK,
|
||||
®dom_MN,
|
||||
®dom_MO,
|
||||
®dom_MP,
|
||||
®dom_MQ,
|
||||
®dom_MR,
|
||||
®dom_MT,
|
||||
®dom_MU,
|
||||
®dom_MW,
|
||||
®dom_MX,
|
||||
®dom_MY,
|
||||
®dom_NI,
|
||||
®dom_NL,
|
||||
®dom_NO,
|
||||
®dom_NP,
|
||||
®dom_NZ,
|
||||
®dom_OM,
|
||||
®dom_PA,
|
||||
®dom_PE,
|
||||
®dom_PF,
|
||||
®dom_PG,
|
||||
®dom_PH,
|
||||
®dom_PK,
|
||||
®dom_PL,
|
||||
®dom_PM,
|
||||
®dom_PR,
|
||||
®dom_PT,
|
||||
®dom_PW,
|
||||
®dom_PY,
|
||||
®dom_QA,
|
||||
®dom_RE,
|
||||
®dom_RO,
|
||||
®dom_RS,
|
||||
®dom_RU,
|
||||
®dom_RW,
|
||||
®dom_SA,
|
||||
®dom_SE,
|
||||
®dom_SG,
|
||||
®dom_SI,
|
||||
®dom_SK,
|
||||
®dom_SN,
|
||||
®dom_SR,
|
||||
®dom_SV,
|
||||
®dom_SY,
|
||||
®dom_TC,
|
||||
®dom_TD,
|
||||
®dom_TG,
|
||||
®dom_TH,
|
||||
®dom_TN,
|
||||
®dom_TR,
|
||||
®dom_TT,
|
||||
®dom_TW,
|
||||
®dom_UA,
|
||||
®dom_UG,
|
||||
®dom_US,
|
||||
®dom_UY,
|
||||
®dom_UZ,
|
||||
®dom_VC,
|
||||
®dom_VE,
|
||||
®dom_VI,
|
||||
®dom_VN,
|
||||
®dom_VU,
|
||||
®dom_WF,
|
||||
®dom_YE,
|
||||
®dom_YT,
|
||||
®dom_ZA,
|
||||
®dom_ZW,
|
||||
NULL,
|
||||
®dom_00, ®dom_AD, ®dom_AE, ®dom_AF, ®dom_AI, ®dom_AL,
|
||||
®dom_AM, ®dom_AN, ®dom_AR, ®dom_AS, ®dom_AT, ®dom_AU,
|
||||
®dom_AW, ®dom_AZ, ®dom_BA, ®dom_BB, ®dom_BD, ®dom_BE,
|
||||
®dom_BF, ®dom_BG, ®dom_BH, ®dom_BL, ®dom_BM, ®dom_BN,
|
||||
®dom_BO, ®dom_BR, ®dom_BS, ®dom_BT, ®dom_BY, ®dom_BZ,
|
||||
®dom_CA, ®dom_CF, ®dom_CH, ®dom_CI, ®dom_CL, ®dom_CN,
|
||||
®dom_CO, ®dom_CR, ®dom_CX, ®dom_CY, ®dom_CZ, ®dom_DE,
|
||||
®dom_DK, ®dom_DM, ®dom_DO, ®dom_DZ, ®dom_EC, ®dom_EE,
|
||||
®dom_EG, ®dom_ES, ®dom_ET, ®dom_FI, ®dom_FM, ®dom_FR,
|
||||
®dom_GB, ®dom_GD, ®dom_GE, ®dom_GF, ®dom_GH, ®dom_GL,
|
||||
®dom_GP, ®dom_GR, ®dom_GT, ®dom_GU, ®dom_GY, ®dom_HK,
|
||||
®dom_HN, ®dom_HR, ®dom_HT, ®dom_HU, ®dom_ID, ®dom_IE,
|
||||
®dom_IL, ®dom_IN, ®dom_IR, ®dom_IS, ®dom_IT, ®dom_JM,
|
||||
®dom_JO, ®dom_JP, ®dom_KE, ®dom_KH, ®dom_KN, ®dom_KP,
|
||||
®dom_KR, ®dom_KW, ®dom_KY, ®dom_KZ, ®dom_LB, ®dom_LC,
|
||||
®dom_LI, ®dom_LK, ®dom_LS, ®dom_LT, ®dom_LU, ®dom_LV,
|
||||
®dom_MA, ®dom_MC, ®dom_MD, ®dom_ME, ®dom_MF, ®dom_MH,
|
||||
®dom_MK, ®dom_MN, ®dom_MO, ®dom_MP, ®dom_MQ, ®dom_MR,
|
||||
®dom_MT, ®dom_MU, ®dom_MW, ®dom_MX, ®dom_MY, ®dom_NG,
|
||||
®dom_NI, ®dom_NL, ®dom_NO, ®dom_NP, ®dom_NZ, ®dom_OM,
|
||||
®dom_PA, ®dom_PE, ®dom_PF, ®dom_PG, ®dom_PH, ®dom_PK,
|
||||
®dom_PL, ®dom_PM, ®dom_PR, ®dom_PT, ®dom_PW, ®dom_PY,
|
||||
®dom_QA, ®dom_RE, ®dom_RO, ®dom_RS, ®dom_RU, ®dom_RW,
|
||||
®dom_SA, ®dom_SE, ®dom_SG, ®dom_SI, ®dom_SK, ®dom_SN,
|
||||
®dom_SR, ®dom_SV, ®dom_SY, ®dom_TC, ®dom_TD, ®dom_TG,
|
||||
®dom_TH, ®dom_TN, ®dom_TR, ®dom_TT, ®dom_TW, ®dom_UA,
|
||||
®dom_UG, ®dom_US, ®dom_UY, ®dom_UZ, ®dom_VC, ®dom_VE,
|
||||
®dom_VI, ®dom_VN, ®dom_VU, ®dom_WF, ®dom_YE, ®dom_YT,
|
||||
®dom_ZA, ®dom_ZW, NULL,
|
||||
};
|
||||
|
||||
int reg_regdb_size = ARRAY_SIZE(reg_regdb);
|
||||
|
||||
|
||||
|
||||
@@ -24,10 +24,10 @@
|
||||
*/
|
||||
|
||||
int rwnx_bfmer_report_add(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta,
|
||||
unsigned int length)
|
||||
unsigned int length)
|
||||
{
|
||||
gfp_t flags;
|
||||
struct rwnx_bfmer_report *bfm_report ;
|
||||
struct rwnx_bfmer_report *bfm_report;
|
||||
|
||||
if (in_softirq())
|
||||
flags = GFP_ATOMIC;
|
||||
@@ -37,7 +37,6 @@ int rwnx_bfmer_report_add(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta,
|
||||
/* Allocate a structure that will contain the beamforming report */
|
||||
bfm_report = kmalloc(sizeof(*bfm_report) + length, flags);
|
||||
|
||||
|
||||
/* Check report allocation */
|
||||
if (!bfm_report) {
|
||||
/* Do not use beamforming */
|
||||
@@ -51,8 +50,8 @@ int rwnx_bfmer_report_add(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta,
|
||||
* Need to provide a Virtual Address to the MAC so that it can
|
||||
* upload the received Beamforming Report in driver memory
|
||||
*/
|
||||
bfm_report->dma_addr = dma_map_single(rwnx_hw->dev, &bfm_report->report[0],
|
||||
length, DMA_FROM_DEVICE);
|
||||
bfm_report->dma_addr = dma_map_single(
|
||||
rwnx_hw->dev, &bfm_report->report[0], length, DMA_FROM_DEVICE);
|
||||
|
||||
/* Check DMA mapping result */
|
||||
if (dma_mapping_error(rwnx_hw->dev, bfm_report->dma_addr)) {
|
||||
@@ -76,7 +75,7 @@ void rwnx_bfmer_report_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta)
|
||||
|
||||
/* Unmap DMA region */
|
||||
dma_unmap_single(rwnx_hw->dev, bfm_report->dma_addr,
|
||||
bfm_report->length, DMA_BIDIRECTIONAL);
|
||||
bfm_report->length, DMA_BIDIRECTIONAL);
|
||||
|
||||
/* Free allocated report structure and clean the pointer */
|
||||
kfree(bfm_report);
|
||||
|
||||
@@ -26,10 +26,10 @@
|
||||
*/
|
||||
|
||||
/// Maximal supported report length (in bytes)
|
||||
#define RWNX_BFMER_REPORT_MAX_LEN 2048
|
||||
#define RWNX_BFMER_REPORT_MAX_LEN 2048
|
||||
|
||||
/// Size of the allocated report space (twice the maximum report length)
|
||||
#define RWNX_BFMER_REPORT_SPACE_SIZE (RWNX_BFMER_REPORT_MAX_LEN * 2)
|
||||
#define RWNX_BFMER_REPORT_SPACE_SIZE (RWNX_BFMER_REPORT_MAX_LEN * 2)
|
||||
|
||||
/**
|
||||
* TYPE DEFINITIONS
|
||||
@@ -40,10 +40,10 @@
|
||||
* Structure used to store a beamforming report.
|
||||
*/
|
||||
struct rwnx_bfmer_report {
|
||||
dma_addr_t dma_addr; /* Virtual address provided to MAC for
|
||||
dma_addr_t dma_addr; /* Virtual address provided to MAC for
|
||||
DMA transfer of the Beamforming Report */
|
||||
unsigned int length; /* Report Length */
|
||||
u8 report[1]; /* Report to be used for VHT TX Beamforming */
|
||||
unsigned int length; /* Report Length */
|
||||
u8 report[1]; /* Report to be used for VHT TX Beamforming */
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -70,7 +70,7 @@ struct rwnx_bfmer_report {
|
||||
******************************************************************************
|
||||
*/
|
||||
int rwnx_bfmer_report_add(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta,
|
||||
unsigned int length);
|
||||
unsigned int length);
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
*
|
||||
*/
|
||||
static const char *rwnx_find_tag(const u8 *file_data, unsigned int file_size,
|
||||
const char *tag_name, unsigned int tag_len)
|
||||
const char *tag_name, unsigned int tag_len)
|
||||
{
|
||||
unsigned int curr, line_start = 0, line_size;
|
||||
|
||||
@@ -35,7 +35,8 @@ static const char *rwnx_find_tag(const u8 *file_data, unsigned int file_size,
|
||||
|
||||
/* Check if this line contains the expected tag */
|
||||
if ((line_size == (strlen(tag_name) + tag_len)) &&
|
||||
(!strncmp(&file_data[line_start], tag_name, strlen(tag_name))))
|
||||
(!strncmp(&file_data[line_start], tag_name,
|
||||
strlen(tag_name))))
|
||||
return &file_data[line_start + strlen(tag_name)];
|
||||
|
||||
/* Move to next line */
|
||||
@@ -50,7 +51,7 @@ static const char *rwnx_find_tag(const u8 *file_data, unsigned int file_size,
|
||||
* Parse the Config file used at init time
|
||||
*/
|
||||
int rwnx_parse_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
struct rwnx_conf_file *config)
|
||||
struct rwnx_conf_file *config)
|
||||
{
|
||||
const struct firmware *config_fw;
|
||||
u8 dflt_mac[ETH_ALEN] = { 0, 111, 111, 111, 111, 0 };
|
||||
@@ -61,19 +62,19 @@ int rwnx_parse_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
|
||||
ret = request_firmware(&config_fw, filename, rwnx_hw->dev);
|
||||
if (ret) {
|
||||
printk(KERN_CRIT "%s: Failed to get %s (%d)\n", __func__, filename, ret);
|
||||
printk(KERN_CRIT "%s: Failed to get %s (%d)\n", __func__,
|
||||
filename, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Get MAC Address */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"MAC_ADDR=", strlen("00:00:00:00:00:00"));
|
||||
"MAC_ADDR=", strlen("00:00:00:00:00:00"));
|
||||
if (tag_ptr != NULL) {
|
||||
u8 *addr = config->mac_addr;
|
||||
if (sscanf(tag_ptr,
|
||||
"%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
|
||||
addr + 0, addr + 1, addr + 2,
|
||||
addr + 3, addr + 4, addr + 5) != ETH_ALEN)
|
||||
if (sscanf(tag_ptr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", addr + 0,
|
||||
addr + 1, addr + 2, addr + 3, addr + 4,
|
||||
addr + 5) != ETH_ALEN)
|
||||
memcpy(config->mac_addr, dflt_mac, ETH_ALEN);
|
||||
} else
|
||||
memcpy(config->mac_addr, dflt_mac, ETH_ALEN);
|
||||
@@ -90,7 +91,7 @@ int rwnx_parse_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
* Parse the Config file used at init time
|
||||
*/
|
||||
int rwnx_parse_phy_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
struct rwnx_phy_conf_file *config, int path)
|
||||
struct rwnx_phy_conf_file *config, int path)
|
||||
{
|
||||
const struct firmware *config_fw;
|
||||
int ret;
|
||||
@@ -100,13 +101,14 @@ int rwnx_parse_phy_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
|
||||
ret = request_firmware(&config_fw, filename, rwnx_hw->dev);
|
||||
if (ret) {
|
||||
printk(KERN_CRIT "%s: Failed to get %s (%d)\n", __func__, filename, ret);
|
||||
printk(KERN_CRIT "%s: Failed to get %s (%d)\n", __func__,
|
||||
filename, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Get Trident path mapping */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"TRD_PATH_MAPPING=", strlen("00"));
|
||||
"TRD_PATH_MAPPING=", strlen("00"));
|
||||
if (tag_ptr != NULL) {
|
||||
u8 val;
|
||||
if (sscanf(tag_ptr, "%hhx", &val) == 1)
|
||||
@@ -120,106 +122,131 @@ int rwnx_parse_phy_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
|
||||
/* Get DC offset compensation */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"TX_DC_OFF_COMP=", strlen("00000000"));
|
||||
"TX_DC_OFF_COMP=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->trd.tx_dc_off_comp) != 1)
|
||||
config->trd.tx_dc_off_comp = 0;
|
||||
} else
|
||||
config->trd.tx_dc_off_comp = 0;
|
||||
|
||||
RWNX_DBG("TX DC offset compensation is: %08X\n", config->trd.tx_dc_off_comp);
|
||||
RWNX_DBG("TX DC offset compensation is: %08X\n",
|
||||
config->trd.tx_dc_off_comp);
|
||||
|
||||
/* Get Karst TX IQ compensation value for path0 on 2.4GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_2_4G_PATH_0=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_2_4G_PATH_0=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.tx_iq_comp_2_4G[0]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x",
|
||||
&config->karst.tx_iq_comp_2_4G[0]) != 1)
|
||||
config->karst.tx_iq_comp_2_4G[0] = 0x01000000;
|
||||
} else
|
||||
config->karst.tx_iq_comp_2_4G[0] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst TX IQ compensation for path 0 on 2.4GHz is: %08X\n", config->karst.tx_iq_comp_2_4G[0]);
|
||||
RWNX_DBG("Karst TX IQ compensation for path 0 on 2.4GHz is: %08X\n",
|
||||
config->karst.tx_iq_comp_2_4G[0]);
|
||||
|
||||
/* Get Karst TX IQ compensation value for path1 on 2.4GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_2_4G_PATH_1=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_2_4G_PATH_1=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.tx_iq_comp_2_4G[1]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x",
|
||||
&config->karst.tx_iq_comp_2_4G[1]) != 1)
|
||||
config->karst.tx_iq_comp_2_4G[1] = 0x01000000;
|
||||
} else
|
||||
config->karst.tx_iq_comp_2_4G[1] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst TX IQ compensation for path 1 on 2.4GHz is: %08X\n", config->karst.tx_iq_comp_2_4G[1]);
|
||||
RWNX_DBG("Karst TX IQ compensation for path 1 on 2.4GHz is: %08X\n",
|
||||
config->karst.tx_iq_comp_2_4G[1]);
|
||||
|
||||
/* Get Karst RX IQ compensation value for path0 on 2.4GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_2_4G_PATH_0=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_2_4G_PATH_0=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.rx_iq_comp_2_4G[0]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x",
|
||||
&config->karst.rx_iq_comp_2_4G[0]) != 1)
|
||||
config->karst.rx_iq_comp_2_4G[0] = 0x01000000;
|
||||
} else
|
||||
config->karst.rx_iq_comp_2_4G[0] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst RX IQ compensation for path 0 on 2.4GHz is: %08X\n", config->karst.rx_iq_comp_2_4G[0]);
|
||||
RWNX_DBG("Karst RX IQ compensation for path 0 on 2.4GHz is: %08X\n",
|
||||
config->karst.rx_iq_comp_2_4G[0]);
|
||||
|
||||
/* Get Karst RX IQ compensation value for path1 on 2.4GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_2_4G_PATH_1=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_2_4G_PATH_1=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.rx_iq_comp_2_4G[1]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x",
|
||||
&config->karst.rx_iq_comp_2_4G[1]) != 1)
|
||||
config->karst.rx_iq_comp_2_4G[1] = 0x01000000;
|
||||
} else
|
||||
config->karst.rx_iq_comp_2_4G[1] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst RX IQ compensation for path 1 on 2.4GHz is: %08X\n", config->karst.rx_iq_comp_2_4G[1]);
|
||||
RWNX_DBG("Karst RX IQ compensation for path 1 on 2.4GHz is: %08X\n",
|
||||
config->karst.rx_iq_comp_2_4G[1]);
|
||||
|
||||
/* Get Karst TX IQ compensation value for path0 on 5GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_5G_PATH_0=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_5G_PATH_0=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.tx_iq_comp_5G[0]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.tx_iq_comp_5G[0]) !=
|
||||
1)
|
||||
config->karst.tx_iq_comp_5G[0] = 0x01000000;
|
||||
} else
|
||||
config->karst.tx_iq_comp_5G[0] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst TX IQ compensation for path 0 on 5GHz is: %08X\n", config->karst.tx_iq_comp_5G[0]);
|
||||
RWNX_DBG("Karst TX IQ compensation for path 0 on 5GHz is: %08X\n",
|
||||
config->karst.tx_iq_comp_5G[0]);
|
||||
|
||||
/* Get Karst TX IQ compensation value for path1 on 5GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_5G_PATH_1=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_TX_IQ_COMP_5G_PATH_1=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.tx_iq_comp_5G[1]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.tx_iq_comp_5G[1]) !=
|
||||
1)
|
||||
config->karst.tx_iq_comp_5G[1] = 0x01000000;
|
||||
} else
|
||||
config->karst.tx_iq_comp_5G[1] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst TX IQ compensation for path 1 on 5GHz is: %08X\n", config->karst.tx_iq_comp_5G[1]);
|
||||
RWNX_DBG("Karst TX IQ compensation for path 1 on 5GHz is: %08X\n",
|
||||
config->karst.tx_iq_comp_5G[1]);
|
||||
|
||||
/* Get Karst RX IQ compensation value for path0 on 5GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_5G_PATH_0=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_5G_PATH_0=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.rx_iq_comp_5G[0]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.rx_iq_comp_5G[0]) !=
|
||||
1)
|
||||
config->karst.rx_iq_comp_5G[0] = 0x01000000;
|
||||
} else
|
||||
config->karst.rx_iq_comp_5G[0] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst RX IQ compensation for path 0 on 5GHz is: %08X\n", config->karst.rx_iq_comp_5G[0]);
|
||||
RWNX_DBG("Karst RX IQ compensation for path 0 on 5GHz is: %08X\n",
|
||||
config->karst.rx_iq_comp_5G[0]);
|
||||
|
||||
/* Get Karst RX IQ compensation value for path1 on 5GHz */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_5G_PATH_1=", strlen("00000000"));
|
||||
tag_ptr = rwnx_find_tag(
|
||||
config_fw->data, config_fw->size,
|
||||
"KARST_RX_IQ_COMP_5G_PATH_1=", strlen("00000000"));
|
||||
if (tag_ptr != NULL) {
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.rx_iq_comp_5G[1]) != 1)
|
||||
if (sscanf(tag_ptr, "%08x", &config->karst.rx_iq_comp_5G[1]) !=
|
||||
1)
|
||||
config->karst.rx_iq_comp_5G[1] = 0x01000000;
|
||||
} else
|
||||
config->karst.rx_iq_comp_5G[1] = 0x01000000;
|
||||
|
||||
RWNX_DBG("Karst RX IQ compensation for path 1 on 5GHz is: %08X\n", config->karst.rx_iq_comp_5G[1]);
|
||||
RWNX_DBG("Karst RX IQ compensation for path 1 on 5GHz is: %08X\n",
|
||||
config->karst.rx_iq_comp_5G[1]);
|
||||
|
||||
/* Get Karst default path */
|
||||
tag_ptr = rwnx_find_tag(config_fw->data, config_fw->size,
|
||||
"KARST_DEFAULT_PATH=", strlen("00"));
|
||||
"KARST_DEFAULT_PATH=", strlen("00"));
|
||||
if (tag_ptr != NULL) {
|
||||
u8 val;
|
||||
if (sscanf(tag_ptr, "%hhx", &val) == 1)
|
||||
@@ -236,4 +263,3 @@ int rwnx_parse_phy_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -27,9 +27,9 @@ struct rwnx_phy_conf_file {
|
||||
};
|
||||
|
||||
int rwnx_parse_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
struct rwnx_conf_file *config);
|
||||
struct rwnx_conf_file *config);
|
||||
|
||||
int rwnx_parse_phy_configfile(struct rwnx_hw *rwnx_hw, const char *filename,
|
||||
struct rwnx_phy_conf_file *config, int path);
|
||||
struct rwnx_phy_conf_file *config, int path);
|
||||
|
||||
#endif /* _RWNX_CFGFILE_H_ */
|
||||
|
||||
@@ -27,15 +27,19 @@
|
||||
/**
|
||||
*
|
||||
*/
|
||||
extern int aicwf_sdio_writeb(struct aic_sdio_dev *sdiodev, uint regaddr, u8 val);
|
||||
extern int aicwf_sdio_writeb(struct aic_sdio_dev *sdiodev, uint regaddr,
|
||||
u8 val);
|
||||
|
||||
void rwnx_cmd_free(struct rwnx_cmd *cmd);
|
||||
|
||||
static void cmd_dump(const struct rwnx_cmd *cmd)
|
||||
{
|
||||
printk(KERN_CRIT "tkn[%d] flags:%04x result:%3d cmd:%4d-%-24s - reqcfm(%4d-%-s)\n",
|
||||
cmd->tkn, cmd->flags, cmd->result, cmd->id, RWNX_ID2STR(cmd->id),
|
||||
cmd->reqid, cmd->reqid != (lmac_msg_id_t)-1 ? RWNX_ID2STR(cmd->reqid) : "none");
|
||||
printk(KERN_CRIT
|
||||
"tkn[%d] flags:%04x result:%3d cmd:%4d-%-24s - reqcfm(%4d-%-s)\n",
|
||||
cmd->tkn, cmd->flags, cmd->result, cmd->id, RWNX_ID2STR(cmd->id),
|
||||
cmd->reqid,
|
||||
cmd->reqid != (lmac_msg_id_t)-1 ? RWNX_ID2STR(cmd->reqid) :
|
||||
"none");
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -46,12 +50,12 @@ static void cmd_complete(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
//RWNX_DBG(RWNX_FN_ENTRY_STR);
|
||||
lockdep_assert_held(&cmd_mgr->lock);
|
||||
|
||||
list_del(&cmd->list);
|
||||
cmd_mgr->queue_sz--;
|
||||
//list_del(&cmd->list);
|
||||
//cmd_mgr->queue_sz--;
|
||||
|
||||
cmd->flags |= RWNX_CMD_FLAG_DONE;
|
||||
if (cmd->flags & RWNX_CMD_FLAG_NONBLOCK) {
|
||||
rwnx_cmd_free(cmd);//kfree(cmd);
|
||||
rwnx_cmd_free(cmd); //kfree(cmd);
|
||||
} else {
|
||||
if (RWNX_CMD_WAIT_COMPLETE(cmd->flags)) {
|
||||
cmd->result = 0;
|
||||
@@ -60,7 +64,8 @@ static void cmd_complete(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
}
|
||||
}
|
||||
|
||||
int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr,
|
||||
struct rwnx_cmd *cmd)
|
||||
{
|
||||
bool defer_push = false;
|
||||
|
||||
@@ -71,23 +76,23 @@ int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
|
||||
if (cmd_mgr->state == RWNX_CMD_MGR_STATE_CRASHED) {
|
||||
printk(KERN_CRIT"cmd queue crashed\n");
|
||||
printk(KERN_CRIT "cmd queue crashed\n");
|
||||
cmd->result = -EPIPE;
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
return -EPIPE;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_RWNX_FHOST
|
||||
#ifndef CONFIG_RWNX_FHOST
|
||||
if (!list_empty(&cmd_mgr->cmds)) {
|
||||
if (cmd_mgr->queue_sz == cmd_mgr->max_queue_sz) {
|
||||
printk(KERN_CRIT"Too many cmds (%d) already queued\n",
|
||||
cmd_mgr->max_queue_sz);
|
||||
printk(KERN_CRIT "Too many cmds (%d) already queued\n",
|
||||
cmd_mgr->max_queue_sz);
|
||||
cmd->result = -ENOMEM;
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
cmd->flags |= RWNX_CMD_FLAG_WAIT_PUSH;
|
||||
defer_push = true;
|
||||
@@ -95,7 +100,7 @@ int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd
|
||||
if (cmd->flags & RWNX_CMD_FLAG_REQ_CFM)
|
||||
cmd->flags |= RWNX_CMD_FLAG_WAIT_CFM;
|
||||
|
||||
cmd->tkn = cmd_mgr->next_tkn++;
|
||||
cmd->tkn = cmd_mgr->next_tkn++;
|
||||
cmd->result = -EINTR;
|
||||
|
||||
if (!(cmd->flags & RWNX_CMD_FLAG_NONBLOCK))
|
||||
@@ -109,43 +114,81 @@ int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if 1
|
||||
static void aic8800_start_system_reset_flow(struct aic_sdio_dev *aic)
|
||||
{
|
||||
int ret = 0;
|
||||
char *event_string = "DHDISDOWN=1";
|
||||
char *envp[] = { event_string, NULL };
|
||||
printk(KERN_ERR "wlan error reset flow.\n");
|
||||
printk(KERN_ERR "send event.\n");
|
||||
ret = kobject_uevent_env(&aic->dev->kobj, KOBJ_CHANGE, envp);
|
||||
if (!ret)
|
||||
printk(KERN_ERR "wlan error event send.\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static int cmd_mgr_queue(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
{
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
int ret;
|
||||
struct aic_sdio_dev *sdiodev = container_of(cmd_mgr, struct aic_sdio_dev, cmd_mgr);
|
||||
struct aic_sdio_dev *sdiodev =
|
||||
container_of(cmd_mgr, struct aic_sdio_dev, cmd_mgr);
|
||||
#endif
|
||||
#ifdef AICWF_USB_SUPPORT
|
||||
struct aic_usb_dev *usbdev = container_of(cmd_mgr, struct aic_usb_dev, cmd_mgr);
|
||||
struct aic_usb_dev *usbdev =
|
||||
container_of(cmd_mgr, struct aic_usb_dev, cmd_mgr);
|
||||
#endif
|
||||
bool defer_push = false;
|
||||
u8_l empty = 0;
|
||||
|
||||
//RWNX_DBG(RWNX_FN_ENTRY_STR);
|
||||
#ifdef CREATE_TRACE_POINTS
|
||||
trace_msg_send(cmd->id);
|
||||
#endif
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
if (cmd->e2a_msg != NULL) {
|
||||
do {
|
||||
if (cmd_mgr->state == RWNX_CMD_MGR_STATE_CRASHED)
|
||||
break;
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
empty = list_empty(&cmd_mgr->cmds);
|
||||
if (!empty) {
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
if (in_softirq()) {
|
||||
printk("in_softirq:check cmdqueue empty\n");
|
||||
mdelay(10);
|
||||
} else {
|
||||
printk("check cmdqueue empty\n");
|
||||
msleep(50);
|
||||
}
|
||||
}
|
||||
} while (!empty); //wait for cmd queue empty
|
||||
} else {
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
}
|
||||
|
||||
if (cmd_mgr->state == RWNX_CMD_MGR_STATE_CRASHED) {
|
||||
printk(KERN_CRIT"cmd queue crashed\n");
|
||||
printk(KERN_CRIT "cmd queue crashed\n");
|
||||
cmd->result = -EPIPE;
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
return -EPIPE;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_RWNX_FHOST
|
||||
#ifndef CONFIG_RWNX_FHOST
|
||||
if (!list_empty(&cmd_mgr->cmds)) {
|
||||
struct rwnx_cmd *last;
|
||||
|
||||
if (cmd_mgr->queue_sz == cmd_mgr->max_queue_sz) {
|
||||
printk(KERN_CRIT"Too many cmds (%d) already queued\n",
|
||||
cmd_mgr->max_queue_sz);
|
||||
printk(KERN_CRIT "Too many cmds (%d) already queued\n",
|
||||
cmd_mgr->max_queue_sz);
|
||||
cmd->result = -ENOMEM;
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
return -ENOMEM;
|
||||
}
|
||||
last = list_entry(cmd_mgr->cmds.prev, struct rwnx_cmd, list);
|
||||
if (last->flags & (RWNX_CMD_FLAG_WAIT_ACK | RWNX_CMD_FLAG_WAIT_PUSH | RWNX_CMD_FLAG_WAIT_CFM)) {
|
||||
if (last->flags &
|
||||
(RWNX_CMD_FLAG_WAIT_ACK | RWNX_CMD_FLAG_WAIT_PUSH |
|
||||
RWNX_CMD_FLAG_WAIT_CFM)) {
|
||||
#if 0 // queue even NONBLOCK command.
|
||||
if (cmd->flags & RWNX_CMD_FLAG_NONBLOCK) {
|
||||
printk(KERN_CRIT"cmd queue busy\n");
|
||||
@@ -158,7 +201,7 @@ static int cmd_mgr_queue(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
defer_push = true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
cmd->flags |= RWNX_CMD_FLAG_WAIT_ACK;
|
||||
@@ -166,7 +209,7 @@ static int cmd_mgr_queue(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
if (cmd->flags & RWNX_CMD_FLAG_REQ_CFM)
|
||||
cmd->flags |= RWNX_CMD_FLAG_WAIT_CFM;
|
||||
|
||||
cmd->tkn = cmd_mgr->next_tkn++;
|
||||
cmd->tkn = cmd_mgr->next_tkn++;
|
||||
cmd->result = -EINTR;
|
||||
|
||||
if (!(cmd->flags & RWNX_CMD_FLAG_NONBLOCK))
|
||||
@@ -176,9 +219,9 @@ static int cmd_mgr_queue(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
cmd_mgr->queue_sz++;
|
||||
|
||||
if (cmd->a2e_msg->id == ME_TRAFFIC_IND_REQ
|
||||
#ifdef AICWF_ARP_OFFLOAD
|
||||
|| cmd->a2e_msg->id == MM_SET_ARPOFFLOAD_REQ
|
||||
#endif
|
||||
#ifdef AICWF_ARP_OFFLOAD
|
||||
|| cmd->a2e_msg->id == MM_SET_ARPOFFLOAD_REQ
|
||||
#endif
|
||||
) {
|
||||
defer_push = true;
|
||||
cmd->flags |= RWNX_CMD_FLAG_WAIT_PUSH;
|
||||
@@ -187,24 +230,28 @@ static int cmd_mgr_queue(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
if (!defer_push) {
|
||||
//printk("queue:id=%x, param_len=%u\n",cmd->a2e_msg->id, cmd->a2e_msg->param_len);
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
aicwf_set_cmd_tx((void *)(sdiodev), cmd->a2e_msg, sizeof(struct lmac_msg) + cmd->a2e_msg->param_len);
|
||||
#else
|
||||
aicwf_set_cmd_tx((void *)(usbdev), cmd->a2e_msg, sizeof(struct lmac_msg) + cmd->a2e_msg->param_len);
|
||||
#endif
|
||||
//printk("queue:id=%x, param_len=%u\n",cmd->a2e_msg->id, cmd->a2e_msg->param_len);
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
aicwf_set_cmd_tx((void *)(sdiodev), cmd->a2e_msg,
|
||||
sizeof(struct lmac_msg) +
|
||||
cmd->a2e_msg->param_len);
|
||||
#else
|
||||
aicwf_set_cmd_tx((void *)(usbdev), cmd->a2e_msg,
|
||||
sizeof(struct lmac_msg) +
|
||||
cmd->a2e_msg->param_len);
|
||||
#endif
|
||||
//rwnx_ipc_msg_push(rwnx_hw, cmd, RWNX_CMD_A2EMSG_LEN(cmd->a2e_msg));
|
||||
|
||||
kfree(cmd->a2e_msg);
|
||||
} else {
|
||||
if(cmd_mgr->queue_sz <= 1){
|
||||
WAKE_CMD_WORK(cmd_mgr);
|
||||
}
|
||||
if (cmd_mgr->queue_sz <= 1) {
|
||||
WAKE_CMD_WORK(cmd_mgr);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!(cmd->flags & RWNX_CMD_FLAG_NONBLOCK)) {
|
||||
#ifdef CONFIG_RWNX_FHOST
|
||||
#ifdef CONFIG_RWNX_FHOST
|
||||
if (wait_for_completion_killable(&cmd->complete)) {
|
||||
cmd->result = -EINTR;
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
@@ -212,16 +259,21 @@ static int cmd_mgr_queue(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
/* TODO: kill the cmd at fw level */
|
||||
}
|
||||
#else
|
||||
unsigned long tout = msecs_to_jiffies(RWNX_80211_CMD_TIMEOUT_MS * cmd_mgr->queue_sz);
|
||||
#else
|
||||
unsigned long tout = msecs_to_jiffies(
|
||||
RWNX_80211_CMD_TIMEOUT_MS * cmd_mgr->queue_sz);
|
||||
if (!wait_for_completion_timeout(&cmd->complete, tout)) {
|
||||
printk(KERN_CRIT"cmd timed-out\n");
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
ret = aicwf_sdio_writeb(sdiodev, sdiodev->sdio_reg.wakeup_reg, 2);
|
||||
printk(KERN_CRIT "cmd timed-out\n");
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
ret = aicwf_sdio_writeb(
|
||||
sdiodev, sdiodev->sdio_reg.wakeup_reg, 2);
|
||||
if (ret < 0) {
|
||||
sdio_err("reg:%d write failed!\n", sdiodev->sdio_reg.wakeup_reg);
|
||||
sdio_err("reg:%d write failed!\n",
|
||||
sdiodev->sdio_reg.wakeup_reg);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
aic8800_start_system_reset_flow(sdiodev);
|
||||
|
||||
cmd_dump(cmd);
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
@@ -232,11 +284,15 @@ static int cmd_mgr_queue(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
}
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
} else {
|
||||
rwnx_cmd_free(cmd);//kfree(cmd);
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
list_del(&cmd->list);
|
||||
cmd_mgr->queue_sz--;
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
rwnx_cmd_free(cmd); //kfree(cmd);
|
||||
if (!list_empty(&cmd_mgr->cmds))
|
||||
WAKE_CMD_WORK(cmd_mgr);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
} else {
|
||||
cmd->result = 0;
|
||||
}
|
||||
@@ -254,7 +310,7 @@ static int cmd_mgr_llind(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
RWNX_DBG(RWNX_FN_ENTRY_STR);
|
||||
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
list_for_each_entry(cur, &cmd_mgr->cmds, list) {
|
||||
list_for_each_entry (cur, &cmd_mgr->cmds, list) {
|
||||
if (!acked) {
|
||||
if (cur->tkn == cmd->tkn) {
|
||||
if (WARN_ON_ONCE(cur != cmd)) {
|
||||
@@ -265,8 +321,8 @@ static int cmd_mgr_llind(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
}
|
||||
}
|
||||
if (cur->flags & RWNX_CMD_FLAG_WAIT_PUSH) {
|
||||
next = cur;
|
||||
break;
|
||||
next = cur;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!acked) {
|
||||
@@ -278,12 +334,12 @@ static int cmd_mgr_llind(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
}
|
||||
|
||||
if (next) {
|
||||
#if 0 //there is no ack
|
||||
#if 0 //there is no ack
|
||||
struct rwnx_hw *rwnx_hw = container_of(cmd_mgr, struct rwnx_hw, cmd_mgr);
|
||||
next->flags &= ~RWNX_CMD_FLAG_WAIT_PUSH;
|
||||
rwnx_ipc_msg_push(rwnx_hw, next, RWNX_CMD_A2EMSG_LEN(next->a2e_msg));
|
||||
kfree(next->a2e_msg);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
spin_unlock(&cmd_mgr->lock);
|
||||
|
||||
@@ -292,7 +348,8 @@ static int cmd_mgr_llind(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd)
|
||||
|
||||
void cmd_mgr_task_process(struct work_struct *work)
|
||||
{
|
||||
struct rwnx_cmd_mgr *cmd_mgr = container_of(work, struct rwnx_cmd_mgr, cmdWork);
|
||||
struct rwnx_cmd_mgr *cmd_mgr =
|
||||
container_of(work, struct rwnx_cmd_mgr, cmdWork);
|
||||
struct rwnx_cmd *cur, *next = NULL;
|
||||
unsigned long tout;
|
||||
|
||||
@@ -302,9 +359,10 @@ void cmd_mgr_task_process(struct work_struct *work)
|
||||
next = NULL;
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
|
||||
list_for_each_entry(cur, &cmd_mgr->cmds, list) {
|
||||
if (cur->flags & RWNX_CMD_FLAG_WAIT_PUSH) { //just judge the first
|
||||
next = cur;
|
||||
list_for_each_entry (cur, &cmd_mgr->cmds, list) {
|
||||
if (cur->flags &
|
||||
RWNX_CMD_FLAG_WAIT_PUSH) { //just judge the first
|
||||
next = cur;
|
||||
}
|
||||
break;
|
||||
}
|
||||
@@ -315,30 +373,44 @@ void cmd_mgr_task_process(struct work_struct *work)
|
||||
|
||||
if (next) {
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
struct aic_sdio_dev *sdiodev = container_of(cmd_mgr, struct aic_sdio_dev, cmd_mgr);
|
||||
struct aic_sdio_dev *sdiodev = container_of(
|
||||
cmd_mgr, struct aic_sdio_dev, cmd_mgr);
|
||||
#endif
|
||||
#ifdef AICWF_USB_SUPPORT
|
||||
struct aic_usb_dev *usbdev = container_of(cmd_mgr, struct aic_usb_dev, cmd_mgr);
|
||||
struct aic_usb_dev *usbdev = container_of(
|
||||
cmd_mgr, struct aic_usb_dev, cmd_mgr);
|
||||
#endif
|
||||
next->flags &= ~RWNX_CMD_FLAG_WAIT_PUSH;
|
||||
|
||||
//printk("cmd_process, cmd->id=%d, tkn=%d\r\n",next->reqid, next->tkn);
|
||||
//rwnx_ipc_msg_push(rwnx_hw, next, RWNX_CMD_A2EMSG_LEN(next->a2e_msg));
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
aicwf_set_cmd_tx((void *)(sdiodev), next->a2e_msg, sizeof(struct lmac_msg) + next->a2e_msg->param_len);
|
||||
aicwf_set_cmd_tx((void *)(sdiodev), next->a2e_msg,
|
||||
sizeof(struct lmac_msg) +
|
||||
next->a2e_msg->param_len);
|
||||
#else
|
||||
aicwf_set_cmd_tx((void *)(usbdev), next->a2e_msg, sizeof(struct lmac_msg) + next->a2e_msg->param_len);
|
||||
aicwf_set_cmd_tx((void *)(usbdev), next->a2e_msg,
|
||||
sizeof(struct lmac_msg) +
|
||||
next->a2e_msg->param_len);
|
||||
#endif
|
||||
kfree(next->a2e_msg);
|
||||
|
||||
tout = msecs_to_jiffies(RWNX_80211_CMD_TIMEOUT_MS * cmd_mgr->queue_sz);
|
||||
if (!wait_for_completion_timeout(&next->complete, tout)) {
|
||||
printk(KERN_CRIT"cmd timed-out\n");
|
||||
tout = msecs_to_jiffies(RWNX_80211_CMD_TIMEOUT_MS *
|
||||
cmd_mgr->queue_sz);
|
||||
if (!wait_for_completion_timeout(&next->complete,
|
||||
tout)) {
|
||||
printk(KERN_CRIT "cmd timed-out\n");
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
if (aicwf_sdio_writeb(sdiodev, sdiodev->sdio_reg.wakeup_reg, 2) < 0) {
|
||||
sdio_err("reg:%d write failed!\n", sdiodev->sdio_reg.wakeup_reg);
|
||||
if (aicwf_sdio_writeb(
|
||||
sdiodev,
|
||||
sdiodev->sdio_reg.wakeup_reg,
|
||||
2) < 0) {
|
||||
sdio_err("reg:%d write failed!\n",
|
||||
sdiodev->sdio_reg.wakeup_reg);
|
||||
}
|
||||
#endif
|
||||
aic8800_start_system_reset_flow(sdiodev);
|
||||
|
||||
cmd_dump(next);
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
cmd_mgr->state = RWNX_CMD_MGR_STATE_CRASHED;
|
||||
@@ -347,16 +419,19 @@ void cmd_mgr_task_process(struct work_struct *work)
|
||||
cmd_complete(cmd_mgr, next);
|
||||
}
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
} else
|
||||
rwnx_cmd_free(next);//kfree(next);
|
||||
} else {
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
list_del(&next->list);
|
||||
cmd_mgr->queue_sz--;
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
rwnx_cmd_free(next); //kfree(next);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
static int cmd_mgr_run_callback(struct rwnx_hw *rwnx_hw, struct rwnx_cmd *cmd,
|
||||
struct rwnx_cmd_e2amsg *msg, msg_cb_fct cb)
|
||||
struct rwnx_cmd_e2amsg *msg, msg_cb_fct cb)
|
||||
{
|
||||
int res;
|
||||
|
||||
@@ -375,15 +450,17 @@ static int cmd_mgr_run_callback(struct rwnx_hw *rwnx_hw, struct rwnx_cmd *cmd,
|
||||
*
|
||||
|
||||
*/
|
||||
static int cmd_mgr_msgind(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd_e2amsg *msg,
|
||||
msg_cb_fct cb)
|
||||
static int cmd_mgr_msgind(struct rwnx_cmd_mgr *cmd_mgr,
|
||||
struct rwnx_cmd_e2amsg *msg, msg_cb_fct cb)
|
||||
{
|
||||
#ifdef AICWF_SDIO_SUPPORT
|
||||
struct aic_sdio_dev *sdiodev = container_of(cmd_mgr, struct aic_sdio_dev, cmd_mgr);
|
||||
struct aic_sdio_dev *sdiodev =
|
||||
container_of(cmd_mgr, struct aic_sdio_dev, cmd_mgr);
|
||||
struct rwnx_hw *rwnx_hw = sdiodev->rwnx_hw;
|
||||
#endif
|
||||
#ifdef AICWF_USB_SUPPORT
|
||||
struct aic_usb_dev *usbdev = container_of(cmd_mgr, struct aic_usb_dev, cmd_mgr);
|
||||
struct aic_usb_dev *usbdev =
|
||||
container_of(cmd_mgr, struct aic_usb_dev, cmd_mgr);
|
||||
struct rwnx_hw *rwnx_hw = usbdev->rwnx_hw;
|
||||
#endif
|
||||
struct rwnx_cmd *cmd, *pos;
|
||||
@@ -395,22 +472,25 @@ static int cmd_mgr_msgind(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd_e2amsg *
|
||||
#endif
|
||||
//printk("cmd->id=%x\n", msg->id);
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
list_for_each_entry_safe(cmd, pos, &cmd_mgr->cmds, list) {
|
||||
list_for_each_entry_safe (cmd, pos, &cmd_mgr->cmds, list) {
|
||||
if (cmd->reqid == msg->id &&
|
||||
(cmd->flags & RWNX_CMD_FLAG_WAIT_CFM)) {
|
||||
|
||||
(cmd->flags & RWNX_CMD_FLAG_WAIT_CFM)) {
|
||||
if (!cmd_mgr_run_callback(rwnx_hw, cmd, msg, cb)) {
|
||||
found = true;
|
||||
cmd->flags &= ~RWNX_CMD_FLAG_WAIT_CFM;
|
||||
|
||||
if (WARN((msg->param_len > RWNX_CMD_E2AMSG_LEN_MAX),
|
||||
"Unexpect E2A msg len %d > %d\n", msg->param_len,
|
||||
RWNX_CMD_E2AMSG_LEN_MAX)) {
|
||||
msg->param_len = RWNX_CMD_E2AMSG_LEN_MAX;
|
||||
if (WARN((msg->param_len >
|
||||
RWNX_CMD_E2AMSG_LEN_MAX),
|
||||
"Unexpect E2A msg len %d > %d\n",
|
||||
msg->param_len,
|
||||
RWNX_CMD_E2AMSG_LEN_MAX)) {
|
||||
msg->param_len =
|
||||
RWNX_CMD_E2AMSG_LEN_MAX;
|
||||
}
|
||||
|
||||
if (cmd->e2a_msg && msg->param_len)
|
||||
memcpy(cmd->e2a_msg, &msg->param, msg->param_len);
|
||||
memcpy(cmd->e2a_msg, &msg->param,
|
||||
msg->param_len);
|
||||
|
||||
if (RWNX_CMD_WAIT_COMPLETE(cmd->flags))
|
||||
cmd_complete(cmd_mgr, cmd);
|
||||
@@ -435,10 +515,9 @@ static void cmd_mgr_print(struct rwnx_cmd_mgr *cmd_mgr)
|
||||
struct rwnx_cmd *cur;
|
||||
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
RWNX_DBG("q_sz/max: %2d / %2d - next tkn: %d\n",
|
||||
cmd_mgr->queue_sz, cmd_mgr->max_queue_sz,
|
||||
cmd_mgr->next_tkn);
|
||||
list_for_each_entry(cur, &cmd_mgr->cmds, list) {
|
||||
RWNX_DBG("q_sz/max: %2d / %2d - next tkn: %d\n", cmd_mgr->queue_sz,
|
||||
cmd_mgr->max_queue_sz, cmd_mgr->next_tkn);
|
||||
list_for_each_entry (cur, &cmd_mgr->cmds, list) {
|
||||
cmd_dump(cur);
|
||||
}
|
||||
spin_unlock_bh(&cmd_mgr->lock);
|
||||
@@ -451,7 +530,7 @@ static void cmd_mgr_drain(struct rwnx_cmd_mgr *cmd_mgr)
|
||||
RWNX_DBG(RWNX_FN_ENTRY_STR);
|
||||
|
||||
spin_lock_bh(&cmd_mgr->lock);
|
||||
list_for_each_entry_safe(cur, nxt, &cmd_mgr->cmds, list) {
|
||||
list_for_each_entry_safe (cur, nxt, &cmd_mgr->cmds, list) {
|
||||
list_del(&cur->list);
|
||||
cmd_mgr->queue_sz--;
|
||||
if (!(cur->flags & RWNX_CMD_FLAG_NONBLOCK))
|
||||
@@ -468,10 +547,10 @@ void rwnx_cmd_mgr_init(struct rwnx_cmd_mgr *cmd_mgr)
|
||||
cmd_mgr->state = RWNX_CMD_MGR_STATE_INITED;
|
||||
spin_lock_init(&cmd_mgr->lock);
|
||||
cmd_mgr->max_queue_sz = RWNX_CMD_MAX_QUEUED;
|
||||
cmd_mgr->queue = &cmd_mgr_queue;
|
||||
cmd_mgr->print = &cmd_mgr_print;
|
||||
cmd_mgr->drain = &cmd_mgr_drain;
|
||||
cmd_mgr->llind = &cmd_mgr_llind;
|
||||
cmd_mgr->queue = &cmd_mgr_queue;
|
||||
cmd_mgr->print = &cmd_mgr_print;
|
||||
cmd_mgr->drain = &cmd_mgr_drain;
|
||||
cmd_mgr->llind = &cmd_mgr_llind;
|
||||
cmd_mgr->msgind = &cmd_mgr_msgind;
|
||||
|
||||
INIT_WORK(&cmd_mgr->cmdWork, cmd_mgr_task_process);
|
||||
@@ -511,14 +590,16 @@ void aicwf_set_cmd_tx(void *dev, struct lmac_msg *msg, uint len)
|
||||
buffer = bus->cmd_buf;
|
||||
|
||||
memset(buffer, 0, CMD_BUF_MAX);
|
||||
buffer[0] = (len+4) & 0x00ff;
|
||||
buffer[1] = ((len+4) >> 8) &0x0f;
|
||||
buffer[0] = (len + 4) & 0x00ff;
|
||||
buffer[1] = ((len + 4) >> 8) & 0x0f;
|
||||
buffer[2] = 0x11;
|
||||
if (sdiodev->chipid == PRODUCT_ID_AIC8801 || sdiodev->chipid == PRODUCT_ID_AIC8800DC ||
|
||||
sdiodev->chipid == PRODUCT_ID_AIC8800DW)
|
||||
buffer[3] = 0x0;
|
||||
else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80)
|
||||
buffer[3] = crc8_ponl_107(&buffer[0], 3); // crc8
|
||||
if (sdiodev->chipid == PRODUCT_ID_AIC8801 ||
|
||||
sdiodev->chipid == PRODUCT_ID_AIC8800DC ||
|
||||
sdiodev->chipid == PRODUCT_ID_AIC8800DW)
|
||||
buffer[3] = 0x0;
|
||||
else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80 ||
|
||||
sdiodev->chipid == PRODUCT_ID_AIC8800D80X2)
|
||||
buffer[3] = crc8_ponl_107(&buffer[0], 3); // crc8
|
||||
index += 4;
|
||||
//there is a dummy word
|
||||
index += 4;
|
||||
@@ -536,4 +617,3 @@ void aicwf_set_cmd_tx(void *dev, struct lmac_msg *msg, uint len)
|
||||
|
||||
aicwf_bus_txmsg(bus, buffer, len + 8);
|
||||
}
|
||||
|
||||
|
||||
@@ -17,29 +17,29 @@
|
||||
#include "lmac_msg.h"
|
||||
|
||||
#ifdef CONFIG_RWNX_SDM
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS (20 * 300)
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS (20 * 300)
|
||||
#elif defined(CONFIG_RWNX_FHOST)
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS (10000)
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS (10000)
|
||||
#else
|
||||
#ifdef AICWF_USB_SUPPORT
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS 2000//300
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS 2000 //300
|
||||
#else
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS 3000//500//300
|
||||
#define RWNX_80211_CMD_TIMEOUT_MS 6000 //500//300
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define RWNX_CMD_FLAG_NONBLOCK BIT(0)
|
||||
#define RWNX_CMD_FLAG_REQ_CFM BIT(1)
|
||||
#define RWNX_CMD_FLAG_WAIT_PUSH BIT(2)
|
||||
#define RWNX_CMD_FLAG_WAIT_ACK BIT(3)
|
||||
#define RWNX_CMD_FLAG_WAIT_CFM BIT(4)
|
||||
#define RWNX_CMD_FLAG_DONE BIT(5)
|
||||
#define RWNX_CMD_FLAG_NONBLOCK BIT(0)
|
||||
#define RWNX_CMD_FLAG_REQ_CFM BIT(1)
|
||||
#define RWNX_CMD_FLAG_WAIT_PUSH BIT(2)
|
||||
#define RWNX_CMD_FLAG_WAIT_ACK BIT(3)
|
||||
#define RWNX_CMD_FLAG_WAIT_CFM BIT(4)
|
||||
#define RWNX_CMD_FLAG_DONE BIT(5)
|
||||
/* ATM IPC design makes it possible to get the CFM before the ACK,
|
||||
* otherwise this could have simply been a state enum */
|
||||
#define RWNX_CMD_WAIT_COMPLETE(flags) \
|
||||
#define RWNX_CMD_WAIT_COMPLETE(flags) \
|
||||
(!(flags & (RWNX_CMD_FLAG_WAIT_ACK | RWNX_CMD_FLAG_WAIT_CFM)))
|
||||
|
||||
#define RWNX_CMD_MAX_QUEUED 16
|
||||
#define RWNX_CMD_MAX_QUEUED 16
|
||||
|
||||
#ifdef CONFIG_RWNX_FHOST
|
||||
#include "ipc_fhost.h"
|
||||
@@ -61,11 +61,11 @@ struct rwnx_term_stream;
|
||||
struct rwnx_hw;
|
||||
struct rwnx_cmd;
|
||||
typedef int (*msg_cb_fct)(struct rwnx_hw *rwnx_hw, struct rwnx_cmd *cmd,
|
||||
struct rwnx_cmd_e2amsg *msg);
|
||||
struct rwnx_cmd_e2amsg *msg);
|
||||
static inline void put_u16(u8 *buf, u16 data)
|
||||
{
|
||||
buf[0] = (u8)(data&0x00ff);
|
||||
buf[1] = (u8)((data >> 8)&0x00ff);
|
||||
buf[0] = (u8)(data & 0x00ff);
|
||||
buf[1] = (u8)((data >> 8) & 0x00ff);
|
||||
}
|
||||
|
||||
enum rwnx_cmd_mgr_state {
|
||||
@@ -87,9 +87,9 @@ struct rwnx_cmd {
|
||||
u32 result;
|
||||
u8 used;
|
||||
int array_id;
|
||||
#ifdef CONFIG_RWNX_FHOST
|
||||
#ifdef CONFIG_RWNX_FHOST
|
||||
struct rwnx_term_stream *stream;
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
struct rwnx_cmd_mgr {
|
||||
@@ -101,9 +101,10 @@ struct rwnx_cmd_mgr {
|
||||
|
||||
struct list_head cmds;
|
||||
|
||||
int (*queue)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*llind)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*msgind)(struct rwnx_cmd_mgr *, struct rwnx_cmd_e2amsg *, msg_cb_fct);
|
||||
int (*queue)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*llind)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
|
||||
int (*msgind)(struct rwnx_cmd_mgr *, struct rwnx_cmd_e2amsg *,
|
||||
msg_cb_fct);
|
||||
void (*print)(struct rwnx_cmd_mgr *);
|
||||
void (*drain)(struct rwnx_cmd_mgr *);
|
||||
|
||||
@@ -111,14 +112,15 @@ struct rwnx_cmd_mgr {
|
||||
struct workqueue_struct *cmd_wq;
|
||||
};
|
||||
|
||||
#define WAKE_CMD_WORK(cmd_mgr) \
|
||||
do { \
|
||||
queue_work((cmd_mgr)->cmd_wq, &cmd_mgr->cmdWork); \
|
||||
#define WAKE_CMD_WORK(cmd_mgr) \
|
||||
do { \
|
||||
queue_work((cmd_mgr)->cmd_wq, &cmd_mgr->cmdWork); \
|
||||
} while (0)
|
||||
|
||||
void rwnx_cmd_mgr_init(struct rwnx_cmd_mgr *cmd_mgr);
|
||||
void rwnx_cmd_mgr_deinit(struct rwnx_cmd_mgr *cmd_mgr);
|
||||
int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd);
|
||||
int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr,
|
||||
struct rwnx_cmd *cmd);
|
||||
void aicwf_set_cmd_tx(void *dev, struct lmac_msg *msg, uint len);
|
||||
|
||||
#endif /* _RWNX_CMDS_H_ */
|
||||
|
||||
@@ -30,7 +30,7 @@
|
||||
/* Generic */
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)
|
||||
#define __bf_shf(x) (__builtin_ffsll(x) - 1)
|
||||
#define FIELD_PREP(_mask, _val) \
|
||||
#define FIELD_PREP(_mask, _val) \
|
||||
(((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask))
|
||||
#else
|
||||
#include <linux/bitfield.h>
|
||||
@@ -51,17 +51,19 @@
|
||||
#define HIGH_KERNEL_VERSION4 KERNEL_VERSION(6, 3, 0)
|
||||
#endif
|
||||
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 60)
|
||||
#define IEEE80211_MAX_AMPDU_BUF IEEE80211_MAX_AMPDU_BUF_HE
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB
|
||||
#define IEEE80211_HE_PHY_CAP3_RX_HE_MU_PPDU_FROM_NON_AP_STA IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU
|
||||
#define IEEE80211_MAX_AMPDU_BUF IEEE80211_MAX_AMPDU_BUF_HE
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB \
|
||||
IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB
|
||||
#define IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB \
|
||||
IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB
|
||||
#define IEEE80211_HE_PHY_CAP3_RX_HE_MU_PPDU_FROM_NON_AP_STA \
|
||||
IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU
|
||||
#endif
|
||||
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
|
||||
#define IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK IEEE80211_HE_MAC_CAP3_MAX_A_AMPDU_LEN_EXP_MASK
|
||||
#define IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK \
|
||||
IEEE80211_HE_MAC_CAP3_MAX_A_AMPDU_LEN_EXP_MASK
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)
|
||||
@@ -73,87 +75,87 @@ struct ieee80211_radiotap_he {
|
||||
};
|
||||
|
||||
enum ieee80211_radiotap_he_bits {
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 0x0004,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 0x0008,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 0x0020,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 0x0100,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 0x0200,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 0x0400,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 0x0800,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 0x1000,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 0x2000,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 0x8000,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 0x0004,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 0x0008,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 0x0020,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 0x0100,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 0x0200,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 0x0400,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 0x0800,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 0x1000,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 0x2000,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 0x8000,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 0x0001,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 0x0002,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 0x0004,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 0x0008,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 0x0020,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 0x3f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 0x8000,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 0x0001,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 0x0002,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 0x0004,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 0x0008,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 0x0020,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 0x3f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 0x8000,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 0x003f,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_UL_DL = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 0x0f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 0x1000,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_CODING = 0x2000,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_STBC = 0x8000,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 0x003f,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_UL_DL = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 0x0f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 0x1000,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_CODING = 0x2000,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA3_STBC = 0x8000,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 0x7ff0,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 0x00f0,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 0x0f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 0xf000,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 0x7ff0,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 0x00f0,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 0x0f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 0xf000,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI = 0x0030,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI = 0x0030,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 0x00c0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 0x0700,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 0x3000,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_TXBF = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 0x8000,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 0x00c0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 0x0700,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 0x3000,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_TXBF = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 0x8000,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_DATA6_NSTS = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_DATA6_TXOP = 0x7f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 0x8000,
|
||||
IEEE80211_RADIOTAP_HE_DATA6_NSTS = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_DATA6_TXOP = 0x7f00,
|
||||
IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 0x8000,
|
||||
};
|
||||
|
||||
struct ieee80211_radiotap_he_mu {
|
||||
@@ -163,42 +165,43 @@ struct ieee80211_radiotap_he_mu {
|
||||
};
|
||||
|
||||
enum ieee80211_radiotap_he_mu_bits {
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM = 0x0020,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN = 0x0100,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN = 0x0200,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN = 0x1000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU = 0x2000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN = 0x8000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS = 0x000f,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN = 0x0010,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM = 0x0020,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN = 0x0040,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN = 0x0080,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN = 0x0100,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN = 0x0200,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN = 0x1000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU = 0x2000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN = 0x4000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN = 0x8000,
|
||||
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW = 0x0003,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_20MHZ = 0x0000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_40MHZ = 0x0001,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_80MHZ = 0x0002,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_160MHZ = 0x0003,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN = 0x0004,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP = 0x0008,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS = 0x00f0,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW = 0x0300,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW = 0x0003,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_20MHZ = 0x0000,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_40MHZ = 0x0001,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_80MHZ = 0x0002,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_160MHZ = 0x0003,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN = 0x0004,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP = 0x0008,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS = 0x00f0,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW = 0x0300,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN = 0x0400,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU = 0x0800,
|
||||
IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU = 0x0800,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)
|
||||
#define rwnx_cfg80211_add_iface(wiphy, name, name_assign_type, type, params) \
|
||||
#define rwnx_cfg80211_add_iface(wiphy, name, name_assign_type, type, params) \
|
||||
rwnx_cfg80211_add_iface(wiphy, name, type, u32 *flags, params)
|
||||
#else
|
||||
#define rwnx_cfg80211_add_iface(wiphy, name, name_assign_type, type, params) \
|
||||
rwnx_cfg80211_add_iface(wiphy, name, name_assign_type, type, u32 *flags, params)
|
||||
#define rwnx_cfg80211_add_iface(wiphy, name, name_assign_type, type, params) \
|
||||
rwnx_cfg80211_add_iface(wiphy, name, name_assign_type, type, \
|
||||
u32 *flags, params)
|
||||
#endif
|
||||
|
||||
#define rwnx_cfg80211_change_iface(wiphy, dev, type, params) \
|
||||
#define rwnx_cfg80211_change_iface(wiphy, dev, type, params) \
|
||||
rwnx_cfg80211_change_iface(wiphy, dev, type, u32 *flags, params)
|
||||
|
||||
#define CCFS0(vht) vht->center_freq_seg1_idx
|
||||
@@ -211,34 +214,36 @@ enum ieee80211_radiotap_he_mu_bits {
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0)
|
||||
#define cfg80211_cqm_rssi_notify(dev, event, level, gfp) \
|
||||
#define cfg80211_cqm_rssi_notify(dev, event, level, gfp) \
|
||||
cfg80211_cqm_rssi_notify(dev, event, gfp)
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)
|
||||
#define ieee80211_amsdu_to_8023s(skb, list, addr, iftype, extra_headroom, check_da, check_sa) \
|
||||
#define ieee80211_amsdu_to_8023s(skb, list, addr, iftype, extra_headroom, \
|
||||
check_da, check_sa) \
|
||||
ieee80211_amsdu_to_8023s(skb, list, addr, iftype, extra_headroom, false)
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)
|
||||
#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)
|
||||
#define cfg80211_disconnected(dev, reason, ie, len, local, gfp) \
|
||||
#define cfg80211_disconnected(dev, reason, ie, len, local, gfp) \
|
||||
cfg80211_disconnected(dev, reason, ie, len, gfp)
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) && !(defined CONFIG_VENDOR_RWNX)
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) && \
|
||||
!(defined CONFIG_VENDOR_RWNX)
|
||||
#define ieee80211_chandef_to_operating_class(chan_def, op_class) 0
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)
|
||||
#define SURVEY_INFO_TIME SURVEY_INFO_CHANNEL_TIME
|
||||
#define SURVEY_INFO_TIME_BUSY SURVEY_INFO_CHANNEL_TIME_BUSY
|
||||
#define SURVEY_INFO_TIME SURVEY_INFO_CHANNEL_TIME
|
||||
#define SURVEY_INFO_TIME_BUSY SURVEY_INFO_CHANNEL_TIME_BUSY
|
||||
#define SURVEY_INFO_TIME_EXT_BUSY SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
|
||||
#define SURVEY_INFO_TIME_RX SURVEY_INFO_CHANNEL_TIME_RX
|
||||
#define SURVEY_INFO_TIME_TX SURVEY_INFO_CHANNEL_TIME_TX
|
||||
#define SURVEY_INFO_TIME_RX SURVEY_INFO_CHANNEL_TIME_RX
|
||||
#define SURVEY_INFO_TIME_TX SURVEY_INFO_CHANNEL_TIME_TX
|
||||
|
||||
#define SURVEY_TIME(s) s->channel_time
|
||||
#define SURVEY_TIME_BUSY(s) s->channel_time_busy
|
||||
@@ -250,37 +255,43 @@ enum ieee80211_radiotap_he_mu_bits {
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)
|
||||
#define cfg80211_ch_switch_started_notify(dev, chandef, count)
|
||||
|
||||
#define WLAN_BSS_COEX_INFORMATION_REQUEST BIT(0)
|
||||
#define WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING BIT(2)
|
||||
#define WLAN_EXT_CAPA4_TDLS_BUFFER_STA BIT(4)
|
||||
#define WLAN_EXT_CAPA4_TDLS_PEER_PSM BIT(5)
|
||||
#define WLAN_EXT_CAPA4_TDLS_CHAN_SWITCH BIT(6)
|
||||
#define WLAN_EXT_CAPA5_TDLS_CH_SW_PROHIBITED BIT(7)
|
||||
#define NL80211_FEATURE_TDLS_CHANNEL_SWITCH 0
|
||||
#define WLAN_BSS_COEX_INFORMATION_REQUEST BIT(0)
|
||||
#define WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING BIT(2)
|
||||
#define WLAN_EXT_CAPA4_TDLS_BUFFER_STA BIT(4)
|
||||
#define WLAN_EXT_CAPA4_TDLS_PEER_PSM BIT(5)
|
||||
#define WLAN_EXT_CAPA4_TDLS_CHAN_SWITCH BIT(6)
|
||||
#define WLAN_EXT_CAPA5_TDLS_CH_SW_PROHIBITED BIT(7)
|
||||
#define NL80211_FEATURE_TDLS_CHANNEL_SWITCH 0
|
||||
|
||||
#define STA_TDLS_INITIATOR(sta) 0
|
||||
|
||||
#define REGULATORY_IGNORE_STALE_KICKOFF 0
|
||||
#else
|
||||
#define STA_TDLS_INITIATOR(sta) sta->tdls_initiator
|
||||
#endif
|
||||
|
||||
#ifndef REGULATORY_IGNORE_STALE_KICKOFF
|
||||
#define REGULATORY_IGNORE_STALE_KICKOFF 0
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0))
|
||||
#define cfg80211_rx_mgmt(wdev, freq, rssi, buf, len, flags) \
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)) && \
|
||||
(LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0))
|
||||
#define cfg80211_rx_mgmt(wdev, freq, rssi, buf, len, flags) \
|
||||
cfg80211_rx_mgmt(wdev, freq, rssi, buf, len, flags, GFP_ATOMIC)
|
||||
#elif LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)
|
||||
#define cfg80211_rx_mgmt(wdev, freq, rssi, buf, len, flags) \
|
||||
#define cfg80211_rx_mgmt(wdev, freq, rssi, buf, len, flags) \
|
||||
cfg80211_rx_mgmt(wdev, freq, rssi, buf, len, GFP_ATOMIC)
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0)
|
||||
#if 0
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
|
||||
#define rwnx_cfg80211_tdls_mgmt(wiphy, dev, peer, act, tok, status, peer_capability, initiator, buf, len) \
|
||||
rwnx_cfg80211_tdls_mgmt(wiphy, dev, peer, act, tok, status, peer_capability, buf, len)
|
||||
#define rwnx_cfg80211_tdls_mgmt(wiphy, dev, peer, act, tok, status, \
|
||||
peer_capability, initiator, buf, len) \
|
||||
rwnx_cfg80211_tdls_mgmt(wiphy, dev, peer, act, tok, status, \
|
||||
peer_capability, buf, len)
|
||||
#else
|
||||
#define rwnx_cfg80211_tdls_mgmt(wiphy, dev, peer, act, tok, status, peer_capability, initiator, buf, len) \
|
||||
#define rwnx_cfg80211_tdls_mgmt(wiphy, dev, peer, act, tok, status, \
|
||||
peer_capability, initiator, buf, len) \
|
||||
rwnx_cfg80211_tdls_mgmt(wiphy, dev, peer, act, tok, status, buf, len)
|
||||
#endif
|
||||
#endif
|
||||
@@ -310,16 +321,16 @@ struct ieee80211_wmm_param_ie {
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)
|
||||
enum {
|
||||
IEEE80211_HE_MCS_SUPPORT_0_7 = 0,
|
||||
IEEE80211_HE_MCS_SUPPORT_0_9 = 1,
|
||||
IEEE80211_HE_MCS_SUPPORT_0_11 = 2,
|
||||
IEEE80211_HE_MCS_NOT_SUPPORTED = 3,
|
||||
IEEE80211_HE_MCS_SUPPORT_0_7 = 0,
|
||||
IEEE80211_HE_MCS_SUPPORT_0_9 = 1,
|
||||
IEEE80211_HE_MCS_SUPPORT_0_11 = 2,
|
||||
IEEE80211_HE_MCS_NOT_SUPPORTED = 3,
|
||||
};
|
||||
#endif
|
||||
|
||||
/* MAC80211 */
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 18, 0)
|
||||
#define rwnx_ops_mgd_prepare_tx(hw, vif, duration) \
|
||||
#define rwnx_ops_mgd_prepare_tx(hw, vif, duration) \
|
||||
rwnx_ops_mgd_prepare_tx(hw, vif)
|
||||
#endif
|
||||
|
||||
@@ -339,8 +350,11 @@ enum {
|
||||
|
||||
#else
|
||||
#define RX_ENC_HT(s) (s->encoding = RX_ENC_HT)
|
||||
#define RX_ENC_HT_GF(s) { s->encoding = RX_ENC_HT; \
|
||||
s->enc_flags |= RX_ENC_FLAG_HT_GF; }
|
||||
#define RX_ENC_HT_GF(s) \
|
||||
{ \
|
||||
s->encoding = RX_ENC_HT; \
|
||||
s->enc_flags |= RX_ENC_FLAG_HT_GF; \
|
||||
}
|
||||
#define RX_ENC_VHT(s) (s->encoding = RX_ENC_VHT)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)
|
||||
#define RX_ENC_HE(s) (s->encoding = RX_ENC_VHT)
|
||||
@@ -358,62 +372,66 @@ enum {
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0)
|
||||
#define ieee80211_cqm_rssi_notify(vif, event, level, gfp) \
|
||||
#define ieee80211_cqm_rssi_notify(vif, event, level, gfp) \
|
||||
ieee80211_cqm_rssi_notify(vif, event, gfp)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_VENDOR_RWNX_AMSDUS_TX
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
|
||||
#define rwnx_ops_ampdu_action(hw, vif, params) \
|
||||
rwnx_ops_ampdu_action(hw, vif, enum ieee80211_ampdu_mlme_action action, \
|
||||
struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size)
|
||||
#define rwnx_ops_ampdu_action(hw, vif, params) \
|
||||
rwnx_ops_ampdu_action(hw, vif, \
|
||||
enum ieee80211_ampdu_mlme_action action, \
|
||||
struct ieee80211_sta *sta, u16 tid, u16 *ssn, \
|
||||
u8 buf_size)
|
||||
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
|
||||
#define rwnx_ops_ampdu_action(hw, vif, params) \
|
||||
rwnx_ops_ampdu_action(hw, vif, enum ieee80211_ampdu_mlme_action action, \
|
||||
struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size, \
|
||||
bool amsdu)
|
||||
#define rwnx_ops_ampdu_action(hw, vif, params) \
|
||||
rwnx_ops_ampdu_action(hw, vif, \
|
||||
enum ieee80211_ampdu_mlme_action action, \
|
||||
struct ieee80211_sta *sta, u16 tid, u16 *ssn, \
|
||||
u8 buf_size, bool amsdu)
|
||||
#endif
|
||||
#endif /* CONFIG_VENDOR_RWNX_AMSDUS_TX */
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)
|
||||
#define IEEE80211_HW_SUPPORT_FAST_XMIT 0
|
||||
#define ieee80211_hw_check(hw, feat) (hw->flags & IEEE80211_HW_##feat)
|
||||
#define ieee80211_hw_set(hw, feat) {hw->flags |= IEEE80211_HW_##feat; }
|
||||
#define ieee80211_hw_set(hw, feat) \
|
||||
{ \
|
||||
hw->flags |= IEEE80211_HW_##feat; \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)
|
||||
#define rwnx_ops_sw_scan_start(hw, vif, mac_addr) \
|
||||
rwnx_ops_sw_scan_start(hw)
|
||||
#define rwnx_ops_sw_scan_complete(hw, vif) \
|
||||
rwnx_ops_sw_scan_complete(hw)
|
||||
#define rwnx_ops_sw_scan_start(hw, vif, mac_addr) rwnx_ops_sw_scan_start(hw)
|
||||
#define rwnx_ops_sw_scan_complete(hw, vif) rwnx_ops_sw_scan_complete(hw)
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0)
|
||||
#define rwnx_ops_hw_scan(hw, vif, hw_req) \
|
||||
#define rwnx_ops_hw_scan(hw, vif, hw_req) \
|
||||
rwnx_ops_hw_scan(hw, vif, struct cfg80211_scan_request *req)
|
||||
#endif
|
||||
|
||||
/* NET */
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) \
|
||||
rwnx_select_queue(dev, skb)
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) rwnx_select_queue(dev, skb)
|
||||
#elif LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) \
|
||||
rwnx_select_queue(dev, skb, void *accel_priv, select_queue_fallback_t fallback)
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) \
|
||||
rwnx_select_queue(dev, skb, void *accel_priv, \
|
||||
select_queue_fallback_t fallback)
|
||||
#elif LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) \
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) \
|
||||
rwnx_select_queue(dev, skb, sb_dev, select_queue_fallback_t fallback)
|
||||
#else
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) \
|
||||
rwnx_select_queue(dev, skb, sb_dev)
|
||||
#define rwnx_select_queue(dev, skb, sb_dev) rwnx_select_queue(dev, skb, sb_dev)
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) && !(defined CONFIG_VENDOR_RWNX)
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) && \
|
||||
!(defined CONFIG_VENDOR_RWNX)
|
||||
#define sk_pacing_shift_update(sk, shift)
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0)
|
||||
#define alloc_netdev_mqs(size, name, assign, setup, txqs, rxqs) \
|
||||
#define alloc_netdev_mqs(size, name, assign, setup, txqs, rxqs) \
|
||||
alloc_netdev_mqs(size, name, setup, txqs, rxqs)
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -10,7 +10,6 @@
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RWNX_DEBUGFS_H_
|
||||
#define _RWNX_DEBUGFS_H_
|
||||
#include <linux/version.h>
|
||||
@@ -25,119 +24,120 @@ struct rwnx_sta;
|
||||
/* some macros taken from iwlwifi */
|
||||
/* TODO: replace with generic read and fill read buffer in open to avoid double
|
||||
* reads */
|
||||
#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
|
||||
if (!debugfs_create_file(#name, mode, parent, rwnx_hw, \
|
||||
&rwnx_dbgfs_##name##_ops)) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
#define DEBUGFS_ADD_FILE(name, parent, mode) \
|
||||
do { \
|
||||
if (!debugfs_create_file(#name, mode, parent, rwnx_hw, \
|
||||
&rwnx_dbgfs_##name##_ops)) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
#define DEBUGFS_ADD_BOOL(name, parent, ptr) do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
|
||||
parent, ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
#define DEBUGFS_ADD_BOOL(name, parent, ptr) \
|
||||
do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, parent, \
|
||||
ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
#define DEBUGFS_ADD_X64(name, parent, ptr) do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_x64(#name, S_IWUSR | S_IRUSR, \
|
||||
parent, ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
#define DEBUGFS_ADD_X64(name, parent, ptr) \
|
||||
do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_x64(#name, S_IWUSR | S_IRUSR, parent, \
|
||||
ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
#define DEBUGFS_ADD_U64(name, parent, ptr, mode) do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_u64(#name, mode, \
|
||||
parent, ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
#define DEBUGFS_ADD_U64(name, parent, ptr, mode) \
|
||||
do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_u64(#name, mode, parent, ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
#define DEBUGFS_ADD_X32(name, parent, ptr) do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
|
||||
parent, ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
#define DEBUGFS_ADD_X32(name, parent, ptr) \
|
||||
do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, parent, \
|
||||
ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 7, 0)
|
||||
#define DEBUGFS_ADD_U32(name, parent, ptr, mode) do { \
|
||||
debugfs_create_u32(#name, mode, \
|
||||
parent, ptr); \
|
||||
} while (0)
|
||||
#define DEBUGFS_ADD_U32(name, parent, ptr, mode) \
|
||||
do { \
|
||||
debugfs_create_u32(#name, mode, parent, ptr); \
|
||||
} while (0)
|
||||
#else
|
||||
#define DEBUGFS_ADD_U32(name, parent, ptr, mode) do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_u32(#name, mode, \
|
||||
parent, ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
#define DEBUGFS_ADD_U32(name, parent, ptr, mode) \
|
||||
do { \
|
||||
struct dentry *__tmp; \
|
||||
__tmp = debugfs_create_u32(#name, mode, parent, ptr); \
|
||||
if (IS_ERR(__tmp) || !__tmp) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* file operation */
|
||||
#define DEBUGFS_READ_FUNC(name) \
|
||||
static ssize_t rwnx_dbgfs_##name##_read(struct file *file, \
|
||||
char __user *user_buf, \
|
||||
size_t count, loff_t *ppos);
|
||||
#define DEBUGFS_READ_FUNC(name) \
|
||||
static ssize_t rwnx_dbgfs_##name##_read(struct file *file, \
|
||||
char __user *user_buf, \
|
||||
size_t count, loff_t *ppos);
|
||||
|
||||
#define DEBUGFS_WRITE_FUNC(name) \
|
||||
static ssize_t rwnx_dbgfs_##name##_write(struct file *file, \
|
||||
const char __user *user_buf,\
|
||||
size_t count, loff_t *ppos);
|
||||
#define DEBUGFS_WRITE_FUNC(name) \
|
||||
static ssize_t rwnx_dbgfs_##name##_write(struct file *file, \
|
||||
const char __user *user_buf, \
|
||||
size_t count, loff_t *ppos);
|
||||
|
||||
#define DEBUGFS_OPEN_FUNC(name) \
|
||||
static int rwnx_dbgfs_##name##_open(struct inode *inode, \
|
||||
struct file *file);
|
||||
#define DEBUGFS_OPEN_FUNC(name) \
|
||||
static int rwnx_dbgfs_##name##_open(struct inode *inode, \
|
||||
struct file *file);
|
||||
|
||||
#define DEBUGFS_RELEASE_FUNC(name) \
|
||||
static int rwnx_dbgfs_##name##_release(struct inode *inode, \
|
||||
struct file *file);
|
||||
#define DEBUGFS_RELEASE_FUNC(name) \
|
||||
static int rwnx_dbgfs_##name##_release(struct inode *inode, \
|
||||
struct file *file);
|
||||
|
||||
#define DEBUGFS_READ_FILE_OPS(name) \
|
||||
DEBUGFS_READ_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.read = rwnx_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
#define DEBUGFS_READ_FILE_OPS(name) \
|
||||
DEBUGFS_READ_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.read = rwnx_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#define DEBUGFS_WRITE_FILE_OPS(name) \
|
||||
DEBUGFS_WRITE_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.write = rwnx_dbgfs_##name##_write, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
#define DEBUGFS_WRITE_FILE_OPS(name) \
|
||||
DEBUGFS_WRITE_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.write = rwnx_dbgfs_##name##_write, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
|
||||
DEBUGFS_READ_FUNC(name); \
|
||||
DEBUGFS_WRITE_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.write = rwnx_dbgfs_##name##_write, \
|
||||
.read = rwnx_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#define DEBUGFS_READ_WRITE_OPEN_RELEASE_FILE_OPS(name) \
|
||||
DEBUGFS_READ_FUNC(name); \
|
||||
DEBUGFS_WRITE_FUNC(name); \
|
||||
DEBUGFS_OPEN_FUNC(name); \
|
||||
DEBUGFS_RELEASE_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.write = rwnx_dbgfs_##name##_write, \
|
||||
.read = rwnx_dbgfs_##name##_read, \
|
||||
.open = rwnx_dbgfs_##name##_open, \
|
||||
.release = rwnx_dbgfs_##name##_release, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
|
||||
DEBUGFS_READ_FUNC(name); \
|
||||
DEBUGFS_WRITE_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.write = rwnx_dbgfs_##name##_write, \
|
||||
.read = rwnx_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#define DEBUGFS_READ_WRITE_OPEN_RELEASE_FILE_OPS(name) \
|
||||
DEBUGFS_READ_FUNC(name); \
|
||||
DEBUGFS_WRITE_FUNC(name); \
|
||||
DEBUGFS_OPEN_FUNC(name); \
|
||||
DEBUGFS_RELEASE_FUNC(name); \
|
||||
static const struct file_operations rwnx_dbgfs_##name##_ops = { \
|
||||
.write = rwnx_dbgfs_##name##_write, \
|
||||
.read = rwnx_dbgfs_##name##_read, \
|
||||
.open = rwnx_dbgfs_##name##_open, \
|
||||
.release = rwnx_dbgfs_##name##_release, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#ifdef CONFIG_RWNX_DEBUGFS
|
||||
|
||||
@@ -185,18 +185,28 @@ int rwnx_dbgfs_register(struct rwnx_hw *rwnx_hw, const char *name);
|
||||
void rwnx_dbgfs_unregister(struct rwnx_hw *rwnx_hw);
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
void rwnx_dbgfs_register_rc_stat(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta);
|
||||
void rwnx_dbgfs_unregister_rc_stat(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta);
|
||||
void rwnx_dbgfs_unregister_rc_stat(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_sta *sta);
|
||||
#endif
|
||||
#else
|
||||
struct rwnx_debugfs {
|
||||
};
|
||||
static inline int rwnx_dbgfs_register(struct rwnx_hw *rwnx_hw, const char *name) { return 0; }
|
||||
static inline void rwnx_dbgfs_unregister(struct rwnx_hw *rwnx_hw) {}
|
||||
struct rwnx_debugfs {};
|
||||
static inline int rwnx_dbgfs_register(struct rwnx_hw *rwnx_hw, const char *name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void rwnx_dbgfs_unregister(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
}
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
static inline void rwnx_dbgfs_register_rc_stat(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta) {}
|
||||
static inline void rwnx_dbgfs_unregister_rc_stat(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta) {}
|
||||
static inline void rwnx_dbgfs_register_rc_stat(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_sta *sta)
|
||||
{
|
||||
}
|
||||
static inline void rwnx_dbgfs_unregister_rc_stat(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_sta *sta)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_RWNX_DEBUGFS */
|
||||
|
||||
|
||||
#endif /* _RWNX_DEBUGFS_H_ */
|
||||
|
||||
@@ -50,117 +50,120 @@
|
||||
#include "aic_br_ext.h"
|
||||
#endif /* CONFIG_BR_SUPPORT */
|
||||
|
||||
#define WPI_HDR_LEN 18
|
||||
#define WPI_PN_LEN 16
|
||||
#define WPI_PN_OFST 2
|
||||
#define WPI_MIC_LEN 16
|
||||
#define WPI_KEY_LEN 32
|
||||
#define WPI_HDR_LEN 18
|
||||
#define WPI_PN_LEN 16
|
||||
#define WPI_PN_OFST 2
|
||||
#define WPI_MIC_LEN 16
|
||||
#define WPI_KEY_LEN 32
|
||||
#define WPI_SUBKEY_LEN 16 // WPI key is actually two 16bytes key
|
||||
|
||||
#define LEGACY_PS_ID 0
|
||||
#define UAPSD_ID 1
|
||||
#define LEGACY_PS_ID 0
|
||||
#define UAPSD_ID 1
|
||||
|
||||
#define PS_SP_INTERRUPTED 255
|
||||
#define PS_SP_INTERRUPTED 255
|
||||
#define MAC_ADDR_LEN 6
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || \
|
||||
defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
enum nl80211_ac {
|
||||
NL80211_AC_VO,
|
||||
NL80211_AC_VI,
|
||||
NL80211_AC_BE,
|
||||
NL80211_AC_BK,
|
||||
NL80211_NUM_ACS
|
||||
NL80211_AC_VO,
|
||||
NL80211_AC_VI,
|
||||
NL80211_AC_BE,
|
||||
NL80211_AC_BK,
|
||||
NL80211_NUM_ACS
|
||||
};
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0) || defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0) || \
|
||||
defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
struct ieee80211_vht_operation {
|
||||
u8 vht_op_info_chwidth;
|
||||
u8 vht_op_info_chan_center_freq_seg1_idx;
|
||||
u8 vht_op_info_chan_center_freq_seg2_idx;
|
||||
__le16 vht_basic_mcs_set;
|
||||
u8 vht_op_info_chwidth;
|
||||
u8 vht_op_info_chan_center_freq_seg1_idx;
|
||||
u8 vht_op_info_chan_center_freq_seg2_idx;
|
||||
__le16 vht_basic_mcs_set;
|
||||
} __packed;
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0) || defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
#define IEEE80211_RADIOTAP_VHT 21
|
||||
#define IEEE80211_RADIOTAP_VHT_KNOWN_GI 0x0004
|
||||
#define IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH 0x0040
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0) || \
|
||||
defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
#define IEEE80211_RADIOTAP_VHT 21
|
||||
#define IEEE80211_RADIOTAP_VHT_KNOWN_GI 0x0004
|
||||
#define IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH 0x0040
|
||||
|
||||
#define IEEE80211_RADIOTAP_VHT_FLAG_STBC 0x01
|
||||
#define IEEE80211_RADIOTAP_VHT_FLAG_SGI 0x04
|
||||
#define IEEE80211_RADIOTAP_VHT_FLAG_STBC 0x01
|
||||
#define IEEE80211_RADIOTAP_VHT_FLAG_SGI 0x04
|
||||
|
||||
#define NL80211_FEATURE_CELL_BASE_REG_HINTS 1 << 3
|
||||
#define NL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL 1 << 4
|
||||
#define NL80211_FEATURE_SAE 1 << 5
|
||||
#define NL80211_FEATURE_LOW_PRIORITY_SCAN 1 << 6
|
||||
#define NL80211_FEATURE_SCAN_FLUSH 1 << 7
|
||||
#define NL80211_FEATURE_AP_SCAN 1 << 8
|
||||
#define NL80211_FEATURE_VIF_TXPOWER 1 << 9
|
||||
#define NL80211_FEATURE_NEED_OBSS_SCAN 1 << 10
|
||||
#define NL80211_FEATURE_P2P_GO_CTWIN 1 << 11
|
||||
#define NL80211_FEATURE_P2P_GO_OPPPS 1 << 12
|
||||
#define NL80211_FEATURE_CELL_BASE_REG_HINTS 1 << 3
|
||||
#define NL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL 1 << 4
|
||||
#define NL80211_FEATURE_SAE 1 << 5
|
||||
#define NL80211_FEATURE_LOW_PRIORITY_SCAN 1 << 6
|
||||
#define NL80211_FEATURE_SCAN_FLUSH 1 << 7
|
||||
#define NL80211_FEATURE_AP_SCAN 1 << 8
|
||||
#define NL80211_FEATURE_VIF_TXPOWER 1 << 9
|
||||
#define NL80211_FEATURE_NEED_OBSS_SCAN 1 << 10
|
||||
#define NL80211_FEATURE_P2P_GO_CTWIN 1 << 11
|
||||
#define NL80211_FEATURE_P2P_GO_OPPPS 1 << 12
|
||||
|
||||
/* 802.11ac VHT Capabilities */
|
||||
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895 0x00000000
|
||||
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 0x00000001
|
||||
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 0x00000002
|
||||
#define IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ 0x00000004
|
||||
#define IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ 0x00000008
|
||||
#define IEEE80211_VHT_CAP_RXLDPC 0x00000010
|
||||
#define IEEE80211_VHT_CAP_SHORT_GI_80 0x00000020
|
||||
#define IEEE80211_VHT_CAP_SHORT_GI_160 0x00000040
|
||||
#define IEEE80211_VHT_CAP_TXSTBC 0x00000080
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_1 0x00000100
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_2 0x00000200
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_3 0x00000300
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_4 0x00000400
|
||||
#define IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE 0x00000800
|
||||
#define IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE 0x00001000
|
||||
#define IEEE80211_VHT_CAP_BEAMFORMER_ANTENNAS_MAX 0x00006000
|
||||
#define IEEE80211_VHT_CAP_SOUNDING_DIMENTION_MAX 0x00030000
|
||||
#define IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE 0x00080000
|
||||
#define IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE 0x00100000
|
||||
#define IEEE80211_VHT_CAP_VHT_TXOP_PS 0x00200000
|
||||
#define IEEE80211_VHT_CAP_HTC_VHT 0x00400000
|
||||
#define IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT 23
|
||||
#define IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK \
|
||||
(7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT)
|
||||
#define IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_UNSOL_MFB 0x08000000
|
||||
#define IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB 0x0c000000
|
||||
#define IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN 0x10000000
|
||||
#define IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN 0x20000000
|
||||
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895 0x00000000
|
||||
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 0x00000001
|
||||
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 0x00000002
|
||||
#define IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ 0x00000004
|
||||
#define IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ 0x00000008
|
||||
#define IEEE80211_VHT_CAP_RXLDPC 0x00000010
|
||||
#define IEEE80211_VHT_CAP_SHORT_GI_80 0x00000020
|
||||
#define IEEE80211_VHT_CAP_SHORT_GI_160 0x00000040
|
||||
#define IEEE80211_VHT_CAP_TXSTBC 0x00000080
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_1 0x00000100
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_2 0x00000200
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_3 0x00000300
|
||||
#define IEEE80211_VHT_CAP_RXSTBC_4 0x00000400
|
||||
#define IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE 0x00000800
|
||||
#define IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE 0x00001000
|
||||
#define IEEE80211_VHT_CAP_BEAMFORMER_ANTENNAS_MAX 0x00006000
|
||||
#define IEEE80211_VHT_CAP_SOUNDING_DIMENTION_MAX 0x00030000
|
||||
#define IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE 0x00080000
|
||||
#define IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE 0x00100000
|
||||
#define IEEE80211_VHT_CAP_VHT_TXOP_PS 0x00200000
|
||||
#define IEEE80211_VHT_CAP_HTC_VHT 0x00400000
|
||||
#define IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT 23
|
||||
#define IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK \
|
||||
(7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT)
|
||||
#define IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_UNSOL_MFB 0x08000000
|
||||
#define IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB 0x0c000000
|
||||
#define IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN 0x10000000
|
||||
#define IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN 0x20000000
|
||||
|
||||
enum ieee80211_vht_mcs_support {
|
||||
IEEE80211_VHT_MCS_SUPPORT_0_7 = 0,
|
||||
IEEE80211_VHT_MCS_SUPPORT_0_8 = 1,
|
||||
IEEE80211_VHT_MCS_SUPPORT_0_9 = 2,
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED = 3,
|
||||
IEEE80211_VHT_MCS_SUPPORT_0_7 = 0,
|
||||
IEEE80211_VHT_MCS_SUPPORT_0_8 = 1,
|
||||
IEEE80211_VHT_MCS_SUPPORT_0_9 = 2,
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED = 3,
|
||||
};
|
||||
|
||||
enum nl80211_chan_width {
|
||||
NL80211_CHAN_WIDTH_20_NOHT,
|
||||
NL80211_CHAN_WIDTH_20,
|
||||
NL80211_CHAN_WIDTH_40,
|
||||
NL80211_CHAN_WIDTH_80,
|
||||
NL80211_CHAN_WIDTH_80P80,
|
||||
NL80211_CHAN_WIDTH_160,
|
||||
NL80211_CHAN_WIDTH_20_NOHT,
|
||||
NL80211_CHAN_WIDTH_20,
|
||||
NL80211_CHAN_WIDTH_40,
|
||||
NL80211_CHAN_WIDTH_80,
|
||||
NL80211_CHAN_WIDTH_80P80,
|
||||
NL80211_CHAN_WIDTH_160,
|
||||
};
|
||||
|
||||
struct cfg80211_chan_def {
|
||||
struct ieee80211_channel *chan;
|
||||
enum nl80211_chan_width width;
|
||||
u32 center_freq1;
|
||||
u32 center_freq2;
|
||||
struct ieee80211_channel *chan;
|
||||
enum nl80211_chan_width width;
|
||||
u32 center_freq1;
|
||||
u32 center_freq2;
|
||||
};
|
||||
|
||||
enum nl80211_mesh_power_mode {
|
||||
NL80211_MESH_POWER_UNKNOWN,
|
||||
NL80211_MESH_POWER_ACTIVE,
|
||||
NL80211_MESH_POWER_LIGHT_SLEEP,
|
||||
NL80211_MESH_POWER_DEEP_SLEEP,
|
||||
__NL80211_MESH_POWER_AFTER_LAST,
|
||||
NL80211_MESH_POWER_MAX = __NL80211_MESH_POWER_AFTER_LAST - 1
|
||||
NL80211_MESH_POWER_UNKNOWN,
|
||||
NL80211_MESH_POWER_ACTIVE,
|
||||
NL80211_MESH_POWER_LIGHT_SLEEP,
|
||||
NL80211_MESH_POWER_DEEP_SLEEP,
|
||||
__NL80211_MESH_POWER_AFTER_LAST,
|
||||
NL80211_MESH_POWER_MAX = __NL80211_MESH_POWER_AFTER_LAST - 1
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -202,17 +205,17 @@ struct rwnx_key {
|
||||
* Structure containing information about a Mesh Path
|
||||
*/
|
||||
struct rwnx_mesh_path {
|
||||
struct list_head list; /* For rwnx_vif.mesh_paths */
|
||||
u8 path_idx; /* Path Index */
|
||||
struct mac_addr tgt_mac_addr; /* Target MAC Address */
|
||||
struct rwnx_sta *p_nhop_sta; /* Pointer to the Next Hop STA */
|
||||
struct list_head list; /* For rwnx_vif.mesh_paths */
|
||||
u8 path_idx; /* Path Index */
|
||||
struct mac_addr tgt_mac_addr; /* Target MAC Address */
|
||||
struct rwnx_sta *p_nhop_sta; /* Pointer to the Next Hop STA */
|
||||
};
|
||||
|
||||
struct rwnx_mesh_proxy {
|
||||
struct list_head list; /* For rwnx_vif.mesh_proxy */
|
||||
struct mac_addr ext_sta_addr; /* Address of the External STA */
|
||||
struct mac_addr proxy_addr; /* Proxy MAC Address */
|
||||
bool local; /* Indicate if interface is a proxy for the device */
|
||||
struct list_head list; /* For rwnx_vif.mesh_proxy */
|
||||
struct mac_addr ext_sta_addr; /* Address of the External STA */
|
||||
struct mac_addr proxy_addr; /* Proxy MAC Address */
|
||||
bool local; /* Indicate if interface is a proxy for the device */
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -247,16 +250,16 @@ struct apm_probe_sta {
|
||||
};
|
||||
/// Possible States of the TDLS link.
|
||||
enum tdls_status_tag {
|
||||
/// TDLS link is not active (no TDLS peer connected)
|
||||
TDLS_LINK_IDLE,
|
||||
/// TDLS Setup Request transmitted
|
||||
TDLS_SETUP_REQ_TX,
|
||||
/// TDLS Setup Response transmitted
|
||||
TDLS_SETUP_RSP_TX,
|
||||
/// TDLS link is active (TDLS peer connected)
|
||||
TDLS_LINK_ACTIVE,
|
||||
/// TDLS Max Number of states.
|
||||
TDLS_STATE_MAX
|
||||
/// TDLS link is not active (no TDLS peer connected)
|
||||
TDLS_LINK_IDLE,
|
||||
/// TDLS Setup Request transmitted
|
||||
TDLS_SETUP_REQ_TX,
|
||||
/// TDLS Setup Response transmitted
|
||||
TDLS_SETUP_RSP_TX,
|
||||
/// TDLS link is active (TDLS peer connected)
|
||||
TDLS_LINK_ACTIVE,
|
||||
/// TDLS Max Number of states.
|
||||
TDLS_STATE_MAX
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -265,19 +268,18 @@ enum tdls_status_tag {
|
||||
*
|
||||
*/
|
||||
struct rwnx_tdls {
|
||||
bool active; /* Indicate if TDLS link is active */
|
||||
bool initiator; /* Indicate if TDLS peer is the TDLS initiator */
|
||||
bool chsw_en; /* Indicate if channel switch is enabled */
|
||||
u8 last_tid; /* TID of the latest MPDU transmitted over the
|
||||
bool active; /* Indicate if TDLS link is active */
|
||||
bool initiator; /* Indicate if TDLS peer is the TDLS initiator */
|
||||
bool chsw_en; /* Indicate if channel switch is enabled */
|
||||
u8 last_tid; /* TID of the latest MPDU transmitted over the
|
||||
TDLS direct link to the TDLS STA */
|
||||
u16 last_sn; /* Sequence number of the latest MPDU transmitted
|
||||
u16 last_sn; /* Sequence number of the latest MPDU transmitted
|
||||
over the TDLS direct link to the TDLS STA */
|
||||
bool ps_on; /* Indicate if the power save is enabled on the
|
||||
bool ps_on; /* Indicate if the power save is enabled on the
|
||||
TDLS STA */
|
||||
bool chsw_allowed; /* Indicate if TDLS channel switch is allowed */
|
||||
bool chsw_allowed; /* Indicate if TDLS channel switch is allowed */
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* enum rwnx_ap_flags - AP flags
|
||||
*
|
||||
@@ -300,34 +302,37 @@ struct rwnx_vif {
|
||||
struct net_device *ndev;
|
||||
struct net_device_stats net_stats;
|
||||
struct rwnx_key key[6];
|
||||
unsigned long drv_flags;
|
||||
unsigned long drv_flags;
|
||||
atomic_t drv_conn_state;
|
||||
u8 drv_vif_index; /* Identifier of the VIF in driver */
|
||||
u8 vif_index; /* Identifier of the station in FW */
|
||||
u8 ch_index; /* Channel context identifier */
|
||||
bool up; /* Indicate if associated netdev is up
|
||||
u8 drv_vif_index; /* Identifier of the VIF in driver */
|
||||
u8 vif_index; /* Identifier of the station in FW */
|
||||
u8 ch_index; /* Channel context identifier */
|
||||
bool up; /* Indicate if associated netdev is up
|
||||
(i.e. Interface is created at fw level) */
|
||||
bool use_4addr; /* Should we use 4addresses mode */
|
||||
bool is_resending; /* Indicate if a frame is being resent on this interface */
|
||||
bool user_mpm; /* In case of Mesh Point VIF, indicate if MPM is handled by userspace */
|
||||
bool roc_tdls; /* Indicate if the ROC has been called by a
|
||||
bool use_4addr; /* Should we use 4addresses mode */
|
||||
bool is_resending; /* Indicate if a frame is being resent on this interface */
|
||||
bool user_mpm; /* In case of Mesh Point VIF, indicate if MPM is handled by userspace */
|
||||
bool roc_tdls; /* Indicate if the ROC has been called by a
|
||||
TDLS station */
|
||||
u8 tdls_status; /* Status of the TDLS link */
|
||||
bool tdls_chsw_prohibited; /* Indicate if TDLS Channel Switch is prohibited */
|
||||
bool wep_enabled; /* 1 if WEP is enabled */
|
||||
bool wep_auth_err; /* 1 if auth status code is not supported auth alg when WEP enabled */
|
||||
enum nl80211_auth_type last_auth_type; /* Authentication type (algorithm) sent in the last connection
|
||||
u8 tdls_status; /* Status of the TDLS link */
|
||||
bool tdls_chsw_prohibited; /* Indicate if TDLS Channel Switch is prohibited */
|
||||
bool wep_enabled; /* 1 if WEP is enabled */
|
||||
bool wep_auth_err; /* 1 if auth status code is not supported auth alg when WEP enabled */
|
||||
enum nl80211_auth_type
|
||||
last_auth_type; /* Authentication type (algorithm) sent in the last connection
|
||||
when WEP enabled */
|
||||
union {
|
||||
struct {
|
||||
struct rwnx_sta *ap; /* Pointer to the peer STA entry allocated for
|
||||
struct rwnx_sta *
|
||||
ap; /* Pointer to the peer STA entry allocated for
|
||||
the AP */
|
||||
struct rwnx_sta *tdls_sta; /* Pointer to the TDLS station */
|
||||
bool external_auth; /* Indicate if external authentication is in progress */
|
||||
struct rwnx_sta
|
||||
*tdls_sta; /* Pointer to the TDLS station */
|
||||
bool external_auth; /* Indicate if external authentication is in progress */
|
||||
u32 group_cipher_type;
|
||||
u32 paired_cipher_type;
|
||||
//connected network info start
|
||||
char ssid[33];//ssid max is 32, but this has one spare for '\0'
|
||||
char ssid[33]; //ssid max is 32, but this has one spare for '\0'
|
||||
int ssid_len;
|
||||
u8 bssid[ETH_ALEN];
|
||||
u32 conn_owner_nlportid;
|
||||
@@ -335,25 +340,30 @@ struct rwnx_vif {
|
||||
//connected network info end
|
||||
} sta;
|
||||
struct {
|
||||
u16 flags; /* see rwnx_ap_flags */
|
||||
struct list_head sta_list; /* List of STA connected to the AP */
|
||||
struct rwnx_bcn bcn; /* beacon */
|
||||
u8 bcmc_index; /* Index of the BCMC sta to use */
|
||||
u16 flags; /* see rwnx_ap_flags */
|
||||
struct list_head
|
||||
sta_list; /* List of STA connected to the AP */
|
||||
struct rwnx_bcn bcn; /* beacon */
|
||||
u8 bcmc_index; /* Index of the BCMC sta to use */
|
||||
#if (defined CONFIG_HE_FOR_OLD_KERNEL) || (defined CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
u8 aic_index;
|
||||
#endif
|
||||
struct rwnx_csa *csa;
|
||||
|
||||
struct list_head mpath_list; /* List of Mesh Paths used on this interface */
|
||||
struct list_head proxy_list; /* List of Proxies Information used on this interface */
|
||||
bool create_path; /* Indicate if we are waiting for a MESH_CREATE_PATH_CFM
|
||||
struct list_head
|
||||
mpath_list; /* List of Mesh Paths used on this interface */
|
||||
struct list_head
|
||||
proxy_list; /* List of Proxies Information used on this interface */
|
||||
bool create_path; /* Indicate if we are waiting for a MESH_CREATE_PATH_CFM
|
||||
message */
|
||||
int generation; /* Increased each time the list of Mesh Paths is updated */
|
||||
enum nl80211_mesh_power_mode mesh_pm; /* mesh power save mode currently set in firmware */
|
||||
enum nl80211_mesh_power_mode next_mesh_pm; /* mesh power save mode for next peer */
|
||||
int generation; /* Increased each time the list of Mesh Paths is updated */
|
||||
enum nl80211_mesh_power_mode
|
||||
mesh_pm; /* mesh power save mode currently set in firmware */
|
||||
enum nl80211_mesh_power_mode
|
||||
next_mesh_pm; /* mesh power save mode for next peer */
|
||||
} ap;
|
||||
struct {
|
||||
struct rwnx_vif *master; /* pointer on master interface */
|
||||
struct rwnx_vif *master; /* pointer on master interface */
|
||||
struct rwnx_sta *sta_4a;
|
||||
} ap_vlan;
|
||||
};
|
||||
@@ -362,20 +372,20 @@ struct rwnx_vif {
|
||||
u8_l is_p2p_vif;
|
||||
struct apm_probe_sta sta_probe;
|
||||
|
||||
#ifdef CONFIG_BR_SUPPORT
|
||||
spinlock_t br_ext_lock;
|
||||
#ifdef CONFIG_BR_SUPPORT
|
||||
spinlock_t br_ext_lock;
|
||||
/* unsigned int macclone_completed; */
|
||||
struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
|
||||
int pppoe_connection_in_progress;
|
||||
unsigned char pppoe_addr[MACADDRLEN];
|
||||
unsigned char scdb_mac[MACADDRLEN];
|
||||
unsigned char scdb_ip[4];
|
||||
struct nat25_network_db_entry *scdb_entry;
|
||||
unsigned char br_mac[MACADDRLEN];
|
||||
unsigned char br_ip[4];
|
||||
struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
|
||||
int pppoe_connection_in_progress;
|
||||
unsigned char pppoe_addr[MACADDRLEN];
|
||||
unsigned char scdb_mac[MACADDRLEN];
|
||||
unsigned char scdb_ip[4];
|
||||
struct nat25_network_db_entry *scdb_entry;
|
||||
unsigned char br_mac[MACADDRLEN];
|
||||
unsigned char br_ip[4];
|
||||
|
||||
struct br_ext_info ethBrExtInfo;
|
||||
#endif /* CONFIG_BR_SUPPORT */
|
||||
struct br_ext_info ethBrExtInfo;
|
||||
#endif /* CONFIG_BR_SUPPORT */
|
||||
};
|
||||
|
||||
#define RWNX_VIF_TYPE(rwnx_vif) (rwnx_vif->wdev.iftype)
|
||||
@@ -425,9 +435,18 @@ struct rwnx_sta_stats {
|
||||
|
||||
#if (defined CONFIG_HE_FOR_OLD_KERNEL) || (defined CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
struct aic_sta {
|
||||
u8 sta_idx; /* Identifier of the station */
|
||||
bool he; /* Flag indicating if the station supports HE */
|
||||
bool vht; /* Flag indicating if the station supports VHT */
|
||||
u8 sta_idx; /* Identifier of the station */
|
||||
bool he; /* Flag indicating if the station supports HE */
|
||||
bool vht; /* Flag indicating if the station supports VHT */
|
||||
|
||||
struct ieee80211_he_cap_elem he_cap_elem;
|
||||
struct ieee80211_he_mcs_nss_supp he_mcs_nss_supp;
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0) || \
|
||||
defined(CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
__le32 vht_cap_info;
|
||||
struct ieee80211_vht_mcs_info supp_mcs;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -436,45 +455,47 @@ struct aic_sta {
|
||||
*/
|
||||
struct rwnx_sta {
|
||||
struct list_head list;
|
||||
u16 aid; /* association ID */
|
||||
u8 sta_idx; /* Identifier of the station */
|
||||
u8 vif_idx; /* Identifier of the VIF (fw id) the station
|
||||
u16 aid; /* association ID */
|
||||
u8 sta_idx; /* Identifier of the station */
|
||||
u8 vif_idx; /* Identifier of the VIF (fw id) the station
|
||||
belongs to */
|
||||
u8 vlan_idx; /* Identifier of the VLAN VIF (fw id) the station
|
||||
u8 vlan_idx; /* Identifier of the VLAN VIF (fw id) the station
|
||||
belongs to (= vif_idx if no vlan in used) */
|
||||
enum nl80211_band band; /* Band */
|
||||
enum nl80211_chan_width width; /* Channel width */
|
||||
u16 center_freq; /* Center frequency */
|
||||
u32 center_freq1; /* Center frequency 1 */
|
||||
u32 center_freq2; /* Center frequency 2 */
|
||||
u8 ch_idx; /* Identifier of the channel
|
||||
u16 center_freq; /* Center frequency */
|
||||
u32 center_freq1; /* Center frequency 1 */
|
||||
u32 center_freq2; /* Center frequency 2 */
|
||||
u8 ch_idx; /* Identifier of the channel
|
||||
context the station belongs to */
|
||||
bool qos; /* Flag indicating if the station
|
||||
bool qos; /* Flag indicating if the station
|
||||
supports QoS */
|
||||
u8 acm; /* Bitfield indicating which queues
|
||||
u8 acm; /* Bitfield indicating which queues
|
||||
have AC mandatory */
|
||||
u16 uapsd_tids; /* Bitfield indicating which tids are subject to
|
||||
u16 uapsd_tids; /* Bitfield indicating which tids are subject to
|
||||
UAPSD */
|
||||
u8 mac_addr[ETH_ALEN]; /* MAC address of the station */
|
||||
u8 mac_addr[ETH_ALEN]; /* MAC address of the station */
|
||||
struct rwnx_key key;
|
||||
bool valid; /* Flag indicating if the entry is valid */
|
||||
struct rwnx_sta_ps ps; /* Information when STA is in PS (AP only) */
|
||||
bool valid; /* Flag indicating if the entry is valid */
|
||||
struct rwnx_sta_ps ps; /* Information when STA is in PS (AP only) */
|
||||
#ifdef CONFIG_RWNX_BFMER
|
||||
struct rwnx_bfmer_report *bfm_report; /* Beamforming report to be used for
|
||||
struct rwnx_bfmer_report *bfm_report; /* Beamforming report to be used for
|
||||
VHT TX Beamforming */
|
||||
#ifdef CONFIG_RWNX_MUMIMO_TX
|
||||
struct rwnx_sta_group_info group_info; /* MU grouping information for the STA */
|
||||
struct rwnx_sta_group_info
|
||||
group_info; /* MU grouping information for the STA */
|
||||
#endif /* CONFIG_RWNX_MUMIMO_TX */
|
||||
#endif /* CONFIG_RWNX_BFMER */
|
||||
|
||||
bool ht; /* Flag indicating if the station
|
||||
bool ht; /* Flag indicating if the station
|
||||
supports HT */
|
||||
bool vht; /* Flag indicating if the station
|
||||
bool vht; /* Flag indicating if the station
|
||||
supports VHT */
|
||||
u32 ac_param[AC_MAX]; /* EDCA parameters */
|
||||
u32 ac_param[AC_MAX]; /* EDCA parameters */
|
||||
struct rwnx_tdls tdls; /* TDLS station information */
|
||||
struct rwnx_sta_stats stats;
|
||||
enum nl80211_mesh_power_mode mesh_pm; /* link-specific mesh power save mode */
|
||||
enum nl80211_mesh_power_mode
|
||||
mesh_pm; /* link-specific mesh power save mode */
|
||||
};
|
||||
|
||||
static inline const u8 *rwnx_sta_addr(struct rwnx_sta *rwnx_sta)
|
||||
@@ -540,7 +561,7 @@ struct rwnx_survey_info {
|
||||
/* Structure containing channel context information */
|
||||
struct rwnx_chanctx {
|
||||
struct cfg80211_chan_def chan_def; /* channel description */
|
||||
u8 count; /* number of vif using this ctxt */
|
||||
u8 count; /* number of vif using this ctxt */
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -559,35 +580,40 @@ struct rwnx_phy_info {
|
||||
bool limit_bw;
|
||||
};
|
||||
|
||||
|
||||
struct defrag_ctrl_info {
|
||||
struct list_head list;
|
||||
u8 sta_idx;
|
||||
u8 tid;
|
||||
u16 sn;
|
||||
u8 next_fn;
|
||||
u16 frm_len;
|
||||
struct sk_buff *skb;
|
||||
struct timer_list defrag_timer;
|
||||
struct rwnx_hw *rwnx_hw;
|
||||
struct list_head list;
|
||||
u8 sta_idx;
|
||||
u8 tid;
|
||||
u16 sn;
|
||||
u8 next_fn;
|
||||
u16 frm_len;
|
||||
struct sk_buff *skb;
|
||||
struct timer_list defrag_timer;
|
||||
struct rwnx_hw *rwnx_hw;
|
||||
};
|
||||
|
||||
struct amsdu_subframe_hdr {
|
||||
u8 da[6];
|
||||
u8 sa[6];
|
||||
u16 sublen;
|
||||
u8 da[6];
|
||||
u8 sa[6];
|
||||
u16 sublen;
|
||||
};
|
||||
|
||||
|
||||
/* rwnx driver status */
|
||||
void rwnx_set_conn_state(atomic_t *drv_conn_state, int state);
|
||||
|
||||
enum rwnx_drv_connect_status {
|
||||
enum rwnx_drv_connect_status {
|
||||
RWNX_DRV_STATUS_DISCONNECTED = 0,
|
||||
RWNX_DRV_STATUS_DISCONNECTING,
|
||||
RWNX_DRV_STATUS_CONNECTING,
|
||||
RWNX_DRV_STATUS_CONNECTED,
|
||||
RWNX_DRV_STATUS_DISCONNECTING,
|
||||
RWNX_DRV_STATUS_CONNECTING,
|
||||
RWNX_DRV_STATUS_CONNECTED,
|
||||
RWNX_DRV_STATUS_ROAMING,
|
||||
};
|
||||
|
||||
static const char *const s_conn_state[] = {
|
||||
"RWNX_DRV_STATUS_DISCONNECTED", "RWNX_DRV_STATUS_DISCONNECTING",
|
||||
"RWNX_DRV_STATUS_CONNECTING", "RWNX_DRV_STATUS_CONNECTED",
|
||||
"RWNX_DRV_STATUS_ROAMING",
|
||||
};
|
||||
|
||||
struct rwnx_hw {
|
||||
struct rwnx_mod_params *mod_params;
|
||||
@@ -600,7 +626,8 @@ struct rwnx_hw {
|
||||
#endif
|
||||
struct wiphy *wiphy;
|
||||
struct list_head vifs;
|
||||
struct rwnx_vif *vif_table[NX_VIRT_DEV_MAX + NX_REMOTE_STA_MAX]; /* indexed with fw id */
|
||||
struct rwnx_vif *vif_table[NX_VIRT_DEV_MAX +
|
||||
NX_REMOTE_STA_MAX]; /* indexed with fw id */
|
||||
struct rwnx_sta sta_table[NX_REMOTE_STA_MAX + NX_VIRT_DEV_MAX];
|
||||
#if (defined CONFIG_HE_FOR_OLD_KERNEL) || (defined CONFIG_VHT_FOR_OLD_KERNEL)
|
||||
struct aic_sta aic_table[NX_REMOTE_STA_MAX + NX_VIRT_DEV_MAX];
|
||||
@@ -608,7 +635,7 @@ struct rwnx_hw {
|
||||
struct rwnx_survey_info survey[SCAN_CHANNEL_MAX];
|
||||
struct cfg80211_scan_request *scan_request;
|
||||
#ifdef CONFIG_SCHED_SCAN
|
||||
struct cfg80211_sched_scan_request *sched_scan_req;
|
||||
struct cfg80211_sched_scan_request *sched_scan_req;
|
||||
#endif
|
||||
struct rwnx_chanctx chanctx_table[NX_CHAN_CTXT_CNT];
|
||||
u8 cur_chanctx;
|
||||
@@ -621,8 +648,9 @@ struct rwnx_hw {
|
||||
#endif
|
||||
|
||||
/* RoC Management */
|
||||
struct rwnx_roc_elem *roc_elem; /* Information provided by cfg80211 in its remain on channel request */
|
||||
u32 roc_cookie_cnt; /* Counter used to identify RoC request sent by cfg80211 */
|
||||
struct rwnx_roc_elem *
|
||||
roc_elem; /* Information provided by cfg80211 in its remain on channel request */
|
||||
u32 roc_cookie_cnt; /* Counter used to identify RoC request sent by cfg80211 */
|
||||
|
||||
struct rwnx_cmd_mgr *cmd_mgr;
|
||||
|
||||
@@ -630,10 +658,11 @@ struct rwnx_hw {
|
||||
|
||||
spinlock_t tx_lock;
|
||||
spinlock_t cb_lock;
|
||||
struct mutex mutex; /* per-device perimeter lock */
|
||||
struct mutex mutex; /* per-device perimeter lock */
|
||||
|
||||
struct tasklet_struct task;
|
||||
struct mm_version_cfm version_cfm; /* Lower layers versions - obtained via MM_VERSION_REQ */
|
||||
struct mm_version_cfm
|
||||
version_cfm; /* Lower layers versions - obtained via MM_VERSION_REQ */
|
||||
|
||||
u32 tcp_pacing_shift;
|
||||
|
||||
@@ -656,15 +685,15 @@ struct rwnx_hw {
|
||||
//struct rwnx_ipc_rxbuf_elems rxbuf_elems;
|
||||
struct rwnx_ipc_elem_var scan_ie;
|
||||
|
||||
struct kmem_cache *sw_txhdr_cache;
|
||||
struct kmem_cache *sw_txhdr_cache;
|
||||
|
||||
struct rwnx_debugfs debugfs;
|
||||
struct rwnx_stats stats;
|
||||
struct rwnx_debugfs debugfs;
|
||||
struct rwnx_stats stats;
|
||||
|
||||
#ifdef CONFIG_PREALLOC_TXQ
|
||||
struct rwnx_txq *txq;
|
||||
struct rwnx_txq *txq;
|
||||
#else
|
||||
struct rwnx_txq txq[NX_NB_TXQ];
|
||||
struct rwnx_txq txq[NX_NB_TXQ];
|
||||
#endif
|
||||
|
||||
struct rwnx_hwq hwq[NX_TXQ_CNT];
|
||||
@@ -690,44 +719,48 @@ struct rwnx_hw {
|
||||
bool band_5g_support;
|
||||
u8_l vendor_info;
|
||||
bool fwlog_en;
|
||||
|
||||
|
||||
struct list_head defrag_list;
|
||||
spinlock_t defrag_lock;
|
||||
|
||||
struct work_struct apmStalossWork;
|
||||
struct workqueue_struct *apmStaloss_wq;
|
||||
u8 apm_vif_idx;
|
||||
u8 sta_mac_addr[6];
|
||||
struct work_struct apmStalossWork;
|
||||
struct workqueue_struct *apmStaloss_wq;
|
||||
u8 apm_vif_idx;
|
||||
u8 sta_mac_addr[6];
|
||||
|
||||
struct wakeup_source *ws_rx;
|
||||
struct wakeup_source *ws_irqrx;
|
||||
struct wakeup_source *ws_tx;
|
||||
struct wakeup_source *ws_pwrctrl;
|
||||
struct wakeup_source *ws_rx;
|
||||
struct wakeup_source *ws_irqrx;
|
||||
struct wakeup_source *ws_tx;
|
||||
struct wakeup_source *ws_pwrctrl;
|
||||
|
||||
#ifdef CONFIG_SCHED_SCAN
|
||||
bool is_sched_scan;
|
||||
#endif//CONFIG_SCHED_SCAN
|
||||
bool is_sched_scan;
|
||||
#endif //CONFIG_SCHED_SCAN
|
||||
#ifdef CONFIG_TEMP_CONTROL
|
||||
unsigned long started_jiffies;
|
||||
s8_l temp;
|
||||
#endif
|
||||
};
|
||||
|
||||
u8 *rwnx_build_bcn(struct rwnx_bcn *bcn, struct cfg80211_beacon_data *new);
|
||||
|
||||
void rwnx_chanctx_link(struct rwnx_vif *vif, u8 idx,
|
||||
struct cfg80211_chan_def *chandef);
|
||||
struct cfg80211_chan_def *chandef);
|
||||
void rwnx_chanctx_unlink(struct rwnx_vif *vif);
|
||||
int rwnx_chanctx_valid(struct rwnx_hw *rwnx_hw, u8 idx);
|
||||
int rwnx_chanctx_valid(struct rwnx_hw *rwnx_hw, u8 idx);
|
||||
|
||||
extern u8 chip_id;
|
||||
|
||||
static inline bool is_multicast_sta(int sta_idx)
|
||||
{
|
||||
if((g_rwnx_plat->sdiodev->chipid == PRODUCT_ID_AIC8801) ||
|
||||
((g_rwnx_plat->sdiodev->chipid == PRODUCT_ID_AIC8800DC || g_rwnx_plat->sdiodev->chipid == PRODUCT_ID_AIC8800DW) && chip_id < 3))
|
||||
{
|
||||
return (sta_idx >= NX_REMOTE_STA_MAX_FOR_OLD_IC);
|
||||
}else{
|
||||
return (sta_idx >= NX_REMOTE_STA_MAX);
|
||||
}
|
||||
|
||||
if ((g_rwnx_plat->sdiodev->chipid == PRODUCT_ID_AIC8801) ||
|
||||
((g_rwnx_plat->sdiodev->chipid == PRODUCT_ID_AIC8800DC ||
|
||||
g_rwnx_plat->sdiodev->chipid == PRODUCT_ID_AIC8800DW) &&
|
||||
chip_id < 3)) {
|
||||
return (sta_idx >= NX_REMOTE_STA_MAX_FOR_OLD_IC);
|
||||
} else {
|
||||
return (sta_idx >= NX_REMOTE_STA_MAX);
|
||||
}
|
||||
}
|
||||
struct rwnx_sta *rwnx_get_sta(struct rwnx_hw *rwnx_hw, const u8 *mac_addr);
|
||||
|
||||
|
||||
@@ -14,42 +14,40 @@
|
||||
#include "reg_access.h"
|
||||
|
||||
/* Config FPGA is accessed via bar0 */
|
||||
#define CFPGA_DMA0_CTRL_REG 0x02C
|
||||
#define CFPGA_DMA1_CTRL_REG 0x04C
|
||||
#define CFPGA_DMA2_CTRL_REG 0x06C
|
||||
#define CFPGA_UINTR_SRC_REG 0x0E8
|
||||
#define CFPGA_UINTR_MASK_REG 0x0EC
|
||||
#define CFPGA_BAR4_HIADDR_REG 0x100
|
||||
#define CFPGA_BAR4_LOADDR_REG 0x104
|
||||
#define CFPGA_BAR4_LOADDR_MASK_REG 0x110
|
||||
#define CFPGA_BAR_TOUT 0x120
|
||||
#define CFPGA_DMA0_CTRL_REG 0x02C
|
||||
#define CFPGA_DMA1_CTRL_REG 0x04C
|
||||
#define CFPGA_DMA2_CTRL_REG 0x06C
|
||||
#define CFPGA_UINTR_SRC_REG 0x0E8
|
||||
#define CFPGA_UINTR_MASK_REG 0x0EC
|
||||
#define CFPGA_BAR4_HIADDR_REG 0x100
|
||||
#define CFPGA_BAR4_LOADDR_REG 0x104
|
||||
#define CFPGA_BAR4_LOADDR_MASK_REG 0x110
|
||||
#define CFPGA_BAR_TOUT 0x120
|
||||
|
||||
#define CFPGA_DMA_CTRL_ENABLE 0x00001400
|
||||
#define CFPGA_DMA_CTRL_DISABLE 0x00001000
|
||||
#define CFPGA_DMA_CTRL_CLEAR 0x00001800
|
||||
#define CFPGA_DMA_CTRL_ENABLE 0x00001400
|
||||
#define CFPGA_DMA_CTRL_DISABLE 0x00001000
|
||||
#define CFPGA_DMA_CTRL_CLEAR 0x00001800
|
||||
#define CFPGA_DMA_CTRL_REREAD_TIME_MASK (BIT(10) - 1)
|
||||
|
||||
#define CFPGA_BAR4_LOADDR_MASK_MAX 0xFF000000
|
||||
#define CFPGA_BAR4_LOADDR_MASK_MAX 0xFF000000
|
||||
|
||||
#define CFPGA_PCIEX_IT 0x00000001
|
||||
#define CFPGA_ALL_ITS 0x0000000F
|
||||
#define CFPGA_PCIEX_IT 0x00000001
|
||||
#define CFPGA_ALL_ITS 0x0000000F
|
||||
|
||||
/* Programmable BAR4 Window start address */
|
||||
#define CPU_RAM_WINDOW_HIGH 0x00000000
|
||||
#define CPU_RAM_WINDOW_LOW 0x00000000
|
||||
#define AHB_BRIDGE_WINDOW_HIGH 0x00000000
|
||||
#define AHB_BRIDGE_WINDOW_LOW 0x60000000
|
||||
#define CPU_RAM_WINDOW_HIGH 0x00000000
|
||||
#define CPU_RAM_WINDOW_LOW 0x00000000
|
||||
#define AHB_BRIDGE_WINDOW_HIGH 0x00000000
|
||||
#define AHB_BRIDGE_WINDOW_LOW 0x60000000
|
||||
|
||||
struct rwnx_dini {
|
||||
u8 *pci_bar0_vaddr;
|
||||
u8 *pci_bar4_vaddr;
|
||||
};
|
||||
|
||||
static const u32 mv_cfg_fpga_dma_ctrl_regs[] = {
|
||||
CFPGA_DMA0_CTRL_REG,
|
||||
CFPGA_DMA1_CTRL_REG,
|
||||
CFPGA_DMA2_CTRL_REG
|
||||
};
|
||||
static const u32 mv_cfg_fpga_dma_ctrl_regs[] = { CFPGA_DMA0_CTRL_REG,
|
||||
CFPGA_DMA1_CTRL_REG,
|
||||
CFPGA_DMA2_CTRL_REG };
|
||||
|
||||
/* This also clears running transactions */
|
||||
static void dini_dma_on(struct rwnx_dini *rwnx_dini)
|
||||
@@ -62,7 +60,7 @@ static void dini_dma_on(struct rwnx_dini *rwnx_dini)
|
||||
reg = rwnx_dini->pci_bar0_vaddr + mv_cfg_fpga_dma_ctrl_regs[i];
|
||||
reread_time = readl(reg) & CFPGA_DMA_CTRL_REREAD_TIME_MASK;
|
||||
|
||||
writel(CFPGA_DMA_CTRL_CLEAR | reread_time, reg);
|
||||
writel(CFPGA_DMA_CTRL_CLEAR | reread_time, reg);
|
||||
writel(CFPGA_DMA_CTRL_ENABLE | reread_time, reg);
|
||||
}
|
||||
}
|
||||
@@ -79,11 +77,10 @@ static void dini_dma_off(struct rwnx_dini *rwnx_dini)
|
||||
reread_time = readl(reg) & CFPGA_DMA_CTRL_REREAD_TIME_MASK;
|
||||
|
||||
writel(CFPGA_DMA_CTRL_DISABLE | reread_time, reg);
|
||||
writel(CFPGA_DMA_CTRL_CLEAR | reread_time, reg);
|
||||
writel(CFPGA_DMA_CTRL_CLEAR | reread_time, reg);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Configure address range for BAR4.
|
||||
* By default BAR4_LOADDR_MASK value is 0xFF000000, then there is no need to
|
||||
* change it because the addresses we need to access are covered by this mask
|
||||
@@ -93,10 +90,9 @@ static void dini_set_bar4_win(u32 low, u32 high, struct rwnx_dini *rwnx_dini)
|
||||
writel(low, rwnx_dini->pci_bar0_vaddr + CFPGA_BAR4_LOADDR_REG);
|
||||
writel(high, rwnx_dini->pci_bar0_vaddr + CFPGA_BAR4_HIADDR_REG);
|
||||
writel(CFPGA_BAR4_LOADDR_MASK_MAX,
|
||||
rwnx_dini->pci_bar0_vaddr + CFPGA_BAR4_LOADDR_MASK_REG);
|
||||
rwnx_dini->pci_bar0_vaddr + CFPGA_BAR4_LOADDR_MASK_REG);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Enable User Interrupts of CFPGA that trigger PCIe IRQs on PCIE_10
|
||||
* and request the corresponding IRQ line
|
||||
@@ -110,7 +106,8 @@ int rwnx_cfpga_irq_enable(struct rwnx_hw *rwnx_hw)
|
||||
int ret;
|
||||
|
||||
/* sched_setscheduler on ONESHOT threaded irq handler for BCNs ? */
|
||||
ret = request_irq(rwnx_hw->plat->pci_dev->irq, rwnx_irq_hdlr, 0, "rwnx", rwnx_hw);
|
||||
ret = request_irq(rwnx_hw->plat->pci_dev->irq, rwnx_irq_hdlr, 0, "rwnx",
|
||||
rwnx_hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -178,7 +175,7 @@ static void rwnx_dini_platform_deinit(struct rwnx_plat *rwnx_plat)
|
||||
}
|
||||
|
||||
static u8 *rwnx_dini_get_address(struct rwnx_plat *rwnx_plat, int addr_name,
|
||||
unsigned int offset)
|
||||
unsigned int offset)
|
||||
{
|
||||
struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
|
||||
|
||||
@@ -186,9 +183,11 @@ static u8 *rwnx_dini_get_address(struct rwnx_plat *rwnx_plat, int addr_name,
|
||||
return NULL;
|
||||
|
||||
if (addr_name == RWNX_ADDR_CPU)
|
||||
dini_set_bar4_win(CPU_RAM_WINDOW_LOW, CPU_RAM_WINDOW_HIGH, rwnx_dini);
|
||||
dini_set_bar4_win(CPU_RAM_WINDOW_LOW, CPU_RAM_WINDOW_HIGH,
|
||||
rwnx_dini);
|
||||
else
|
||||
dini_set_bar4_win(AHB_BRIDGE_WINDOW_LOW, AHB_BRIDGE_WINDOW_HIGH, rwnx_dini);
|
||||
dini_set_bar4_win(AHB_BRIDGE_WINDOW_LOW, AHB_BRIDGE_WINDOW_HIGH,
|
||||
rwnx_dini);
|
||||
|
||||
return rwnx_dini->pci_bar4_vaddr + offset;
|
||||
}
|
||||
@@ -207,7 +206,8 @@ static const u32 rwnx_dini_config_reg[] = {
|
||||
RF_v6_PHYDIAG_CONF1_ADDR,
|
||||
};
|
||||
|
||||
static int rwnx_dini_get_config_reg(struct rwnx_plat *rwnx_plat, const u32 **list)
|
||||
static int rwnx_dini_get_config_reg(struct rwnx_plat *rwnx_plat,
|
||||
const u32 **list)
|
||||
{
|
||||
if (!list)
|
||||
return 0;
|
||||
@@ -226,14 +226,16 @@ static int rwnx_dini_get_config_reg(struct rwnx_plat *rwnx_plat, const u32 **lis
|
||||
*
|
||||
* Allocate and initialize a rwnx_plat structure for the dini platform.
|
||||
*/
|
||||
int rwnx_dini_platform_init(struct pci_dev *pci_dev, struct rwnx_plat **rwnx_plat)
|
||||
int rwnx_dini_platform_init(struct pci_dev *pci_dev,
|
||||
struct rwnx_plat **rwnx_plat)
|
||||
{
|
||||
struct rwnx_dini *rwnx_dini;
|
||||
u16 pci_cmd;
|
||||
int ret = 0;
|
||||
|
||||
*rwnx_plat = kzalloc(sizeof(struct rwnx_plat) + sizeof(struct rwnx_dini),
|
||||
GFP_KERNEL);
|
||||
*rwnx_plat =
|
||||
kzalloc(sizeof(struct rwnx_plat) + sizeof(struct rwnx_dini),
|
||||
GFP_KERNEL);
|
||||
if (!*rwnx_plat)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -289,7 +291,7 @@ out_bar4:
|
||||
iounmap(rwnx_dini->pci_bar0_vaddr);
|
||||
out_bar0:
|
||||
pci_release_regions(pci_dev);
|
||||
//out_request:
|
||||
//out_request:
|
||||
pci_disable_device(pci_dev);
|
||||
out_enable:
|
||||
kfree(*rwnx_plat);
|
||||
|
||||
@@ -15,6 +15,6 @@
|
||||
#include "rwnx_platform.h"
|
||||
|
||||
int rwnx_dini_platform_init(struct pci_dev *pci_dev,
|
||||
struct rwnx_plat **rwnx_plat);
|
||||
struct rwnx_plat **rwnx_plat);
|
||||
|
||||
#endif /* _RWNX_DINI_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -25,12 +25,14 @@ int rwnx_fw_log_init(struct rwnx_fw_log *fw_log)
|
||||
|
||||
fw_log->buf.data = buf;
|
||||
fw_log->buf.start = fw_log->buf.data;
|
||||
fw_log->buf.size = 0;
|
||||
fw_log->buf.end = fw_log->buf.data;
|
||||
fw_log->buf.size = 0;
|
||||
fw_log->buf.end = fw_log->buf.data;
|
||||
fw_log->buf.dataend = fw_log->buf.data + FW_LOG_SIZE;
|
||||
spin_lock_init(&fw_log->lock);
|
||||
|
||||
AICWFDBG(LOGINFO, "fw_log_init: %lx, %lx\n", (unsigned long)fw_log->buf.start, (unsigned long)(fw_log->buf.dataend));
|
||||
AICWFDBG(LOGINFO, "fw_log_init: %lx, %lx\n",
|
||||
(unsigned long)fw_log->buf.start,
|
||||
(unsigned long)(fw_log->buf.dataend));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -42,7 +44,6 @@ void rwnx_fw_log_deinit(struct rwnx_fw_log *fw_log)
|
||||
if (fw_log->buf.data)
|
||||
kfree(fw_log->buf.data);
|
||||
fw_log->buf.start = NULL;
|
||||
fw_log->buf.end = NULL;
|
||||
fw_log->buf.end = NULL;
|
||||
fw_log->buf.size = 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
static struct genl_family rwnx_nl80211_fam;
|
||||
|
||||
static bool __rwnx_cfg80211_unexpected_frame(struct net_device *dev, u8 cmd,
|
||||
const u8 *addr, gfp_t gfp)
|
||||
const u8 *addr, gfp_t gfp)
|
||||
{
|
||||
struct wireless_dev *wdev = dev->ieee80211_ptr;
|
||||
struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy);
|
||||
@@ -42,13 +42,13 @@ static bool __rwnx_cfg80211_unexpected_frame(struct net_device *dev, u8 cmd,
|
||||
genlmsg_unicast(wiphy_net(&rdev->wiphy), msg, nlportid);
|
||||
return true;
|
||||
|
||||
nla_put_failure:
|
||||
nla_put_failure:
|
||||
nlmsg_free(msg);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool rwnx_cfg80211_rx_spurious_frame(struct net_device *dev,
|
||||
const u8 *addr, gfp_t gfp)
|
||||
bool rwnx_cfg80211_rx_spurious_frame(struct net_device *dev, const u8 *addr,
|
||||
gfp_t gfp)
|
||||
{
|
||||
struct wireless_dev *wdev = dev->ieee80211_ptr;
|
||||
bool ret;
|
||||
@@ -57,13 +57,13 @@ bool rwnx_cfg80211_rx_spurious_frame(struct net_device *dev,
|
||||
wdev->iftype != NL80211_IFTYPE_P2P_GO)) {
|
||||
return false;
|
||||
}
|
||||
ret = __rwnx_cfg80211_unexpected_frame(dev, NL80211_CMD_UNEXPECTED_FRAME,
|
||||
addr, gfp);
|
||||
ret = __rwnx_cfg80211_unexpected_frame(
|
||||
dev, NL80211_CMD_UNEXPECTED_FRAME, addr, gfp);
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool rwnx_cfg80211_rx_unexpected_4addr_frame(struct net_device *dev,
|
||||
const u8 *addr, gfp_t gfp)
|
||||
const u8 *addr, gfp_t gfp)
|
||||
{
|
||||
struct wireless_dev *wdev = dev->ieee80211_ptr;
|
||||
bool ret;
|
||||
@@ -73,16 +73,15 @@ bool rwnx_cfg80211_rx_unexpected_4addr_frame(struct net_device *dev,
|
||||
wdev->iftype != NL80211_IFTYPE_AP_VLAN)) {
|
||||
return false;
|
||||
}
|
||||
ret = __rwnx_cfg80211_unexpected_frame(dev,
|
||||
NL80211_CMD_UNEXPECTED_4ADDR_FRAME,
|
||||
addr, gfp);
|
||||
ret = __rwnx_cfg80211_unexpected_frame(
|
||||
dev, NL80211_CMD_UNEXPECTED_4ADDR_FRAME, addr, gfp);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
|
||||
void rwnx_cfg80211_notify_new_peer_candidate(struct net_device *dev, const u8 *addr,
|
||||
const u8 *ie, u8 ie_len,
|
||||
int sig_dbm, gfp_t gfp)
|
||||
void rwnx_cfg80211_notify_new_peer_candidate(struct net_device *dev,
|
||||
const u8 *addr, const u8 *ie,
|
||||
u8 ie_len, int sig_dbm, gfp_t gfp)
|
||||
{
|
||||
struct wireless_dev *wdev = dev->ieee80211_ptr;
|
||||
struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy);
|
||||
@@ -96,7 +95,8 @@ void rwnx_cfg80211_notify_new_peer_candidate(struct net_device *dev, const u8 *a
|
||||
if (!msg)
|
||||
return;
|
||||
|
||||
hdr = genlmsg_put(msg, 0, 0, &rwnx_nl80211_fam, 0, NL80211_CMD_NEW_PEER_CANDIDATE);
|
||||
hdr = genlmsg_put(msg, 0, 0, &rwnx_nl80211_fam, 0,
|
||||
NL80211_CMD_NEW_PEER_CANDIDATE);
|
||||
if (!hdr) {
|
||||
nlmsg_free(msg);
|
||||
return;
|
||||
@@ -105,27 +105,24 @@ void rwnx_cfg80211_notify_new_peer_candidate(struct net_device *dev, const u8 *a
|
||||
if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) ||
|
||||
nla_put_u32(msg, NL80211_ATTR_IFINDEX, dev->ifindex) ||
|
||||
nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, addr) ||
|
||||
(ie_len && ie &&
|
||||
nla_put(msg, NL80211_ATTR_IE, ie_len, ie)) ||
|
||||
(sig_dbm &&
|
||||
nla_put_u32(msg, NL80211_ATTR_RX_SIGNAL_DBM, sig_dbm)))
|
||||
(ie_len && ie && nla_put(msg, NL80211_ATTR_IE, ie_len, ie)) ||
|
||||
(sig_dbm && nla_put_u32(msg, NL80211_ATTR_RX_SIGNAL_DBM, sig_dbm)))
|
||||
goto nla_put_failure;
|
||||
|
||||
genlmsg_end(msg, hdr);
|
||||
|
||||
#define NL80211_MCGRP_MLME 3
|
||||
genlmsg_multicast_netns(&rwnx_nl80211_fam, wiphy_net(&rdev->wiphy), msg, 0,
|
||||
NL80211_MCGRP_MLME, gfp);
|
||||
genlmsg_multicast_netns(&rwnx_nl80211_fam, wiphy_net(&rdev->wiphy), msg,
|
||||
0, NL80211_MCGRP_MLME, gfp);
|
||||
return;
|
||||
|
||||
nla_put_failure:
|
||||
nla_put_failure:
|
||||
nlmsg_free(msg);
|
||||
}
|
||||
#endif
|
||||
|
||||
void rwnx_cfg80211_report_obss_beacon(struct wiphy *wiphy,
|
||||
const u8 *frame, size_t len,
|
||||
int freq, int sig_dbm)
|
||||
void rwnx_cfg80211_report_obss_beacon(struct wiphy *wiphy, const u8 *frame,
|
||||
size_t len, int freq, int sig_dbm)
|
||||
{
|
||||
struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);
|
||||
struct sk_buff *msg;
|
||||
@@ -133,20 +130,20 @@ void rwnx_cfg80211_report_obss_beacon(struct wiphy *wiphy,
|
||||
struct cfg80211_beacon_registration *reg;
|
||||
|
||||
spin_lock_bh(&rdev->beacon_registrations_lock);
|
||||
list_for_each_entry(reg, &rdev->beacon_registrations, list) {
|
||||
list_for_each_entry (reg, &rdev->beacon_registrations, list) {
|
||||
msg = nlmsg_new(len + 100, GFP_ATOMIC);
|
||||
if (!msg) {
|
||||
spin_unlock_bh(&rdev->beacon_registrations_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
hdr = genlmsg_put(msg, 0, 0, &rwnx_nl80211_fam, 0, NL80211_CMD_FRAME);
|
||||
hdr = genlmsg_put(msg, 0, 0, &rwnx_nl80211_fam, 0,
|
||||
NL80211_CMD_FRAME);
|
||||
if (!hdr)
|
||||
goto nla_put_failure;
|
||||
|
||||
if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) ||
|
||||
(freq &&
|
||||
nla_put_u32(msg, NL80211_ATTR_WIPHY_FREQ, freq)) ||
|
||||
(freq && nla_put_u32(msg, NL80211_ATTR_WIPHY_FREQ, freq)) ||
|
||||
(sig_dbm &&
|
||||
nla_put_u32(msg, NL80211_ATTR_RX_SIGNAL_DBM, sig_dbm)) ||
|
||||
nla_put(msg, NL80211_ATTR_FRAME, len, frame))
|
||||
@@ -159,13 +156,13 @@ void rwnx_cfg80211_report_obss_beacon(struct wiphy *wiphy,
|
||||
spin_unlock_bh(&rdev->beacon_registrations_lock);
|
||||
return;
|
||||
|
||||
nla_put_failure:
|
||||
nla_put_failure:
|
||||
spin_unlock_bh(&rdev->beacon_registrations_lock);
|
||||
nlmsg_free(msg);
|
||||
}
|
||||
|
||||
static int rwnx_nl80211_send_chandef(struct sk_buff *msg,
|
||||
const struct cfg80211_chan_def *chandef)
|
||||
const struct cfg80211_chan_def *chandef)
|
||||
{
|
||||
if (WARN_ON(!cfg80211_chandef_valid(chandef)))
|
||||
return -EINVAL;
|
||||
@@ -195,11 +192,10 @@ static int rwnx_nl80211_send_chandef(struct sk_buff *msg,
|
||||
}
|
||||
|
||||
void rwnx_cfg80211_ch_switch_notify(struct cfg80211_registered_device *rdev,
|
||||
struct net_device *netdev,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
gfp_t gfp,
|
||||
enum nl80211_commands notif,
|
||||
u8 count)
|
||||
struct net_device *netdev,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
gfp_t gfp, enum nl80211_commands notif,
|
||||
u8 count)
|
||||
{
|
||||
struct sk_buff *msg;
|
||||
void *hdr;
|
||||
@@ -222,42 +218,45 @@ void rwnx_cfg80211_ch_switch_notify(struct cfg80211_registered_device *rdev,
|
||||
|
||||
if ((notif == NL80211_CMD_CH_SWITCH_STARTED_NOTIFY) &&
|
||||
(nla_put_u32(msg, NL80211_ATTR_CH_SWITCH_COUNT, count)))
|
||||
goto nla_put_failure;
|
||||
goto nla_put_failure;
|
||||
|
||||
genlmsg_end(msg, hdr);
|
||||
|
||||
genlmsg_multicast_netns(&rwnx_nl80211_fam, wiphy_net(&rdev->wiphy), msg, 0,
|
||||
NL80211_MCGRP_MLME, gfp);
|
||||
genlmsg_multicast_netns(&rwnx_nl80211_fam, wiphy_net(&rdev->wiphy), msg,
|
||||
0, NL80211_MCGRP_MLME, gfp);
|
||||
return;
|
||||
|
||||
nla_put_failure:
|
||||
nla_put_failure:
|
||||
nlmsg_free(msg);
|
||||
}
|
||||
|
||||
void rwnx_cfg80211_ch_switch_started_notify(struct net_device *dev,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
u8 count
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
|
||||
, bool quiet
|
||||
#endif
|
||||
)
|
||||
struct cfg80211_chan_def *chandef,
|
||||
u8 count
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
|
||||
,
|
||||
bool quiet
|
||||
#endif
|
||||
)
|
||||
{
|
||||
struct wireless_dev *wdev = dev->ieee80211_ptr;
|
||||
struct wiphy *wiphy = wdev->wiphy;
|
||||
struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);
|
||||
|
||||
rwnx_cfg80211_ch_switch_notify(rdev, dev, chandef, GFP_KERNEL,
|
||||
NL80211_CMD_CH_SWITCH_STARTED_NOTIFY, count);
|
||||
NL80211_CMD_CH_SWITCH_STARTED_NOTIFY,
|
||||
count);
|
||||
}
|
||||
|
||||
int rwnx_regulatory_set_wiphy_regd_sync_rtnl(struct wiphy *wiphy,
|
||||
struct ieee80211_regdomain *rd)
|
||||
struct ieee80211_regdomain *rd)
|
||||
{
|
||||
wiphy_apply_custom_regulatory(wiphy, rd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rwnx_skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list)
|
||||
void rwnx_skb_append(struct sk_buff *old, struct sk_buff *newsk,
|
||||
struct sk_buff_head *list)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct sk_buff *prev = old;
|
||||
@@ -271,8 +270,8 @@ void rwnx_skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_
|
||||
spin_unlock_irqrestore(&list->lock, flags);
|
||||
}
|
||||
|
||||
bool rwnx_ieee80211_chandef_to_operating_class(struct cfg80211_chan_def *chandef,
|
||||
u8 *op_class)
|
||||
bool rwnx_ieee80211_chandef_to_operating_class(
|
||||
struct cfg80211_chan_def *chandef, u8 *op_class)
|
||||
{
|
||||
u8 vht_opclass;
|
||||
u32 freq = chandef->center_freq1;
|
||||
@@ -400,7 +399,8 @@ bool rwnx_ieee80211_chandef_to_operating_class(struct cfg80211_chan_def *chandef
|
||||
return false;
|
||||
}
|
||||
|
||||
int rwnx_call_usermodehelper(const char *path, char **argv, char **envp, int wait)
|
||||
int rwnx_call_usermodehelper(const char *path, char **argv, char **envp,
|
||||
int wait)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
@@ -8,64 +8,68 @@
|
||||
//#if IS_ENABLED(CONFIG_GKI_OPT_FEATURES) && IS_ENABLED(CONFIG_ANDROID) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
|
||||
|
||||
|
||||
bool rwnx_cfg80211_rx_spurious_frame(struct net_device *dev,
|
||||
const u8 *addr, gfp_t gfp);
|
||||
bool rwnx_cfg80211_rx_spurious_frame(struct net_device *dev, const u8 *addr,
|
||||
gfp_t gfp);
|
||||
|
||||
bool rwnx_cfg80211_rx_unexpected_4addr_frame(struct net_device *dev,
|
||||
const u8 *addr, gfp_t gfp);
|
||||
const u8 *addr, gfp_t gfp);
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
|
||||
void rwnx_cfg80211_notify_new_peer_candidate(struct net_device *dev, const u8 *addr,
|
||||
const u8 *ie, u8 ie_len,
|
||||
int sig_dbm, gfp_t gfp);
|
||||
void rwnx_cfg80211_notify_new_peer_candidate(struct net_device *dev,
|
||||
const u8 *addr, const u8 *ie,
|
||||
u8 ie_len, int sig_dbm, gfp_t gfp);
|
||||
#endif
|
||||
|
||||
void rwnx_cfg80211_report_obss_beacon(struct wiphy *wiphy,
|
||||
const u8 *frame, size_t len,
|
||||
int freq, int sig_dbm);
|
||||
void rwnx_cfg80211_report_obss_beacon(struct wiphy *wiphy, const u8 *frame,
|
||||
size_t len, int freq, int sig_dbm);
|
||||
|
||||
void rwnx_cfg80211_ch_switch_notify(struct cfg80211_registered_device *rdev,
|
||||
struct net_device *netdev,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
gfp_t gfp,
|
||||
enum nl80211_commands notif,
|
||||
u8 count);
|
||||
struct net_device *netdev,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
gfp_t gfp, enum nl80211_commands notif,
|
||||
u8 count);
|
||||
|
||||
void rwnx_cfg80211_ch_switch_started_notify(struct net_device *dev,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
u8 count
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
|
||||
, bool quiet
|
||||
#endif
|
||||
);
|
||||
struct cfg80211_chan_def *chandef,
|
||||
u8 count
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
|
||||
,
|
||||
bool quiet
|
||||
#endif
|
||||
);
|
||||
|
||||
int rwnx_regulatory_set_wiphy_regd_sync_rtnl(struct wiphy *wiphy,
|
||||
struct ieee80211_regdomain *rd);
|
||||
struct ieee80211_regdomain *rd);
|
||||
|
||||
void rwnx_skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list);
|
||||
void rwnx_skb_append(struct sk_buff *old, struct sk_buff *newsk,
|
||||
struct sk_buff_head *list);
|
||||
|
||||
bool rwnx_ieee80211_chandef_to_operating_class(struct cfg80211_chan_def *chandef,
|
||||
u8 *op_class);
|
||||
bool rwnx_ieee80211_chandef_to_operating_class(
|
||||
struct cfg80211_chan_def *chandef, u8 *op_class);
|
||||
|
||||
int rwnx_call_usermodehelper(const char *path, char **argv, char **envp, int wait);
|
||||
int rwnx_call_usermodehelper(const char *path, char **argv, char **envp,
|
||||
int wait);
|
||||
|
||||
#else
|
||||
|
||||
#define rwnx_cfg80211_rx_spurious_frame cfg80211_rx_spurious_frame
|
||||
#define rwnx_cfg80211_rx_unexpected_4addr_frame cfg80211_rx_unexpected_4addr_frame
|
||||
#define rwnx_cfg80211_rx_spurious_frame cfg80211_rx_spurious_frame
|
||||
#define rwnx_cfg80211_rx_unexpected_4addr_frame \
|
||||
cfg80211_rx_unexpected_4addr_frame
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
|
||||
#define rwnx_cfg80211_notify_new_peer_candidate cfg80211_notify_new_peer_candidate
|
||||
#define rwnx_cfg80211_notify_new_peer_candidate \
|
||||
cfg80211_notify_new_peer_candidate
|
||||
#endif
|
||||
|
||||
#define rwnx_cfg80211_report_obss_beacon cfg80211_report_obss_beacon
|
||||
#define rwnx_cfg80211_ch_switch_notify cfg80211_ch_switch_notify
|
||||
#define rwnx_cfg80211_ch_switch_started_notify cfg80211_ch_switch_started_notify
|
||||
#define rwnx_regulatory_set_wiphy_regd_sync_rtnl regulatory_set_wiphy_regd_sync_rtnl
|
||||
#define rwnx_skb_append skb_append
|
||||
#define rwnx_ieee80211_chandef_to_operating_class ieee80211_chandef_to_operating_class
|
||||
#define rwnx_call_usermodehelper call_usermodehelper
|
||||
#define rwnx_cfg80211_report_obss_beacon cfg80211_report_obss_beacon
|
||||
#define rwnx_cfg80211_ch_switch_notify cfg80211_ch_switch_notify
|
||||
#define rwnx_cfg80211_ch_switch_started_notify cfg80211_ch_switch_started_notify
|
||||
#define rwnx_regulatory_set_wiphy_regd_sync_rtnl \
|
||||
regulatory_set_wiphy_regd_sync_rtnl
|
||||
#define rwnx_skb_append skb_append
|
||||
#define rwnx_ieee80211_chandef_to_operating_class \
|
||||
ieee80211_chandef_to_operating_class
|
||||
#define rwnx_call_usermodehelper call_usermodehelper
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -20,7 +20,7 @@ extern u8 chip_sub_id;
|
||||
extern u8 chip_mcu_id;
|
||||
extern u8 chip_id;
|
||||
|
||||
#define CHIP_ID_H_MASK 0xC0
|
||||
#define IS_CHIP_ID_H() ((chip_id & CHIP_ID_H_MASK) == CHIP_ID_H_MASK)
|
||||
#define CHIP_ID_H_MASK 0xC0
|
||||
#define IS_CHIP_ID_H() ((chip_id & CHIP_ID_H_MASK) == CHIP_ID_H_MASK)
|
||||
|
||||
#endif /* _RWNX_MAIN_H_ */
|
||||
|
||||
@@ -20,13 +20,14 @@
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
struct rwnx_mesh_proxy *rwnx_get_mesh_proxy_info(struct rwnx_vif *p_rwnx_vif, u8 *p_sta_addr, bool local)
|
||||
struct rwnx_mesh_proxy *rwnx_get_mesh_proxy_info(struct rwnx_vif *p_rwnx_vif,
|
||||
u8 *p_sta_addr, bool local)
|
||||
{
|
||||
struct rwnx_mesh_proxy *p_mesh_proxy = NULL;
|
||||
struct rwnx_mesh_proxy *p_cur_proxy;
|
||||
|
||||
/* Look for proxied devices with provided address */
|
||||
list_for_each_entry(p_cur_proxy, &p_rwnx_vif->ap.proxy_list, list) {
|
||||
list_for_each_entry (p_cur_proxy, &p_rwnx_vif->ap.proxy_list, list) {
|
||||
if (p_cur_proxy->local != local) {
|
||||
continue;
|
||||
}
|
||||
|
||||
@@ -40,6 +40,7 @@
|
||||
* @brief TODO [LT]
|
||||
****************************************************************************************
|
||||
*/
|
||||
struct rwnx_mesh_proxy *rwnx_get_mesh_proxy_info(struct rwnx_vif *p_rwnx_vif, u8 *p_sta_addr, bool local);
|
||||
struct rwnx_mesh_proxy *rwnx_get_mesh_proxy_info(struct rwnx_vif *p_rwnx_vif,
|
||||
u8 *p_sta_addr, bool local);
|
||||
|
||||
#endif /* _RWNX_MESH_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -66,5 +66,10 @@ int rwnx_handle_dynparams(struct rwnx_hw *rwnx_hw, struct wiphy *wiphy);
|
||||
void rwnx_custregd(struct rwnx_hw *rwnx_hw, struct wiphy *wiphy);
|
||||
void rwnx_enable_wapi(struct rwnx_hw *rwnx_hw);
|
||||
void rwnx_enable_mfp(struct rwnx_hw *rwnx_hw);
|
||||
struct ieee80211_regdomain *getRegdomainFromRwnxDB(struct wiphy *wiphy,
|
||||
char *alpha2);
|
||||
|
||||
struct ieee80211_regdomain *getRegdomainFromRwnxDBIndex(struct wiphy *wiphy,
|
||||
int index);
|
||||
|
||||
#endif /* _RWNX_MOD_PARAM_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -18,169 +18,213 @@
|
||||
int rwnx_send_reset(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_start(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_version_req(struct rwnx_hw *rwnx_hw, struct mm_version_cfm *cfm);
|
||||
int rwnx_send_add_if (struct rwnx_hw *rwnx_hw, const unsigned char *mac,
|
||||
enum nl80211_iftype iftype, bool p2p, struct mm_add_if_cfm *cfm);
|
||||
int rwnx_send_remove_if (struct rwnx_hw *rwnx_hw, u8 vif_index, bool defer);
|
||||
int rwnx_send_add_if(struct rwnx_hw *rwnx_hw, const unsigned char *mac,
|
||||
enum nl80211_iftype iftype, bool p2p,
|
||||
struct mm_add_if_cfm *cfm);
|
||||
int rwnx_send_remove_if(struct rwnx_hw *rwnx_hw, u8 vif_index, bool defer);
|
||||
int rwnx_send_set_channel(struct rwnx_hw *rwnx_hw, int phy_idx,
|
||||
struct mm_set_channel_cfm *cfm);
|
||||
int rwnx_send_key_add(struct rwnx_hw *rwnx_hw, u8 vif_idx, u8 sta_idx, bool pairwise,
|
||||
u8 *key, u8 key_len, u8 key_idx, u8 cipher_suite,
|
||||
struct mm_key_add_cfm *cfm);
|
||||
struct mm_set_channel_cfm *cfm);
|
||||
int rwnx_send_key_add(struct rwnx_hw *rwnx_hw, u8 vif_idx, u8 sta_idx,
|
||||
bool pairwise, u8 *key, u8 key_len, u8 key_idx,
|
||||
u8 cipher_suite, struct mm_key_add_cfm *cfm);
|
||||
int rwnx_send_key_del(struct rwnx_hw *rwnx_hw, uint8_t hw_key_idx);
|
||||
int rwnx_send_bcn(struct rwnx_hw *rwnx_hw, u8 *buf, u8 vif_idx, u16 bcn_len);
|
||||
|
||||
int rwnx_send_bcn_change(struct rwnx_hw *rwnx_hw, u8 vif_idx, u32 bcn_addr,
|
||||
u16 bcn_len, u16 tim_oft, u16 tim_len, u16 *csa_oft);
|
||||
u16 bcn_len, u16 tim_oft, u16 tim_len, u16 *csa_oft);
|
||||
int rwnx_send_tim_update(struct rwnx_hw *rwnx_hw, u8 vif_idx, u16 aid,
|
||||
u8 tx_status);
|
||||
u8 tx_status);
|
||||
int rwnx_send_roc(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
struct ieee80211_channel *chan, unsigned int duration, struct mm_remain_on_channel_cfm *roc_cfm);
|
||||
struct ieee80211_channel *chan, unsigned int duration,
|
||||
struct mm_remain_on_channel_cfm *roc_cfm);
|
||||
int rwnx_send_cancel_roc(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_set_power(struct rwnx_hw *rwnx_hw, u8 vif_idx, s8 pwr,
|
||||
struct mm_set_power_cfm *cfm);
|
||||
int rwnx_send_set_power(struct rwnx_hw *rwnx_hw, u8 vif_idx, s8 pwr,
|
||||
struct mm_set_power_cfm *cfm);
|
||||
int rwnx_send_set_edca(struct rwnx_hw *rwnx_hw, u8 hw_queue, u32 param,
|
||||
bool uapsd, u8 inst_nbr);
|
||||
int rwnx_send_tdls_chan_switch_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif,
|
||||
struct rwnx_sta *rwnx_sta, bool sta_initiator,
|
||||
u8 oper_class, struct cfg80211_chan_def *chandef,
|
||||
struct tdls_chan_switch_cfm *cfm);
|
||||
int rwnx_send_tdls_cancel_chan_switch_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *rwnx_vif,
|
||||
struct rwnx_sta *rwnx_sta,
|
||||
struct tdls_cancel_chan_switch_cfm *cfm);
|
||||
bool uapsd, u8 inst_nbr);
|
||||
int rwnx_send_tdls_chan_switch_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *rwnx_vif,
|
||||
struct rwnx_sta *rwnx_sta,
|
||||
bool sta_initiator, u8 oper_class,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
struct tdls_chan_switch_cfm *cfm);
|
||||
int rwnx_send_tdls_cancel_chan_switch_req(
|
||||
struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif,
|
||||
struct rwnx_sta *rwnx_sta, struct tdls_cancel_chan_switch_cfm *cfm);
|
||||
|
||||
#ifdef CONFIG_RWNX_P2P_DEBUGFS
|
||||
int rwnx_send_p2p_oppps_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif,
|
||||
u8 ctw, struct mm_set_p2p_oppps_cfm *cfm);
|
||||
u8 ctw, struct mm_set_p2p_oppps_cfm *cfm);
|
||||
int rwnx_send_p2p_noa_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif,
|
||||
int count, int interval, int duration,
|
||||
bool dyn_noa, struct mm_set_p2p_noa_cfm *cfm);
|
||||
int count, int interval, int duration, bool dyn_noa,
|
||||
struct mm_set_p2p_noa_cfm *cfm);
|
||||
#endif /* CONFIG_RWNX_P2P_DEBUGFS */
|
||||
|
||||
#ifdef AICWF_ARP_OFFLOAD
|
||||
int rwnx_send_arpoffload_en_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif,
|
||||
u32_l ipaddr, u8_l enable);
|
||||
int rwnx_send_arpoffload_en_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *rwnx_vif, u32_l ipaddr,
|
||||
u8_l enable);
|
||||
#endif
|
||||
int rwnx_send_rf_config_req(struct rwnx_hw *rwnx_hw, u8_l ofst, u8_l sel, u8_l *tbl, u16_l len);
|
||||
int rwnx_send_rf_calib_req(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm);
|
||||
int rwnx_send_get_macaddr_req(struct rwnx_hw *rwnx_hw, struct mm_get_mac_addr_cfm *cfm);
|
||||
int rwnx_send_rf_config_req(struct rwnx_hw *rwnx_hw, u8_l ofst, u8_l sel,
|
||||
u8_l *tbl, u16_l len);
|
||||
int rwnx_send_rf_calib_req(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_set_rf_calib_cfm *cfm);
|
||||
int rwnx_send_get_macaddr_req(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_get_mac_addr_cfm *cfm);
|
||||
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
int rwnx_send_me_config_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_me_chan_config_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_me_chan_config_req(struct rwnx_hw *rwnx_hw, char *ccode);
|
||||
int rwnx_send_me_set_control_port_req(struct rwnx_hw *rwnx_hw, bool opened,
|
||||
u8 sta_idx);
|
||||
int rwnx_send_me_sta_add(struct rwnx_hw *rwnx_hw, struct station_parameters *params,
|
||||
const u8 *mac, u8 inst_nbr, struct me_sta_add_cfm *cfm);
|
||||
u8 sta_idx);
|
||||
int rwnx_send_me_sta_add(struct rwnx_hw *rwnx_hw,
|
||||
struct station_parameters *params, const u8 *mac,
|
||||
u8 inst_nbr, struct me_sta_add_cfm *cfm);
|
||||
int rwnx_send_me_sta_del(struct rwnx_hw *rwnx_hw, u8 sta_idx, bool tdls_sta);
|
||||
int rwnx_send_me_traffic_ind(struct rwnx_hw *rwnx_hw, u8 sta_idx, bool uapsd, u8 tx_status);
|
||||
int rwnx_send_me_traffic_ind(struct rwnx_hw *rwnx_hw, u8 sta_idx, bool uapsd,
|
||||
u8 tx_status);
|
||||
int rwnx_send_me_rc_stats(struct rwnx_hw *rwnx_hw, u8 sta_idx,
|
||||
struct me_rc_stats_cfm *cfm);
|
||||
int rwnx_send_me_rc_set_rate(struct rwnx_hw *rwnx_hw,
|
||||
u8 sta_idx,
|
||||
u16 rate_idx);
|
||||
struct me_rc_stats_cfm *cfm);
|
||||
int rwnx_send_me_rc_set_rate(struct rwnx_hw *rwnx_hw, u8 sta_idx, u16 rate_idx);
|
||||
int rwnx_send_me_set_ps_mode(struct rwnx_hw *rwnx_hw, u8 ps_mode);
|
||||
int rwnx_send_me_set_lp_level(struct rwnx_hw *rwnx_hw, u8 lp_level);
|
||||
int rwnx_send_sm_connect_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *rwnx_vif,
|
||||
struct cfg80211_connect_params *sme,
|
||||
struct sm_connect_cfm *cfm);
|
||||
int rwnx_send_me_set_lp_level(struct rwnx_hw *rwnx_hw, u8 lp_level,
|
||||
u8 disable_filter);
|
||||
int rwnx_send_sm_connect_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif,
|
||||
struct cfg80211_connect_params *sme,
|
||||
struct sm_connect_cfm *cfm);
|
||||
int rwnx_send_sm_disconnect_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *rwnx_vif,
|
||||
u16 reason);
|
||||
struct rwnx_vif *rwnx_vif, u16 reason);
|
||||
int rwnx_send_sm_external_auth_required_rsp(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *rwnx_vif,
|
||||
u16 status);
|
||||
struct rwnx_vif *rwnx_vif,
|
||||
u16 status);
|
||||
int rwnx_send_apm_start_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
struct cfg80211_ap_settings *settings,
|
||||
struct apm_start_cfm *cfm,
|
||||
struct rwnx_ipc_elem_var *elem);
|
||||
struct cfg80211_ap_settings *settings,
|
||||
struct apm_start_cfm *cfm,
|
||||
struct rwnx_ipc_elem_var *elem);
|
||||
int rwnx_send_apm_stop_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif);
|
||||
int rwnx_send_scanu_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif,
|
||||
struct cfg80211_scan_request *param);
|
||||
struct cfg80211_scan_request *param);
|
||||
int rwnx_send_scanu_cancel_req(struct rwnx_hw *rwnx_hw,
|
||||
struct scan_cancel_cfm *cfm);
|
||||
struct scan_cancel_cfm *cfm);
|
||||
|
||||
int rwnx_send_apm_start_cac_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
struct apm_start_cac_cfm *cfm);
|
||||
struct cfg80211_chan_def *chandef,
|
||||
struct apm_start_cac_cfm *cfm);
|
||||
int rwnx_send_apm_stop_cac_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif);
|
||||
int rwnx_send_tdls_peer_traffic_ind_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif);
|
||||
int rwnx_send_tdls_peer_traffic_ind_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *rwnx_vif);
|
||||
int rwnx_send_config_monitor_req(struct rwnx_hw *rwnx_hw,
|
||||
struct cfg80211_chan_def *chandef,
|
||||
struct me_config_monitor_cfm *cfm);
|
||||
struct cfg80211_chan_def *chandef,
|
||||
struct me_config_monitor_cfm *cfm);
|
||||
int rwnx_send_mesh_start_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
const struct mesh_config *conf, const struct mesh_setup *setup,
|
||||
struct mesh_start_cfm *cfm);
|
||||
const struct mesh_config *conf,
|
||||
const struct mesh_setup *setup,
|
||||
struct mesh_start_cfm *cfm);
|
||||
int rwnx_send_mesh_stop_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
struct mesh_stop_cfm *cfm);
|
||||
struct mesh_stop_cfm *cfm);
|
||||
int rwnx_send_mesh_update_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
u32 mask, const struct mesh_config *p_mconf, struct mesh_update_cfm *cfm);
|
||||
u32 mask, const struct mesh_config *p_mconf,
|
||||
struct mesh_update_cfm *cfm);
|
||||
int rwnx_send_mesh_peer_info_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
u8 sta_idx, struct mesh_peer_info_cfm *cfm);
|
||||
void rwnx_send_mesh_peer_update_ntf(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
u8 sta_idx, u8 mlink_state);
|
||||
void rwnx_send_mesh_path_create_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif, u8 *tgt_addr);
|
||||
int rwnx_send_mesh_path_update_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif, const u8 *tgt_addr,
|
||||
const u8 *p_nhop_addr, struct mesh_path_update_cfm *cfm);
|
||||
void rwnx_send_mesh_proxy_add_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif, u8 *ext_addr);
|
||||
u8 sta_idx, struct mesh_peer_info_cfm *cfm);
|
||||
void rwnx_send_mesh_peer_update_ntf(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *vif, u8 sta_idx,
|
||||
u8 mlink_state);
|
||||
void rwnx_send_mesh_path_create_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *vif, u8 *tgt_addr);
|
||||
int rwnx_send_mesh_path_update_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_vif *vif, const u8 *tgt_addr,
|
||||
const u8 *p_nhop_addr,
|
||||
struct mesh_path_update_cfm *cfm);
|
||||
void rwnx_send_mesh_proxy_add_req(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||||
u8 *ext_addr);
|
||||
#endif /* CONFIG_RWNX_FULLMAC */
|
||||
|
||||
#ifdef CONFIG_RWNX_BFMER
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
void rwnx_send_bfmer_enable(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta,
|
||||
const struct ieee80211_vht_cap *vht_cap);
|
||||
const struct ieee80211_vht_cap *vht_cap);
|
||||
#endif /* CONFIG_RWNX_FULLMAC */
|
||||
#ifdef CONFIG_RWNX_MUMIMO_TX
|
||||
int rwnx_send_mu_group_update_req(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta);
|
||||
int rwnx_send_mu_group_update_req(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_sta *rwnx_sta);
|
||||
#endif /* CONFIG_RWNX_MUMIMO_TX */
|
||||
#endif /* CONFIG_RWNX_BFMER */
|
||||
|
||||
/* Debug messages */
|
||||
int rwnx_send_dbg_trigger_req(struct rwnx_hw *rwnx_hw, char *msg);
|
||||
int rwnx_send_dbg_mem_read_req(struct rwnx_hw *rwnx_hw, u32 mem_addr,
|
||||
struct dbg_mem_read_cfm *cfm);
|
||||
struct dbg_mem_read_cfm *cfm);
|
||||
int rwnx_send_dbg_mem_write_req(struct rwnx_hw *rwnx_hw, u32 mem_addr,
|
||||
u32 mem_data);
|
||||
u32 mem_data);
|
||||
int rwnx_send_dbg_mem_mask_write_req(struct rwnx_hw *rwnx_hw, u32 mem_addr,
|
||||
u32 mem_mask, u32 mem_data);
|
||||
u32 mem_mask, u32 mem_data);
|
||||
int rwnx_send_dbg_set_mod_filter_req(struct rwnx_hw *rwnx_hw, u32 filter);
|
||||
#ifdef CONFIG_RFTEST
|
||||
int rwnx_send_rftest_req(struct rwnx_hw *rwnx_hw, u32_l cmd, u32_l argc, u8_l *argv, struct dbg_rftest_cmd_cfm *cfm);
|
||||
int rwnx_send_rftest_req(struct rwnx_hw *rwnx_hw, u32_l cmd, u32_l argc,
|
||||
u8_l *argv, struct dbg_rftest_cmd_cfm *cfm);
|
||||
#endif
|
||||
#ifdef CONFIG_MCU_MESSAGE
|
||||
int rwnx_send_dbg_custom_msg_req(struct rwnx_hw *rwnx_hw,
|
||||
u32 cmd, void *buf, u32 len, u32 action,
|
||||
struct dbg_custom_msg_cfm *cfm);
|
||||
int rwnx_send_dbg_custom_msg_req(struct rwnx_hw *rwnx_hw, u32 cmd, void *buf,
|
||||
u32 len, u32 action,
|
||||
struct dbg_custom_msg_cfm *cfm);
|
||||
#endif
|
||||
int rwnx_send_dbg_set_sev_filter_req(struct rwnx_hw *rwnx_hw, u32 filter);
|
||||
int rwnx_send_dbg_get_sys_stat_req(struct rwnx_hw *rwnx_hw,
|
||||
struct dbg_get_sys_stat_cfm *cfm);
|
||||
struct dbg_get_sys_stat_cfm *cfm);
|
||||
int rwnx_send_dbg_mem_block_write_req(struct rwnx_hw *rwnx_hw, u32 mem_addr,
|
||||
u32 mem_size, u32 *mem_data);
|
||||
u32 mem_size, u32 *mem_data);
|
||||
int rwnx_send_dbg_mem_block_read_req(struct rwnx_hw *rwnx_hw, u32 mem_addr,
|
||||
u32 mem_size,
|
||||
struct dbg_mem_block_read_cfm *cfm);
|
||||
int rwnx_send_dbg_start_app_req(struct rwnx_hw *rwnx_hw, u32 boot_addr,
|
||||
u32 boot_type);
|
||||
int rwnx_send_cfg_rssi_req(struct rwnx_hw *rwnx_hw, u8 vif_index, int rssi_thold, u32 rssi_hyst);
|
||||
int rwnx_send_disable_agg_req(struct rwnx_hw *rwnx_hw, u8_l agg_disable, u8_l agg_disable_rx, u8_l sta_idx);
|
||||
int rwnx_send_coex_req(struct rwnx_hw *rwnx_hw, u8_l disable_coexnull, u8_l enable_nullcts);
|
||||
int rwnx_send_get_sta_info_req(struct rwnx_hw *rwnx_hw, u8_l sta_idx, struct mm_get_sta_info_cfm *cfm);
|
||||
int rwnx_send_set_stack_start_req(struct rwnx_hw *rwnx_hw, u8_l on, u8_l efuse_valid, u8_l set_vendor_info,
|
||||
u8_l fwtrace_redir_en, struct mm_set_stack_start_cfm *cfm);
|
||||
int rwnx_send_txop_req(struct rwnx_hw *rwnx_hw, uint16_t *txop, u8_l long_nav_en, u8_l cfe_en);
|
||||
int rwnx_send_set_temp_comp_req(struct rwnx_hw *rwnx_hw, struct mm_set_vendor_swconfig_cfm *cfm);
|
||||
int rwnx_send_vendor_hwconfig_req(struct rwnx_hw *rwnx_hw, uint32_t hwconfig_id, int32_t *param, int32_t *param_out);
|
||||
int rwnx_send_vendor_swconfig_req(struct rwnx_hw *rwnx_hw, uint32_t swconfig_id, int32_t *param_in, int32_t *param_out);
|
||||
int rwnx_send_mask_set_ext_flags_req(struct rwnx_hw *rwnx_hw, uint32_t flags_mask, uint32_t flags_val, struct mm_set_vendor_swconfig_cfm *cfm);
|
||||
int rwnx_send_get_fw_version_req(struct rwnx_hw *rwnx_hw, struct mm_get_fw_version_cfm *cfm);
|
||||
u32 boot_type);
|
||||
int rwnx_send_cfg_rssi_req(struct rwnx_hw *rwnx_hw, u8 vif_index,
|
||||
int rssi_thold, u32 rssi_hyst);
|
||||
int rwnx_send_disable_agg_req(struct rwnx_hw *rwnx_hw, u8_l agg_disable,
|
||||
u8_l agg_disable_rx, u8_l sta_idx);
|
||||
int rwnx_send_coex_req(struct rwnx_hw *rwnx_hw, u8_l disable_coexnull,
|
||||
u8_l enable_nullcts);
|
||||
int rwnx_send_get_sta_info_req(struct rwnx_hw *rwnx_hw, u8_l sta_idx,
|
||||
struct mm_get_sta_info_cfm *cfm);
|
||||
int rwnx_send_set_stack_start_req(struct rwnx_hw *rwnx_hw, u8_l on,
|
||||
u8_l efuse_valid, u8_l set_vendor_info,
|
||||
u8_l fwtrace_redir_en,
|
||||
struct mm_set_stack_start_cfm *cfm);
|
||||
int rwnx_send_txop_req(struct rwnx_hw *rwnx_hw, uint16_t *txop,
|
||||
u8_l long_nav_en, u8_l cfe_en);
|
||||
int rwnx_send_get_temp_req(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_set_vendor_swconfig_cfm *cfm);
|
||||
int rwnx_send_set_temp_comp_req(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_set_vendor_swconfig_cfm *cfm);
|
||||
int rwnx_send_vendor_hwconfig_req(struct rwnx_hw *rwnx_hw, uint32_t hwconfig_id,
|
||||
int32_t *param, int32_t *param_out);
|
||||
int rwnx_send_vendor_swconfig_req(struct rwnx_hw *rwnx_hw, uint32_t swconfig_id,
|
||||
int32_t *param_in, int32_t *param_out);
|
||||
int rwnx_send_mask_set_ext_flags_req(struct rwnx_hw *rwnx_hw,
|
||||
uint32_t flags_mask, uint32_t flags_val,
|
||||
struct mm_set_vendor_swconfig_cfm *cfm);
|
||||
int rwnx_send_get_fw_version_req(struct rwnx_hw *rwnx_hw,
|
||||
struct mm_get_fw_version_cfm *cfm);
|
||||
int rwnx_send_txpwr_idx_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_txpwr_ofst_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_txpwr_ofst2x_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_txpwr_ofst2x_v2_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_set_filter(struct rwnx_hw *rwnx_hw, uint32_t filter);
|
||||
int rwnx_send_txpwr_lvl_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_txpwr_lvl_v3_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_txpwr_lvl_v4_req(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_send_txpwr_lvl_adj_req(struct rwnx_hw *rwnx_hw);
|
||||
#ifdef CONFIG_APF
|
||||
int rwnx_send_set_apf_prog_req(struct rwnx_hw *rwnx_hw, u8_l *program,
|
||||
u32_l program_len);
|
||||
int rwnx_send_get_apf_prog_req(struct rwnx_hw *rwnx_hw, u8_l *program,
|
||||
u32_l program_len);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_BT
|
||||
int rwnx_sdio_bt_send_req(struct rwnx_hw *rwnx_hw,uint32_t len, struct sk_buff *skb);
|
||||
int rwnx_sdio_bt_send_req(struct rwnx_hw *rwnx_hw, uint32_t len,
|
||||
struct sk_buff *skb);
|
||||
#endif
|
||||
|
||||
#endif /* _RWNX_MSG_TX_H_ */
|
||||
|
||||
@@ -12,14 +12,13 @@
|
||||
#include "rwnx_msg_tx.h"
|
||||
#include "rwnx_events.h"
|
||||
|
||||
|
||||
/**
|
||||
* rwnx_mu_group_sta_init - Initialize group information for a STA
|
||||
*
|
||||
* @sta: Sta to initialize
|
||||
*/
|
||||
void rwnx_mu_group_sta_init(struct rwnx_sta *sta,
|
||||
const struct ieee80211_vht_cap *vht_cap)
|
||||
const struct ieee80211_vht_cap *vht_cap)
|
||||
{
|
||||
sta->group_info.map = 0;
|
||||
sta->group_info.cnt = 0;
|
||||
@@ -29,9 +28,9 @@ void rwnx_mu_group_sta_init(struct rwnx_sta *sta,
|
||||
sta->group_info.traffic = 0;
|
||||
sta->group_info.group = 0;
|
||||
|
||||
if (!vht_cap ||
|
||||
!(vht_cap->vht_cap_info & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE)) {
|
||||
sta->group_info.map = RWNX_SU_GROUP;
|
||||
if (!vht_cap || !(vht_cap->vht_cap_info &
|
||||
IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE)) {
|
||||
sta->group_info.map = RWNX_SU_GROUP;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -52,8 +51,10 @@ void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta)
|
||||
|
||||
lock_taken = (down_interruptible(&mu->lock) == 0);
|
||||
|
||||
group_sta_for_each(sta, group_id, map) {
|
||||
struct rwnx_mu_group *group = rwnx_mu_group_from_id(mu, group_id);
|
||||
group_sta_for_each(sta, group_id, map)
|
||||
{
|
||||
struct rwnx_mu_group *group =
|
||||
rwnx_mu_group_from_id(mu, group_id);
|
||||
|
||||
for (i = 0; i < CONFIG_USER_MAX; i++) {
|
||||
if (group->users[i] == sta) {
|
||||
@@ -63,10 +64,21 @@ void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta)
|
||||
if (group->user_cnt == 1) {
|
||||
for (j = 0; j < CONFIG_USER_MAX; j++) {
|
||||
if (group->users[j]) {
|
||||
group->users[j]->group_info.cnt--;
|
||||
group->users[j]->group_info.map &= ~BIT_ULL(group->group_id);
|
||||
if (group->users[j]->group_info.group == group_id)
|
||||
group->users[j]->group_info.group = 0;
|
||||
group->users[j]
|
||||
->group_info
|
||||
.cnt--;
|
||||
group->users[j]
|
||||
->group_info
|
||||
.map &= ~BIT_ULL(
|
||||
group->group_id);
|
||||
if (group->users[j]
|
||||
->group_info
|
||||
.group ==
|
||||
group_id)
|
||||
group->users[j]
|
||||
->group_info
|
||||
.group =
|
||||
0;
|
||||
group->user_cnt--;
|
||||
break;
|
||||
}
|
||||
@@ -80,8 +92,9 @@ void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta)
|
||||
}
|
||||
}
|
||||
|
||||
WARN((i == CONFIG_USER_MAX), "sta %d doesn't belongs to group %d",
|
||||
sta->sta_idx, group_id);
|
||||
WARN((i == CONFIG_USER_MAX),
|
||||
"sta %d doesn't belongs to group %d", sta->sta_idx,
|
||||
group_id);
|
||||
}
|
||||
|
||||
sta->group_info.map = 0;
|
||||
@@ -123,7 +136,7 @@ u64 rwnx_mu_group_sta_get_map(struct rwnx_sta *sta)
|
||||
* doesn't belongs to the group (or group id is invalid)
|
||||
*/
|
||||
int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
int group_id)
|
||||
int group_id)
|
||||
{
|
||||
struct rwnx_mu_group *group;
|
||||
int i;
|
||||
@@ -137,8 +150,7 @@ int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
return i;
|
||||
}
|
||||
|
||||
WARN(1, "sta %d doesn't belongs to group %d",
|
||||
sta->sta_idx, group_id);
|
||||
WARN(1, "sta %d doesn't belongs to group %d", sta->sta_idx, group_id);
|
||||
return -1;
|
||||
}
|
||||
|
||||
@@ -149,8 +161,8 @@ int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
* @elem: element to move (or add) at the top of @list
|
||||
*
|
||||
*/
|
||||
static inline
|
||||
void rwnx_mu_group_move_head(struct list_head *list, struct list_head *elem)
|
||||
static inline void rwnx_mu_group_move_head(struct list_head *list,
|
||||
struct list_head *elem)
|
||||
{
|
||||
if (elem->next != LIST_POISON1) {
|
||||
__list_del_entry(elem);
|
||||
@@ -169,9 +181,8 @@ void rwnx_mu_group_move_head(struct list_head *list, struct list_head *elem)
|
||||
* Each users is also added to the update_sta list, so that group info
|
||||
* will be resent to fw for this user.
|
||||
*/
|
||||
static inline
|
||||
void rwnx_mu_group_remove_users(struct rwnx_mu_info *mu,
|
||||
struct rwnx_mu_group *group)
|
||||
static inline void rwnx_mu_group_remove_users(struct rwnx_mu_info *mu,
|
||||
struct rwnx_mu_group *group)
|
||||
{
|
||||
struct rwnx_sta *sta;
|
||||
int i, group_id = group->group_id;
|
||||
@@ -183,7 +194,7 @@ void rwnx_mu_group_remove_users(struct rwnx_mu_info *mu,
|
||||
sta->group_info.cnt--;
|
||||
sta->group_info.map &= ~BIT_ULL(group_id);
|
||||
rwnx_mu_group_move_head(&mu->update_sta,
|
||||
&sta->group_info.update);
|
||||
&sta->group_info.update);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -208,10 +219,9 @@ void rwnx_mu_group_remove_users(struct rwnx_mu_info *mu,
|
||||
* Each users (effectively added to @group) is also added to the update_sta
|
||||
* list, so that group info will be resent to fw for this user.
|
||||
*/
|
||||
static inline
|
||||
void rwnx_mu_group_add_users(struct rwnx_mu_info *mu,
|
||||
struct rwnx_mu_group *group,
|
||||
int nb_user, struct rwnx_sta **users)
|
||||
static inline void rwnx_mu_group_add_users(struct rwnx_mu_info *mu,
|
||||
struct rwnx_mu_group *group,
|
||||
int nb_user, struct rwnx_sta **users)
|
||||
{
|
||||
int i, j, group_id = group->group_id;
|
||||
|
||||
@@ -219,30 +229,30 @@ void rwnx_mu_group_add_users(struct rwnx_mu_info *mu,
|
||||
mu->group_cnt++;
|
||||
|
||||
j = 0;
|
||||
for (i = 0; i < nb_user ; i++) {
|
||||
for (; j < CONFIG_USER_MAX ; j++) {
|
||||
for (i = 0; i < nb_user; i++) {
|
||||
for (; j < CONFIG_USER_MAX; j++) {
|
||||
if (group->users[j] == NULL) {
|
||||
group->users[j] = users[i];
|
||||
users[i]->group_info.cnt++;
|
||||
users[i]->group_info.map |= BIT_ULL(group_id);
|
||||
|
||||
rwnx_mu_group_move_head(&(mu->update_sta),
|
||||
&(users[i]->group_info.update));
|
||||
rwnx_mu_group_move_head(
|
||||
&(mu->update_sta),
|
||||
&(users[i]->group_info.update));
|
||||
group->user_cnt++;
|
||||
j++;
|
||||
break;
|
||||
}
|
||||
|
||||
WARN(j == (CONFIG_USER_MAX - 1),
|
||||
"Too many user for group %d (nb_user=%d)",
|
||||
group_id, group->user_cnt + nb_user - i);
|
||||
"Too many user for group %d (nb_user=%d)",
|
||||
group_id, group->user_cnt + nb_user - i);
|
||||
}
|
||||
}
|
||||
|
||||
trace_mu_group_update(group);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* rwnx_mu_group_create_one - create on group with a specific group of user
|
||||
*
|
||||
@@ -264,9 +274,8 @@ void rwnx_mu_group_add_users(struct rwnx_mu_info *mu,
|
||||
*
|
||||
* @return 1 if a new group has been created and 0 otherwise
|
||||
*/
|
||||
static
|
||||
int rwnx_mu_group_create_one(struct rwnx_mu_info *mu, int nb_user,
|
||||
struct rwnx_sta **users, int *nb_group_left)
|
||||
static int rwnx_mu_group_create_one(struct rwnx_mu_info *mu, int nb_user,
|
||||
struct rwnx_sta **users, int *nb_group_left)
|
||||
{
|
||||
int i, group_id;
|
||||
struct rwnx_mu_group *group;
|
||||
@@ -275,10 +284,9 @@ int rwnx_mu_group_create_one(struct rwnx_mu_info *mu, int nb_user,
|
||||
|
||||
group_match = users[0]->group_info.map;
|
||||
group_avail = users[0]->group_info.map;
|
||||
for (i = 1; i < nb_user ; i++) {
|
||||
for (i = 1; i < nb_user; i++) {
|
||||
group_match &= users[i]->group_info.map;
|
||||
group_avail |= users[i]->group_info.map;
|
||||
|
||||
}
|
||||
|
||||
if (group_match) {
|
||||
@@ -295,22 +303,26 @@ int rwnx_mu_group_create_one(struct rwnx_mu_info *mu, int nb_user,
|
||||
struct rwnx_sta *users2[CONFIG_USER_MAX];
|
||||
int nb_user2;
|
||||
|
||||
group_for_each(group_id, group_avail) {
|
||||
group_for_each(group_id, group_avail)
|
||||
{
|
||||
group = rwnx_mu_group_from_id(mu, group_id);
|
||||
if (group->user_cnt == CONFIG_USER_MAX)
|
||||
continue;
|
||||
|
||||
nb_user2 = 0;
|
||||
for (i = 0; i < nb_user ; i++) {
|
||||
if (!(users[i]->group_info.map & BIT_ULL(group_id))) {
|
||||
for (i = 0; i < nb_user; i++) {
|
||||
if (!(users[i]->group_info.map &
|
||||
BIT_ULL(group_id))) {
|
||||
users2[nb_user2] = users[i];
|
||||
nb_user2++;
|
||||
}
|
||||
}
|
||||
|
||||
if ((group->user_cnt + nb_user2) <= CONFIG_USER_MAX) {
|
||||
rwnx_mu_group_add_users(mu, group, nb_user2, users2);
|
||||
rwnx_mu_group_move_head(&mu->active_groups, &group->list);
|
||||
rwnx_mu_group_add_users(mu, group, nb_user2,
|
||||
users2);
|
||||
rwnx_mu_group_move_head(&mu->active_groups,
|
||||
&group->list);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@@ -342,9 +354,8 @@ int rwnx_mu_group_create_one(struct rwnx_mu_info *mu, int nb_user,
|
||||
* Loops end when there is no more users, or no more new group is allowed
|
||||
*
|
||||
*/
|
||||
static
|
||||
void rwnx_mu_group_create(struct rwnx_mu_info *mu, struct rwnx_sta *sta,
|
||||
int *nb_group_left)
|
||||
static void rwnx_mu_group_create(struct rwnx_mu_info *mu, struct rwnx_sta *sta,
|
||||
int *nb_group_left)
|
||||
{
|
||||
struct rwnx_sta *user_sta = sta;
|
||||
struct rwnx_sta *users[CONFIG_USER_MAX];
|
||||
@@ -352,8 +363,8 @@ void rwnx_mu_group_create(struct rwnx_mu_info *mu, struct rwnx_sta *sta,
|
||||
|
||||
users[0] = sta;
|
||||
while (*nb_group_left) {
|
||||
|
||||
list_for_each_entry_continue(user_sta, &mu->active_sta, group_info.active) {
|
||||
list_for_each_entry_continue (user_sta, &mu->active_sta,
|
||||
group_info.active) {
|
||||
users[nb_user] = user_sta;
|
||||
if (++nb_user == CONFIG_USER_MAX) {
|
||||
break;
|
||||
@@ -361,7 +372,8 @@ void rwnx_mu_group_create(struct rwnx_mu_info *mu, struct rwnx_sta *sta,
|
||||
}
|
||||
|
||||
if (nb_user > 1) {
|
||||
if (rwnx_mu_group_create_one(mu, nb_user, users, nb_group_left))
|
||||
if (rwnx_mu_group_create_one(mu, nb_user, users,
|
||||
nb_group_left))
|
||||
(*nb_group_left)--;
|
||||
|
||||
if (nb_user < CONFIG_USER_MAX)
|
||||
@@ -413,13 +425,14 @@ void rwnx_mu_group_create(struct rwnx_mu_info *mu, struct rwnx_sta *sta,
|
||||
void rwnx_mu_group_work(struct work_struct *ws)
|
||||
{
|
||||
struct delayed_work *dw = container_of(ws, struct delayed_work, work);
|
||||
struct rwnx_mu_info *mu = container_of(dw, struct rwnx_mu_info, group_work);
|
||||
struct rwnx_mu_info *mu =
|
||||
container_of(dw, struct rwnx_mu_info, group_work);
|
||||
struct rwnx_hw *rwnx_hw = container_of(mu, struct rwnx_hw, mu);
|
||||
struct rwnx_sta *sta, *next;
|
||||
int nb_group_left = NX_MU_GROUP_MAX;
|
||||
|
||||
if (WARN(!rwnx_hw->mod_params->mutx,
|
||||
"In group formation work, but mutx disabled"))
|
||||
"In group formation work, but mutx disabled"))
|
||||
return;
|
||||
|
||||
if (down_interruptible(&mu->lock) != 0)
|
||||
@@ -429,7 +442,8 @@ void rwnx_mu_group_work(struct work_struct *ws)
|
||||
if (!mu->update_count)
|
||||
mu->update_count++;
|
||||
|
||||
list_for_each_entry_safe(sta, next, &mu->active_sta, group_info.active) {
|
||||
list_for_each_entry_safe (sta, next, &mu->active_sta,
|
||||
group_info.active) {
|
||||
if (nb_group_left)
|
||||
rwnx_mu_group_create(mu, sta, &nb_group_left);
|
||||
|
||||
@@ -438,7 +452,8 @@ void rwnx_mu_group_work(struct work_struct *ws)
|
||||
}
|
||||
|
||||
if (!list_empty(&mu->update_sta)) {
|
||||
list_for_each_entry_safe(sta, next, &mu->update_sta, group_info.update) {
|
||||
list_for_each_entry_safe (sta, next, &mu->update_sta,
|
||||
group_info.update) {
|
||||
rwnx_send_mu_group_update_req(rwnx_hw, sta);
|
||||
list_del(&sta->group_info.update);
|
||||
}
|
||||
@@ -505,7 +520,7 @@ void rwnx_mu_group_init(struct rwnx_hw *rwnx_hw)
|
||||
* It is called with mu->lock taken.
|
||||
*/
|
||||
void rwnx_mu_set_active_sta(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
int traffic)
|
||||
int traffic)
|
||||
{
|
||||
struct rwnx_mu_info *mu = &rwnx_hw->mu;
|
||||
|
||||
@@ -515,14 +530,15 @@ void rwnx_mu_set_active_sta(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
sta->group_info.traffic += traffic;
|
||||
|
||||
if ((sta->group_info.last_update != mu->update_count) ||
|
||||
!list_empty(&mu->active_sta)) {
|
||||
|
||||
rwnx_mu_group_move_head(&mu->active_sta, &sta->group_info.active);
|
||||
!list_empty(&mu->active_sta)) {
|
||||
rwnx_mu_group_move_head(&mu->active_sta,
|
||||
&sta->group_info.active);
|
||||
|
||||
if (!delayed_work_pending(&mu->group_work) &&
|
||||
!list_is_singular(&mu->active_sta)) {
|
||||
schedule_delayed_work(&mu->group_work,
|
||||
msecs_to_jiffies(RWNX_MU_GROUP_INTERVAL));
|
||||
!list_is_singular(&mu->active_sta)) {
|
||||
schedule_delayed_work(
|
||||
&mu->group_work,
|
||||
msecs_to_jiffies(RWNX_MU_GROUP_INTERVAL));
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -543,7 +559,6 @@ void rwnx_mu_set_active_group(struct rwnx_hw *rwnx_hw, int group_id)
|
||||
rwnx_mu_group_move_head(&mu->active_groups, &group->list);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* rwnx_mu_group_sta_select - Select the best group for MU stas
|
||||
*
|
||||
@@ -580,8 +595,7 @@ void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw)
|
||||
if (!mu->group_cnt || time_before(jiffies, mu->next_group_select))
|
||||
return;
|
||||
|
||||
list_for_each_entry(vif, &rwnx_hw->vifs, list) {
|
||||
|
||||
list_for_each_entry (vif, &rwnx_hw->vifs, list) {
|
||||
if (RWNX_VIF_TYPE(vif) != NL80211_IFTYPE_AP)
|
||||
continue;
|
||||
|
||||
@@ -593,7 +607,7 @@ void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw)
|
||||
|
||||
memset(nb_users, 0, sizeof(nb_users));
|
||||
memset(traffic, 0, sizeof(traffic));
|
||||
list_for_each_entry(sta, head, list) {
|
||||
list_for_each_entry (sta, head, list) {
|
||||
int sta_traffic = sta->group_info.traffic;
|
||||
|
||||
/* reset statistics for next selection */
|
||||
@@ -603,10 +617,11 @@ void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw)
|
||||
sta->group_info.group = 0;
|
||||
|
||||
if (sta->group_info.cnt == 0 ||
|
||||
sta_traffic < RWNX_MU_GROUP_MIN_TRAFFIC)
|
||||
sta_traffic < RWNX_MU_GROUP_MIN_TRAFFIC)
|
||||
continue;
|
||||
|
||||
group_sta_for_each(sta, group_id, map) {
|
||||
group_sta_for_each(sta, group_id, map)
|
||||
{
|
||||
nb_users[group_id]++;
|
||||
traffic[group_id] += sta_traffic;
|
||||
|
||||
@@ -641,10 +656,14 @@ void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw)
|
||||
group = rwnx_mu_group_from_id(mu, group_id);
|
||||
for (j = 0; j < CONFIG_USER_MAX; j++) {
|
||||
if (group->users[j]) {
|
||||
trace_mu_group_selection(group->users[j], group_id);
|
||||
group->users[j]->group_info.group = group_id;
|
||||
trace_mu_group_selection(
|
||||
group->users[j], group_id);
|
||||
group->users[j]->group_info.group =
|
||||
group_id;
|
||||
|
||||
group_sta_for_each(group->users[j], tmp, map) {
|
||||
group_sta_for_each(group->users[j], tmp,
|
||||
map)
|
||||
{
|
||||
if (group_id != tmp)
|
||||
nb_users[tmp]--;
|
||||
}
|
||||
@@ -653,7 +672,7 @@ void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw)
|
||||
}
|
||||
}
|
||||
|
||||
mu->next_group_select = jiffies +
|
||||
msecs_to_jiffies(RWNX_MU_GROUP_SELECT_INTERVAL);
|
||||
mu->next_group_select =
|
||||
jiffies + msecs_to_jiffies(RWNX_MU_GROUP_SELECT_INTERVAL);
|
||||
mu->next_group_select |= 1;
|
||||
}
|
||||
|
||||
@@ -36,7 +36,7 @@ struct rwnx_sta_group_info {
|
||||
int cnt;
|
||||
u64 map;
|
||||
int traffic;
|
||||
u8 group;
|
||||
u8 group;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -92,25 +92,24 @@ struct rwnx_mu_info {
|
||||
// minimum traffic in a RWNX_MU_GROUP_SELECT_INTERVAL to consider the sta
|
||||
#define RWNX_MU_GROUP_MIN_TRAFFIC 50 /* in number of packet */
|
||||
|
||||
|
||||
#define RWNX_GET_FIRST_GROUP_ID(map) (fls64(map) - 1)
|
||||
|
||||
#define group_sta_for_each(sta, id, map) \
|
||||
do { \
|
||||
map = sta->group_info.map & RWNX_MU_GROUP_MASK; \
|
||||
for (id = (fls64(map) - 1) ; id > 0 ; \
|
||||
map &= ~(u64)BIT_ULL(id), id = (fls64(map) - 1)) \
|
||||
#define group_sta_for_each(sta, id, map) \
|
||||
do { \
|
||||
map = sta->group_info.map & RWNX_MU_GROUP_MASK; \
|
||||
for (id = (fls64(map) - 1); id > 0; \
|
||||
map &= ~(u64)BIT_ULL(id), id = (fls64(map) - 1)) \
|
||||
} while (0)
|
||||
|
||||
#define group_for_each(id, map) \
|
||||
for (id = (fls64(map) - 1) ; id > 0 ; \
|
||||
map &= ~(u64)BIT_ULL(id), id = (fls64(map) - 1))
|
||||
#define group_for_each(id, map) \
|
||||
for (id = (fls64(map) - 1); id > 0; \
|
||||
map &= ~(u64)BIT_ULL(id), id = (fls64(map) - 1))
|
||||
|
||||
#define RWNX_MUMIMO_INFO_POS_ID(info) (((info) >> 6) & 0x3)
|
||||
#define RWNX_MUMIMO_INFO_GROUP_ID(info) ((info) & 0x3f)
|
||||
#define RWNX_MUMIMO_INFO_GROUP_ID(info) ((info)&0x3f)
|
||||
|
||||
static inline
|
||||
struct rwnx_mu_group *rwnx_mu_group_from_id(struct rwnx_mu_info *mu, int id)
|
||||
static inline struct rwnx_mu_group *
|
||||
rwnx_mu_group_from_id(struct rwnx_mu_info *mu, int id)
|
||||
{
|
||||
if (id > NX_MU_GROUP_MAX)
|
||||
return NULL;
|
||||
@@ -118,64 +117,62 @@ struct rwnx_mu_group *rwnx_mu_group_from_id(struct rwnx_mu_info *mu, int id)
|
||||
return &mu->groups[id - 1];
|
||||
}
|
||||
|
||||
|
||||
void rwnx_mu_group_sta_init(struct rwnx_sta *sta,
|
||||
const struct ieee80211_vht_cap *vht_cap);
|
||||
const struct ieee80211_vht_cap *vht_cap);
|
||||
void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta);
|
||||
u64 rwnx_mu_group_sta_get_map(struct rwnx_sta *sta);
|
||||
int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
int group_id);
|
||||
int group_id);
|
||||
|
||||
void rwnx_mu_group_init(struct rwnx_hw *rwnx_hw);
|
||||
|
||||
void rwnx_mu_set_active_sta(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
int traffic);
|
||||
int traffic);
|
||||
void rwnx_mu_set_active_group(struct rwnx_hw *rwnx_hw, int group_id);
|
||||
void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw);
|
||||
|
||||
|
||||
#else /* ! CONFIG_RWNX_MUMIMO_TX */
|
||||
|
||||
static inline
|
||||
void rwnx_mu_group_sta_init(struct rwnx_sta *sta,
|
||||
const struct ieee80211_vht_cap *vht_cap)
|
||||
{}
|
||||
static inline void
|
||||
rwnx_mu_group_sta_init(struct rwnx_sta *sta,
|
||||
const struct ieee80211_vht_cap *vht_cap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline
|
||||
void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta)
|
||||
{}
|
||||
static inline void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_sta *sta)
|
||||
{
|
||||
}
|
||||
|
||||
static inline
|
||||
u64 rwnx_mu_group_sta_get_map(struct rwnx_sta *sta)
|
||||
static inline u64 rwnx_mu_group_sta_get_map(struct rwnx_sta *sta)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline
|
||||
int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
int group_id)
|
||||
static inline int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_sta *sta, int group_id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline
|
||||
void rwnx_mu_group_init(struct rwnx_hw *rwnx_hw)
|
||||
{}
|
||||
static inline void rwnx_mu_group_init(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
}
|
||||
|
||||
static inline
|
||||
void rwnx_mu_set_active_sta(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta,
|
||||
int traffic)
|
||||
{}
|
||||
static inline void rwnx_mu_set_active_sta(struct rwnx_hw *rwnx_hw,
|
||||
struct rwnx_sta *sta, int traffic)
|
||||
{
|
||||
}
|
||||
|
||||
static inline
|
||||
void rwnx_mu_set_active_group(struct rwnx_hw *rwnx_hw, int group_id)
|
||||
{}
|
||||
static inline void rwnx_mu_set_active_group(struct rwnx_hw *rwnx_hw,
|
||||
int group_id)
|
||||
{
|
||||
}
|
||||
|
||||
static inline
|
||||
void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw)
|
||||
{}
|
||||
static inline void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RWNX_MUMIMO_TX */
|
||||
|
||||
#endif /* _RWNX_MU_GROUP_H_ */
|
||||
|
||||
|
||||
@@ -14,24 +14,26 @@
|
||||
#include "rwnx_dini.h"
|
||||
#include "rwnx_v7.h"
|
||||
|
||||
#define PCI_VENDOR_ID_DINIGROUP 0x17DF
|
||||
#define PCI_DEVICE_ID_DINIGROUP_DNV6_F2PCIE 0x1907
|
||||
#define PCI_VENDOR_ID_DINIGROUP 0x17DF
|
||||
#define PCI_DEVICE_ID_DINIGROUP_DNV6_F2PCIE 0x1907
|
||||
|
||||
#define PCI_DEVICE_ID_XILINX_CEVA_VIRTEX7 0x7011
|
||||
#define PCI_DEVICE_ID_XILINX_CEVA_VIRTEX7 0x7011
|
||||
|
||||
static const struct pci_device_id rwnx_pci_ids[] = {
|
||||
{PCI_DEVICE(PCI_VENDOR_ID_DINIGROUP, PCI_DEVICE_ID_DINIGROUP_DNV6_F2PCIE)},
|
||||
{PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_XILINX_CEVA_VIRTEX7)},
|
||||
{0,}
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_DINIGROUP,
|
||||
PCI_DEVICE_ID_DINIGROUP_DNV6_F2PCIE) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_XILINX_CEVA_VIRTEX7) },
|
||||
{
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
/* Uncomment this for depmod to create module alias */
|
||||
/* We don't want this on development platform */
|
||||
//MODULE_DEVICE_TABLE(pci, rwnx_pci_ids);
|
||||
|
||||
static int rwnx_pci_probe(struct pci_dev *pci_dev,
|
||||
const struct pci_device_id *pci_id)
|
||||
const struct pci_device_id *pci_id)
|
||||
{
|
||||
struct rwnx_plat *rwnx_plat = NULL;
|
||||
void *drvdata;
|
||||
@@ -75,12 +77,10 @@ static void rwnx_pci_remove(struct pci_dev *pci_dev)
|
||||
pci_set_drvdata(pci_dev, NULL);
|
||||
}
|
||||
|
||||
static struct pci_driver rwnx_pci_drv = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = rwnx_pci_ids,
|
||||
.probe = rwnx_pci_probe,
|
||||
.remove = rwnx_pci_remove
|
||||
};
|
||||
static struct pci_driver rwnx_pci_drv = { .name = KBUILD_MODNAME,
|
||||
.id_table = rwnx_pci_ids,
|
||||
.probe = rwnx_pci_probe,
|
||||
.remove = rwnx_pci_remove };
|
||||
|
||||
int rwnx_pci_register_drv(void)
|
||||
{
|
||||
@@ -91,4 +91,3 @@ void rwnx_pci_unregister_drv(void)
|
||||
{
|
||||
pci_unregister_driver(&rwnx_pci_drv);
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -14,27 +14,27 @@
|
||||
#include <linux/pci.h>
|
||||
#include "lmac_msg.h"
|
||||
|
||||
#define RWNX_CONFIG_FW_NAME "rwnx_settings.ini"
|
||||
#define RWNX_PHY_CONFIG_TRD_NAME "rwnx_trident.ini"
|
||||
#define RWNX_PHY_CONFIG_KARST_NAME "rwnx_karst.ini"
|
||||
#define RWNX_AGC_FW_NAME "agcram.bin"
|
||||
#define RWNX_LDPC_RAM_NAME "ldpcram.bin"
|
||||
#define RWNX_CONFIG_FW_NAME "rwnx_settings.ini"
|
||||
#define RWNX_PHY_CONFIG_TRD_NAME "rwnx_trident.ini"
|
||||
#define RWNX_PHY_CONFIG_KARST_NAME "rwnx_karst.ini"
|
||||
#define RWNX_AGC_FW_NAME "agcram.bin"
|
||||
#define RWNX_LDPC_RAM_NAME "ldpcram.bin"
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
#define RWNX_MAC_FW_BASE_NAME "fmacfw"
|
||||
#define RWNX_MAC_FW_BASE_NAME "fmacfw"
|
||||
#elif defined CONFIG_RWNX_FHOST
|
||||
#define RWNX_MAC_FW_BASE_NAME "fhostfw"
|
||||
#define RWNX_MAC_FW_BASE_NAME "fhostfw"
|
||||
#endif /* CONFIG_RWNX_FULLMAC */
|
||||
|
||||
#ifdef CONFIG_RWNX_TL4
|
||||
#define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME".hex"
|
||||
#define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME ".hex"
|
||||
#else
|
||||
#define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME".ihex"
|
||||
#define RWNX_MAC_FW_NAME2 RWNX_MAC_FW_BASE_NAME".bin"
|
||||
#define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME ".ihex"
|
||||
#define RWNX_MAC_FW_NAME2 RWNX_MAC_FW_BASE_NAME ".bin"
|
||||
#endif
|
||||
|
||||
#define RWNX_FCU_FW_NAME "fcuram.bin"
|
||||
#define RWNX_FCU_FW_NAME "fcuram.bin"
|
||||
#if (defined(CONFIG_DPD) && !defined(CONFIG_FORCE_DPD_CALIB))
|
||||
#define FW_DPDRESULT_NAME_8800DC "aic_dpdresult_lite_8800dc.bin"
|
||||
#define FW_DPDRESULT_NAME_8800DC "aic_dpdresult_lite_8800dc.bin"
|
||||
#endif
|
||||
|
||||
/**
|
||||
@@ -51,6 +51,16 @@ enum rwnx_platform_addr {
|
||||
RWNX_ADDR_MAX,
|
||||
};
|
||||
|
||||
#define POWER_LEVEL_INVALID_VAL (127)
|
||||
|
||||
typedef enum {
|
||||
REGIONS_SRRC,
|
||||
REGIONS_FCC,
|
||||
REGIONS_ETSI,
|
||||
REGIONS_JP,
|
||||
REGIONS_DEFAULT,
|
||||
} Regions_code;
|
||||
|
||||
struct rwnx_hw;
|
||||
|
||||
/**
|
||||
@@ -86,21 +96,20 @@ struct rwnx_plat {
|
||||
int (*enable)(struct rwnx_hw *rwnx_hw);
|
||||
int (*disable)(struct rwnx_hw *rwnx_hw);
|
||||
void (*deinit)(struct rwnx_plat *rwnx_plat);
|
||||
u8* (*get_address)(struct rwnx_plat *rwnx_plat, int addr_name,
|
||||
unsigned int offset);
|
||||
u8 *(*get_address)(struct rwnx_plat *rwnx_plat, int addr_name,
|
||||
unsigned int offset);
|
||||
void (*ack_irq)(struct rwnx_plat *rwnx_plat);
|
||||
int (*get_config_reg)(struct rwnx_plat *rwnx_plat, const u32 **list);
|
||||
|
||||
u8 priv[0] __aligned(sizeof(void *));
|
||||
};
|
||||
|
||||
#define RWNX_ADDR(plat, base, offset) \
|
||||
plat->get_address(plat, base, offset)
|
||||
#define RWNX_ADDR(plat, base, offset) plat->get_address(plat, base, offset)
|
||||
|
||||
#define RWNX_REG_READ(plat, base, offset) \
|
||||
#define RWNX_REG_READ(plat, base, offset) \
|
||||
readl(plat->get_address(plat, base, offset))
|
||||
|
||||
#define RWNX_REG_WRITE(val, plat, base, offset) \
|
||||
#define RWNX_REG_WRITE(val, plat, base, offset) \
|
||||
writel(val, plat->get_address(plat, base, offset))
|
||||
|
||||
extern struct rwnx_plat *g_rwnx_plat;
|
||||
@@ -123,10 +132,23 @@ void set_txpwr_loss_ofst(s8_l value);
|
||||
void get_userconfig_txpwr_lvl_in_fdrv(txpwr_lvl_conf_t *txpwr_lvl);
|
||||
void get_userconfig_txpwr_lvl_v2_in_fdrv(txpwr_lvl_conf_v2_t *txpwr_lvl_v2);
|
||||
void get_userconfig_txpwr_lvl_v3_in_fdrv(txpwr_lvl_conf_v3_t *txpwr_lvl_v3);
|
||||
void get_userconfig_txpwr_lvl_v4_in_fdrv(txpwr_lvl_conf_v4_t *txpwr_lvl_v4);
|
||||
void get_userconfig_txpwr_lvl_adj_in_fdrv(txpwr_lvl_adj_conf_t *txpwr_lvl_adj);
|
||||
uint8_t get_ccode_region(char *ccode);
|
||||
u8 get_region_index(char *name);
|
||||
|
||||
#ifdef CONFIG_POWER_LIMIT
|
||||
int8_t rwnx_plat_powerlimit_save(u8_l band, char *channel, u8_l bw, char *limit,
|
||||
char *name);
|
||||
void rwnx_plat_powerlimit_parsing(char *buffer, int size, char *cc);
|
||||
int8_t get_powerlimit_by_freq(uint8_t band, uint16_t freq, uint8_t r_idx);
|
||||
int8_t get_powerlimit_by_chnum(uint8_t chnum, uint8_t r_idx, uint8_t bw);
|
||||
#endif
|
||||
|
||||
void get_userconfig_txpwr_ofst_in_fdrv(txpwr_ofst_conf_t *txpwr_ofst);
|
||||
void get_userconfig_txpwr_ofst2x_in_fdrv(txpwr_ofst2x_conf_t *txpwr_ofst2x);
|
||||
void get_userconfig_txpwr_ofst2x_v2_in_fdrv(
|
||||
txpwr_ofst2x_conf_v2_t *txpwr_ofst2x_v2);
|
||||
void get_userconfig_txpwr_loss(txpwr_loss_conf_t *txpwr_loss);
|
||||
extern struct device *rwnx_platform_get_dev(struct rwnx_plat *rwnx_plat);
|
||||
|
||||
|
||||
@@ -17,13 +17,15 @@
|
||||
static inline void rwnx_prof_set(struct rwnx_hw *rwnx_hw, int val)
|
||||
{
|
||||
struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
|
||||
RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM, NXMAC_SW_SET_PROFILING_ADDR);
|
||||
RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM,
|
||||
NXMAC_SW_SET_PROFILING_ADDR);
|
||||
}
|
||||
|
||||
static inline void rwnx_prof_clear(struct rwnx_hw *rwnx_hw, int val)
|
||||
{
|
||||
struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
|
||||
RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM, NXMAC_SW_CLEAR_PROFILING_ADDR);
|
||||
RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM,
|
||||
NXMAC_SW_CLEAR_PROFILING_ADDR);
|
||||
}
|
||||
|
||||
#if 0
|
||||
@@ -51,7 +53,8 @@ enum {
|
||||
SW_PROF_HOSTBUF_IDX = 12,
|
||||
/****** IPC IRQs related signals ******/
|
||||
/* E2A direction */
|
||||
SW_PROF_IRQ_E2A_RXDESC = 16, // to make sure we let 16 bits available for LMAC FW
|
||||
SW_PROF_IRQ_E2A_RXDESC =
|
||||
16, // to make sure we let 16 bits available for LMAC FW
|
||||
SW_PROF_IRQ_E2A_TXCFM,
|
||||
SW_PROF_IRQ_E2A_DBG,
|
||||
SW_PROF_IRQ_E2A_MSG,
|
||||
@@ -76,58 +79,70 @@ enum {
|
||||
|
||||
// [LT]For debug purpose only
|
||||
#if (0)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (21)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_BIT (22)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (23)
|
||||
#define SW_PROF_CHAN_CTXT_PUSH_BIT (24)
|
||||
#define SW_PROF_CHAN_CTXT_QUEUE_BIT (25)
|
||||
#define SW_PROF_CHAN_CTXT_TX_BIT (26)
|
||||
#define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (27)
|
||||
#define SW_PROF_CHAN_CTXT_PSWTCH_BIT (28)
|
||||
#define SW_PROF_CHAN_CTXT_SWTCH_BIT (29)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (21)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_BIT (22)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (23)
|
||||
#define SW_PROF_CHAN_CTXT_PUSH_BIT (24)
|
||||
#define SW_PROF_CHAN_CTXT_QUEUE_BIT (25)
|
||||
#define SW_PROF_CHAN_CTXT_TX_BIT (26)
|
||||
#define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (27)
|
||||
#define SW_PROF_CHAN_CTXT_PSWTCH_BIT (28)
|
||||
#define SW_PROF_CHAN_CTXT_SWTCH_BIT (29)
|
||||
|
||||
// TO DO: update this
|
||||
|
||||
#define REG_SW_SET_PROFILING_CHAN(env, bit) \
|
||||
#define REG_SW_SET_PROFILING_CHAN(env, bit) \
|
||||
rwnx_prof_set((struct rwnx_hw *)env, BIT(bit))
|
||||
|
||||
#define REG_SW_CLEAR_PROFILING_CHAN(env, bit) \
|
||||
#define REG_SW_CLEAR_PROFILING_CHAN(env, bit) \
|
||||
rwnx_prof_clear((struct rwnx_hw *)env, BIT(bit))
|
||||
|
||||
#else
|
||||
#define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_PUSH_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_QUEUE_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_TX_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_PSWTCH_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_SWTCH_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_PUSH_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_QUEUE_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_TX_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_PSWTCH_BIT (0)
|
||||
#define SW_PROF_CHAN_CTXT_SWTCH_BIT (0)
|
||||
|
||||
#define REG_SW_SET_PROFILING_CHAN(env, bit) do {} while (0)
|
||||
#define REG_SW_CLEAR_PROFILING_CHAN(env, bit) do {} while (0)
|
||||
#define REG_SW_SET_PROFILING_CHAN(env, bit) \
|
||||
do { \
|
||||
} while (0)
|
||||
#define REG_SW_CLEAR_PROFILING_CHAN(env, bit) \
|
||||
do { \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RWNX_SW_PROFILING
|
||||
/* Macros for SW PRofiling registers access */
|
||||
#define REG_SW_SET_PROFILING(env, bit) \
|
||||
#define REG_SW_SET_PROFILING(env, bit) \
|
||||
rwnx_prof_set((struct rwnx_hw *)env, BIT(bit))
|
||||
|
||||
#define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) \
|
||||
#define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) \
|
||||
rwnx_prof_set((struct rwnx_hw *)env, val << (SW_PROF_HOSTBUF_IDX))
|
||||
|
||||
#define REG_SW_CLEAR_PROFILING(env, bit) \
|
||||
#define REG_SW_CLEAR_PROFILING(env, bit) \
|
||||
rwnx_prof_clear((struct rwnx_hw *)env, BIT(bit))
|
||||
|
||||
#define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) \
|
||||
#define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) \
|
||||
rwnx_prof_clear((struct rwnx_hw *)env, 0x0F << (SW_PROF_HOSTBUF_IDX))
|
||||
|
||||
#else
|
||||
#define REG_SW_SET_PROFILING(env, value) do {} while (0)
|
||||
#define REG_SW_CLEAR_PROFILING(env, value) do {} while (0)
|
||||
#define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) do {} while (0)
|
||||
#define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) do {} while (0)
|
||||
#define REG_SW_SET_PROFILING(env, value) \
|
||||
do { \
|
||||
} while (0)
|
||||
#define REG_SW_CLEAR_PROFILING(env, value) \
|
||||
do { \
|
||||
} while (0)
|
||||
#define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) \
|
||||
do { \
|
||||
} while (0)
|
||||
#define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) \
|
||||
do { \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#endif /* _RWNX_PROF_H_ */
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
* tolerated deviation of radar time stamp in usecs on both sides
|
||||
* TODO: this might need to be HW-dependent
|
||||
*/
|
||||
#define PRI_TOLERANCE 16
|
||||
#define PRI_TOLERANCE 16
|
||||
|
||||
/**
|
||||
* struct radar_types - contains array of patterns defined for one DFS domain
|
||||
@@ -90,9 +90,8 @@ struct radar_detector_specs {
|
||||
enum radar_waveform_type type;
|
||||
};
|
||||
|
||||
|
||||
/* percentage on ppb threshold to trigger detection */
|
||||
#define MIN_PPB_THRESH 50
|
||||
#define MIN_PPB_THRESH 50
|
||||
#define PPB_THRESH(PPB) ((PPB * MIN_PPB_THRESH + 50) / 100)
|
||||
#define PRF2PRI(PRF) ((1000000 + PRF / 2) / PRF)
|
||||
|
||||
@@ -101,116 +100,116 @@ struct radar_detector_specs {
|
||||
#define WIDTH_LOWER(X) (X)
|
||||
#define WIDTH_UPPER(X) (X)
|
||||
|
||||
#define ETSI_PATTERN_SHORT(ID, WMIN, WMAX, PMIN, PMAX, PPB) \
|
||||
{ \
|
||||
ID, WIDTH_LOWER(WMIN), WIDTH_UPPER(WMAX), \
|
||||
(PRF2PRI(PMAX) - PRI_TOLERANCE), \
|
||||
(PRF2PRI(PMIN) + PRI_TOLERANCE), 1, PPB, \
|
||||
PPB_THRESH(PPB), PRI_TOLERANCE, RADAR_WAVEFORM_SHORT \
|
||||
}
|
||||
#define ETSI_PATTERN_SHORT(ID, WMIN, WMAX, PMIN, PMAX, PPB) \
|
||||
{ \
|
||||
ID, WIDTH_LOWER(WMIN), WIDTH_UPPER(WMAX), \
|
||||
(PRF2PRI(PMAX) - PRI_TOLERANCE), \
|
||||
(PRF2PRI(PMIN) + PRI_TOLERANCE), 1, PPB, \
|
||||
PPB_THRESH(PPB), PRI_TOLERANCE, RADAR_WAVEFORM_SHORT \
|
||||
}
|
||||
|
||||
#define ETSI_PATTERN_INTERLEAVED(ID, WMIN, WMAX, PMIN, PMAX, PRFMIN, PRFMAX, PPB) \
|
||||
{ \
|
||||
ID, WIDTH_LOWER(WMIN), WIDTH_UPPER(WMAX), \
|
||||
(PRF2PRI(PMAX) * PRFMIN- PRI_TOLERANCE), \
|
||||
(PRF2PRI(PMIN) * PRFMAX + PRI_TOLERANCE), \
|
||||
PRFMAX, PPB * PRFMAX, \
|
||||
PPB_THRESH(PPB), PRI_TOLERANCE, RADAR_WAVEFORM_INTERLEAVED \
|
||||
}
|
||||
#define ETSI_PATTERN_INTERLEAVED(ID, WMIN, WMAX, PMIN, PMAX, PRFMIN, PRFMAX, \
|
||||
PPB) \
|
||||
{ \
|
||||
ID, WIDTH_LOWER(WMIN), WIDTH_UPPER(WMAX), \
|
||||
(PRF2PRI(PMAX) * PRFMIN - PRI_TOLERANCE), \
|
||||
(PRF2PRI(PMIN) * PRFMAX + PRI_TOLERANCE), PRFMAX, \
|
||||
PPB *PRFMAX, PPB_THRESH(PPB), PRI_TOLERANCE, \
|
||||
RADAR_WAVEFORM_INTERLEAVED \
|
||||
}
|
||||
|
||||
/* radar types as defined by ETSI EN-301-893 v1.7.1 */
|
||||
static const struct radar_detector_specs etsi_radar_ref_types_v17_riu[] = {
|
||||
ETSI_PATTERN_SHORT(0, 0, 8, 700, 700, 18),
|
||||
ETSI_PATTERN_SHORT(1, 0, 10, 200, 1000, 10),
|
||||
ETSI_PATTERN_SHORT(2, 0, 22, 200, 1600, 15),
|
||||
ETSI_PATTERN_SHORT(3, 0, 22, 2300, 4000, 25),
|
||||
ETSI_PATTERN_SHORT(0, 0, 8, 700, 700, 18),
|
||||
ETSI_PATTERN_SHORT(1, 0, 10, 200, 1000, 10),
|
||||
ETSI_PATTERN_SHORT(2, 0, 22, 200, 1600, 15),
|
||||
ETSI_PATTERN_SHORT(3, 0, 22, 2300, 4000, 25),
|
||||
ETSI_PATTERN_SHORT(4, 20, 38, 2000, 4000, 20),
|
||||
ETSI_PATTERN_INTERLEAVED(5, 0, 8, 300, 400, 2, 3, 10),
|
||||
ETSI_PATTERN_INTERLEAVED(6, 0, 8, 400, 1200, 2, 3, 15),
|
||||
ETSI_PATTERN_INTERLEAVED(5, 0, 8, 300, 400, 2, 3, 10),
|
||||
ETSI_PATTERN_INTERLEAVED(6, 0, 8, 400, 1200, 2, 3, 15),
|
||||
};
|
||||
|
||||
static const struct radar_detector_specs etsi_radar_ref_types_v17_fcu[] = {
|
||||
ETSI_PATTERN_SHORT(0, 0, 8, 700, 700, 18),
|
||||
ETSI_PATTERN_SHORT(1, 0, 8, 200, 1000, 10),
|
||||
ETSI_PATTERN_SHORT(2, 0, 16, 200, 1600, 15),
|
||||
ETSI_PATTERN_SHORT(3, 0, 16, 2300, 4000, 25),
|
||||
ETSI_PATTERN_SHORT(0, 0, 8, 700, 700, 18),
|
||||
ETSI_PATTERN_SHORT(1, 0, 8, 200, 1000, 10),
|
||||
ETSI_PATTERN_SHORT(2, 0, 16, 200, 1600, 15),
|
||||
ETSI_PATTERN_SHORT(3, 0, 16, 2300, 4000, 25),
|
||||
ETSI_PATTERN_SHORT(4, 20, 34, 2000, 4000, 20),
|
||||
ETSI_PATTERN_INTERLEAVED(5, 0, 8, 300, 400, 2, 3, 10),
|
||||
ETSI_PATTERN_INTERLEAVED(6, 0, 8, 400, 1200, 2, 3, 15),
|
||||
ETSI_PATTERN_INTERLEAVED(5, 0, 8, 300, 400, 2, 3, 10),
|
||||
ETSI_PATTERN_INTERLEAVED(6, 0, 8, 400, 1200, 2, 3, 15),
|
||||
};
|
||||
|
||||
static const struct radar_types etsi_radar_types_v17 = {
|
||||
.region = NL80211_DFS_ETSI,
|
||||
.region = NL80211_DFS_ETSI,
|
||||
.num_radar_types = ARRAY_SIZE(etsi_radar_ref_types_v17_riu),
|
||||
.spec_riu = etsi_radar_ref_types_v17_riu,
|
||||
.spec_fcu = etsi_radar_ref_types_v17_fcu,
|
||||
.spec_riu = etsi_radar_ref_types_v17_riu,
|
||||
.spec_fcu = etsi_radar_ref_types_v17_fcu,
|
||||
};
|
||||
|
||||
#define FCC_PATTERN(ID, WMIN, WMAX, PMIN, PMAX, PRF, PPB, TYPE) \
|
||||
{ \
|
||||
ID, WIDTH_LOWER(WMIN), WIDTH_UPPER(WMAX), \
|
||||
PMIN - PRI_TOLERANCE, \
|
||||
PMAX * PRF + PRI_TOLERANCE, PRF, PPB * PRF, \
|
||||
PPB_THRESH(PPB), PRI_TOLERANCE, TYPE \
|
||||
}
|
||||
#define FCC_PATTERN(ID, WMIN, WMAX, PMIN, PMAX, PRF, PPB, TYPE) \
|
||||
{ \
|
||||
ID, WIDTH_LOWER(WMIN), WIDTH_UPPER(WMAX), \
|
||||
PMIN - PRI_TOLERANCE, PMAX *PRF + PRI_TOLERANCE, PRF, \
|
||||
PPB *PRF, PPB_THRESH(PPB), PRI_TOLERANCE, TYPE \
|
||||
}
|
||||
|
||||
static const struct radar_detector_specs fcc_radar_ref_types_riu[] = {
|
||||
FCC_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(1, 0, 8, 518, 3066, 1, 102, RADAR_WAVEFORM_WEATHER),
|
||||
FCC_PATTERN(2, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(3, 6, 20, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(4, 10, 28, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(5, 50, 110, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
FCC_PATTERN(6, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(1, 0, 8, 518, 3066, 1, 102, RADAR_WAVEFORM_WEATHER),
|
||||
FCC_PATTERN(2, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(3, 6, 20, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(4, 10, 28, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(5, 50, 110, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
FCC_PATTERN(6, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
};
|
||||
|
||||
static const struct radar_detector_specs fcc_radar_ref_types_fcu[] = {
|
||||
FCC_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(1, 0, 8, 518, 3066, 1, 102, RADAR_WAVEFORM_WEATHER),
|
||||
FCC_PATTERN(2, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(3, 6, 12, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(4, 10, 22, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(5, 50, 104, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
FCC_PATTERN(6, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(1, 0, 8, 518, 3066, 1, 102, RADAR_WAVEFORM_WEATHER),
|
||||
FCC_PATTERN(2, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(3, 6, 12, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(4, 10, 22, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
FCC_PATTERN(5, 50, 104, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
FCC_PATTERN(6, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
};
|
||||
|
||||
static const struct radar_types fcc_radar_types = {
|
||||
.region = NL80211_DFS_FCC,
|
||||
.region = NL80211_DFS_FCC,
|
||||
.num_radar_types = ARRAY_SIZE(fcc_radar_ref_types_riu),
|
||||
.spec_riu = fcc_radar_ref_types_riu,
|
||||
.spec_fcu = fcc_radar_ref_types_fcu,
|
||||
.spec_riu = fcc_radar_ref_types_riu,
|
||||
.spec_fcu = fcc_radar_ref_types_fcu,
|
||||
};
|
||||
|
||||
#define JP_PATTERN FCC_PATTERN
|
||||
static const struct radar_detector_specs jp_radar_ref_types_riu[] = {
|
||||
JP_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(1, 2, 8, 3846, 3846, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(2, 0, 8, 1388, 1388, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(3, 0, 8, 4000, 4000, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(4, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(5, 6, 20, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(6, 10, 28, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(7, 50, 110, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
JP_PATTERN(8, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(1, 2, 8, 3846, 3846, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(2, 0, 8, 1388, 1388, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(3, 0, 8, 4000, 4000, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(4, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(5, 6, 20, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(6, 10, 28, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(7, 50, 110, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
JP_PATTERN(8, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
};
|
||||
|
||||
static const struct radar_detector_specs jp_radar_ref_types_fcu[] = {
|
||||
JP_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(1, 2, 6, 3846, 3846, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(2, 0, 8, 1388, 1388, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(3, 2, 2, 4000, 4000, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(4, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(5, 6, 12, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(6, 10, 22, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(7, 50, 104, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
JP_PATTERN(8, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(0, 0, 8, 1428, 1428, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(1, 2, 6, 3846, 3846, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(2, 0, 8, 1388, 1388, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(3, 2, 2, 4000, 4000, 1, 18, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(4, 0, 8, 150, 230, 1, 23, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(5, 6, 12, 200, 500, 1, 16, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(6, 10, 22, 200, 500, 1, 12, RADAR_WAVEFORM_SHORT),
|
||||
JP_PATTERN(7, 50, 104, 1000, 2000, 1, 8, RADAR_WAVEFORM_LONG),
|
||||
JP_PATTERN(8, 0, 8, 333, 333, 1, 9, RADAR_WAVEFORM_SHORT),
|
||||
};
|
||||
|
||||
static const struct radar_types jp_radar_types = {
|
||||
.region = NL80211_DFS_JP,
|
||||
.region = NL80211_DFS_JP,
|
||||
.num_radar_types = ARRAY_SIZE(jp_radar_ref_types_riu),
|
||||
.spec_riu = jp_radar_ref_types_riu,
|
||||
.spec_fcu = jp_radar_ref_types_fcu,
|
||||
.spec_riu = jp_radar_ref_types_riu,
|
||||
.spec_fcu = jp_radar_ref_types_fcu,
|
||||
};
|
||||
|
||||
static const struct radar_types *dfs_domains[] = {
|
||||
@@ -219,7 +218,6 @@ static const struct radar_types *dfs_domains[] = {
|
||||
&jp_radar_types,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct pri_sequence - sequence of pulses matching one PRI
|
||||
* @head: list_head
|
||||
@@ -245,7 +243,6 @@ struct pri_sequence {
|
||||
u8 ppb_thresh;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct pulse_elem - elements in pulse queue
|
||||
* @ts: time stamp in usecs
|
||||
@@ -288,11 +285,11 @@ struct pri_detector {
|
||||
*/
|
||||
struct pri_detector_ops {
|
||||
void (*init)(struct pri_detector *pde);
|
||||
struct pri_sequence * (*add_pulse)(struct pri_detector *pde, u16 len, u64 ts, u16 pri);
|
||||
struct pri_sequence *(*add_pulse)(struct pri_detector *pde, u16 len,
|
||||
u64 ts, u16 pri);
|
||||
int reset_on_pri_overflow;
|
||||
};
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* PRI (pulse repetition interval) sequence detection
|
||||
*****************************************************************************/
|
||||
@@ -326,11 +323,11 @@ static void pool_deregister_ref(void)
|
||||
struct pri_sequence *ps, *ps0;
|
||||
struct pulse_elem *p, *p0;
|
||||
|
||||
list_for_each_entry_safe(p, p0, &pulse_pool, head) {
|
||||
list_for_each_entry_safe (p, p0, &pulse_pool, head) {
|
||||
list_del(&p->head);
|
||||
kfree(p);
|
||||
}
|
||||
list_for_each_entry_safe(ps, ps0, &pseq_pool, head) {
|
||||
list_for_each_entry_safe (ps, ps0, &pseq_pool, head) {
|
||||
list_del(&ps->head);
|
||||
kfree(ps);
|
||||
}
|
||||
@@ -407,8 +404,7 @@ static bool pulse_queue_dequeue(struct pri_detector *pde)
|
||||
*
|
||||
* dequeue pulse that are too old.
|
||||
*/
|
||||
static
|
||||
void pulse_queue_check_window(struct pri_detector *pde)
|
||||
static void pulse_queue_check_window(struct pri_detector *pde)
|
||||
{
|
||||
u64 min_valid_ts;
|
||||
struct pulse_elem *p;
|
||||
@@ -435,14 +431,13 @@ void pulse_queue_check_window(struct pri_detector *pde)
|
||||
* Add one pulse to the list. If the maximum number of pulses
|
||||
* if reached, remove oldest one.
|
||||
*/
|
||||
static
|
||||
bool pulse_queue_enqueue(struct pri_detector *pde, u64 ts)
|
||||
static bool pulse_queue_enqueue(struct pri_detector *pde, u64 ts)
|
||||
{
|
||||
struct pulse_elem *p = pool_get_pulse_elem();
|
||||
if (p == NULL) {
|
||||
p = kmalloc(sizeof(*p), GFP_ATOMIC);
|
||||
if (p == NULL) {
|
||||
return false;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
INIT_LIST_HEAD(&p->head);
|
||||
@@ -457,7 +452,6 @@ bool pulse_queue_enqueue(struct pri_detector *pde, u64 ts)
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* Short waveform
|
||||
**************************************************************************/
|
||||
@@ -465,8 +459,7 @@ bool pulse_queue_enqueue(struct pri_detector *pde, u64 ts)
|
||||
* pde_get_multiple() - get number of multiples considering a given tolerance
|
||||
* @return factor if abs(val - factor*fraction) <= tolerance, 0 otherwise
|
||||
*/
|
||||
static
|
||||
u32 pde_get_multiple(u32 val, u32 fraction, u32 tolerance)
|
||||
static u32 pde_get_multiple(u32 val, u32 fraction, u32 tolerance)
|
||||
{
|
||||
u32 remainder;
|
||||
u32 factor;
|
||||
@@ -509,14 +502,13 @@ u32 pde_get_multiple(u32 val, u32 fraction, u32 tolerance)
|
||||
* pri = (ts - pulse_queued.ts) which contains more than @min_count pulses.
|
||||
*
|
||||
*/
|
||||
static
|
||||
bool pde_short_create_sequences(struct pri_detector *pde,
|
||||
u64 ts, u32 min_count)
|
||||
static bool pde_short_create_sequences(struct pri_detector *pde, u64 ts,
|
||||
u32 min_count)
|
||||
{
|
||||
struct pulse_elem *p;
|
||||
u16 pulse_idx = 0;
|
||||
|
||||
list_for_each_entry(p, &pde->pulses, head) {
|
||||
list_for_each_entry (p, &pde->pulses, head) {
|
||||
struct pri_sequence ps, *new_ps;
|
||||
struct pulse_elem *p2;
|
||||
u32 tmp_false_count;
|
||||
@@ -538,8 +530,8 @@ bool pde_short_create_sequences(struct pri_detector *pde,
|
||||
ps.first_ts = p->ts;
|
||||
ps.last_ts = ts;
|
||||
ps.pri = ts - p->ts;
|
||||
ps.dur = ps.pri * (pde->rs->ppb - 1)
|
||||
+ 2 * pde->rs->max_pri_tolerance;
|
||||
ps.dur = ps.pri * (pde->rs->ppb - 1) +
|
||||
2 * pde->rs->max_pri_tolerance;
|
||||
|
||||
p2 = p;
|
||||
tmp_false_count = 0;
|
||||
@@ -548,14 +540,14 @@ bool pde_short_create_sequences(struct pri_detector *pde,
|
||||
else
|
||||
min_valid_ts = ts - ps.dur;
|
||||
/* check which past pulses are candidates for new sequence */
|
||||
list_for_each_entry_continue(p2, &pde->pulses, head) {
|
||||
list_for_each_entry_continue (p2, &pde->pulses, head) {
|
||||
u32 factor;
|
||||
if (p2->ts < min_valid_ts)
|
||||
/* stop on crossing window border */
|
||||
break;
|
||||
/* check if pulse match (multi)PRI */
|
||||
factor = pde_get_multiple(ps.last_ts - p2->ts, ps.pri,
|
||||
pde->rs->max_pri_tolerance);
|
||||
pde->rs->max_pri_tolerance);
|
||||
if (factor > 0) {
|
||||
ps.count++;
|
||||
ps.first_ts = p2->ts;
|
||||
@@ -608,12 +600,11 @@ bool pde_short_create_sequences(struct pri_detector *pde,
|
||||
*
|
||||
* @return the length of the longest sequence in which the pulse has been added
|
||||
*/
|
||||
static
|
||||
u32 pde_short_add_to_existing_seqs(struct pri_detector *pde, u64 ts)
|
||||
static u32 pde_short_add_to_existing_seqs(struct pri_detector *pde, u64 ts)
|
||||
{
|
||||
u32 max_count = 0;
|
||||
struct pri_sequence *ps, *ps2;
|
||||
list_for_each_entry_safe(ps, ps2, &pde->sequences, head) {
|
||||
list_for_each_entry_safe (ps, ps2, &pde->sequences, head) {
|
||||
u32 delta_ts;
|
||||
u32 factor;
|
||||
|
||||
@@ -626,7 +617,7 @@ u32 pde_short_add_to_existing_seqs(struct pri_detector *pde, u64 ts)
|
||||
|
||||
delta_ts = ts - ps->last_ts;
|
||||
factor = pde_get_multiple(delta_ts, ps->pri,
|
||||
pde->rs->max_pri_tolerance);
|
||||
pde->rs->max_pri_tolerance);
|
||||
|
||||
if (factor > 0) {
|
||||
ps->last_ts = ts;
|
||||
@@ -641,7 +632,6 @@ u32 pde_short_add_to_existing_seqs(struct pri_detector *pde, u64 ts)
|
||||
return max_count;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* pde_short_check_detection - check_detection function for
|
||||
* SHORT/WEATHER/INTERLEAVED radar waveform
|
||||
@@ -653,22 +643,21 @@ u32 pde_short_add_to_existing_seqs(struct pri_detector *pde, u64 ts)
|
||||
*
|
||||
* @return The first complete sequence, and NULL if no sequence is complete.
|
||||
*/
|
||||
static
|
||||
struct pri_sequence *pde_short_check_detection(struct pri_detector *pde)
|
||||
static struct pri_sequence *pde_short_check_detection(struct pri_detector *pde)
|
||||
{
|
||||
struct pri_sequence *ps;
|
||||
|
||||
if (list_empty(&pde->sequences))
|
||||
return NULL;
|
||||
|
||||
list_for_each_entry(ps, &pde->sequences, head) {
|
||||
list_for_each_entry (ps, &pde->sequences, head) {
|
||||
/*
|
||||
* we assume to have enough matching confidence if we
|
||||
* 1) have enough pulses
|
||||
* 2) have more matching than false pulses
|
||||
*/
|
||||
if ((ps->count >= ps->ppb_thresh) &&
|
||||
(ps->count * pde->rs->num_pri > ps->count_falses)) {
|
||||
(ps->count * pde->rs->num_pri > ps->count_falses)) {
|
||||
return ps;
|
||||
}
|
||||
}
|
||||
@@ -683,8 +672,7 @@ struct pri_sequence *pde_short_check_detection(struct pri_detector *pde)
|
||||
* Initialize pri_detector window size to the maximun size of one burst
|
||||
* for the radar specification associated.
|
||||
*/
|
||||
static
|
||||
void pde_short_init(struct pri_detector *pde)
|
||||
static void pde_short_init(struct pri_detector *pde)
|
||||
{
|
||||
pde->window_size = pde->rs->pri_max * pde->rs->ppb * pde->rs->num_pri;
|
||||
pde->max_count = pde->rs->ppb * 2;
|
||||
@@ -707,9 +695,8 @@ static void pri_detector_reset(struct pri_detector *pde, u64 ts);
|
||||
* - Check if this pulse complete a sequence
|
||||
* - If not save this pulse in the list
|
||||
*/
|
||||
static
|
||||
struct pri_sequence *pde_short_add_pulse(struct pri_detector *pde,
|
||||
u16 len, u64 ts, u16 pri)
|
||||
static struct pri_sequence *pde_short_add_pulse(struct pri_detector *pde,
|
||||
u16 len, u64 ts, u16 pri)
|
||||
{
|
||||
u32 max_updated_seq;
|
||||
struct pri_sequence *ps;
|
||||
@@ -741,8 +728,6 @@ struct pri_sequence *pde_short_add_pulse(struct pri_detector *pde,
|
||||
return ps;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* pri detector ops to detect short radar waveform
|
||||
* A Short waveform is defined by :
|
||||
@@ -757,7 +742,6 @@ static struct pri_detector_ops pri_detector_short = {
|
||||
.reset_on_pri_overflow = 1,
|
||||
};
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* Long waveform
|
||||
**************************************************************************/
|
||||
@@ -772,14 +756,12 @@ static struct pri_detector_ops pri_detector_short = {
|
||||
* Initialize pri_detector window size to the long waveform radar
|
||||
* waveform (ie. 12s) and max_count
|
||||
*/
|
||||
static
|
||||
void pde_long_init(struct pri_detector *pde)
|
||||
static void pde_long_init(struct pri_detector *pde)
|
||||
{
|
||||
pde->window_size = LONG_RADAR_DURATION;
|
||||
pde->max_count = LONG_RADAR_MAX_BURST; /* only count burst not pulses */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* pde_long_add_pulse - Add pulse to a pri_detector for
|
||||
* LONG radar waveform
|
||||
@@ -797,9 +779,8 @@ void pde_long_init(struct pri_detector *pde)
|
||||
* We only queue one pulse per burst and valid the radar when enough burst
|
||||
* has been detected.
|
||||
*/
|
||||
static
|
||||
struct pri_sequence *pde_long_add_pulse(struct pri_detector *pde,
|
||||
u16 len, u64 ts, u16 pri)
|
||||
static struct pri_sequence *pde_long_add_pulse(struct pri_detector *pde,
|
||||
u16 len, u64 ts, u16 pri)
|
||||
{
|
||||
struct pri_sequence *ps;
|
||||
const struct radar_detector_specs *rs = pde->rs;
|
||||
@@ -832,13 +813,14 @@ struct pri_sequence *pde_long_add_pulse(struct pri_detector *pde,
|
||||
|
||||
if (delta_ts < rs->pri_max) {
|
||||
/* ignore pulse too close from previous one */
|
||||
} else if ((delta_ts >= rs->pri_min) &&
|
||||
(delta_ts <= rs->pri_max)) {
|
||||
} else if ((delta_ts >= rs->pri_min) &&
|
||||
(delta_ts <= rs->pri_max)) {
|
||||
/* this is a new pulse in the current burst, ignore it
|
||||
(i.e don't queue it) */
|
||||
ps->count_falses++;
|
||||
} else if ((ps->count > 2) &&
|
||||
(ps->dur + delta_ts) < LONG_RADAR_BURST_MIN_DURATION) {
|
||||
(ps->dur + delta_ts) <
|
||||
LONG_RADAR_BURST_MIN_DURATION) {
|
||||
/* not enough time between burst, ignore pulse */
|
||||
} else {
|
||||
/* a new burst */
|
||||
@@ -851,10 +833,13 @@ struct pri_sequence *pde_long_add_pulse(struct pri_detector *pde,
|
||||
u64 min_valid_ts;
|
||||
|
||||
min_valid_ts = ts - pde->window_size;
|
||||
while ((p = pulse_queue_get_tail(pde)) != NULL) {
|
||||
while ((p = pulse_queue_get_tail(pde)) !=
|
||||
NULL) {
|
||||
if (p->ts >= min_valid_ts) {
|
||||
ps->first_ts = p->ts;
|
||||
ps->deadline_ts = p->ts + pde->window_size;
|
||||
ps->deadline_ts =
|
||||
p->ts +
|
||||
pde->window_size;
|
||||
break;
|
||||
}
|
||||
pulse_queue_dequeue(pde);
|
||||
@@ -865,7 +850,7 @@ struct pri_sequence *pde_long_add_pulse(struct pri_detector *pde,
|
||||
/* valid radar if enough burst detected and delta with first burst
|
||||
is at least duration/2 */
|
||||
if (ps->count > pde->rs->ppb_thresh &&
|
||||
(ts - ps->first_ts) > (pde->window_size / 2)) {
|
||||
(ts - ps->first_ts) > (pde->window_size / 2)) {
|
||||
return ps;
|
||||
} else {
|
||||
pulse_queue_enqueue(pde, ts);
|
||||
@@ -886,7 +871,6 @@ static struct pri_detector_ops pri_detector_long = {
|
||||
.reset_on_pri_overflow = 0,
|
||||
};
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* PRI detector init/reset/exit/get
|
||||
**************************************************************************/
|
||||
@@ -898,7 +882,7 @@ static struct pri_detector_ops pri_detector_long = {
|
||||
* @freq: Frequency of the pri detector
|
||||
*/
|
||||
struct pri_detector *pri_detector_init(struct dfs_pattern_detector *dpd,
|
||||
u16 radar_type, u16 freq)
|
||||
u16 radar_type, u16 freq)
|
||||
{
|
||||
struct pri_detector *pde;
|
||||
|
||||
@@ -937,16 +921,15 @@ struct pri_detector *pri_detector_init(struct dfs_pattern_detector *dpd,
|
||||
*
|
||||
* free pulse queue and sequences list and give objects back to pools
|
||||
*/
|
||||
static
|
||||
void pri_detector_reset(struct pri_detector *pde, u64 ts)
|
||||
static void pri_detector_reset(struct pri_detector *pde, u64 ts)
|
||||
{
|
||||
struct pri_sequence *ps, *ps0;
|
||||
struct pulse_elem *p, *p0;
|
||||
list_for_each_entry_safe(ps, ps0, &pde->sequences, head) {
|
||||
list_for_each_entry_safe (ps, ps0, &pde->sequences, head) {
|
||||
list_del_init(&ps->head);
|
||||
pool_put_pseq_elem(ps);
|
||||
}
|
||||
list_for_each_entry_safe(p, p0, &pde->pulses, head) {
|
||||
list_for_each_entry_safe (p, p0, &pde->pulses, head) {
|
||||
list_del_init(&p->head);
|
||||
pool_put_pulse_elem(p);
|
||||
}
|
||||
@@ -959,8 +942,7 @@ void pri_detector_reset(struct pri_detector *pde, u64 ts)
|
||||
*
|
||||
* @pde: pointer on pri_detector
|
||||
*/
|
||||
static
|
||||
void pri_detector_exit(struct pri_detector *pde)
|
||||
static void pri_detector_exit(struct pri_detector *pde)
|
||||
{
|
||||
pri_detector_reset(pde, 0);
|
||||
pool_deregister_ref();
|
||||
@@ -982,11 +964,11 @@ void pri_detector_exit(struct pri_detector *pde)
|
||||
*
|
||||
* Maybe will need to adapt frequency merge for pattern with chirp.
|
||||
*/
|
||||
static struct pri_detector *
|
||||
pri_detector_get(struct dfs_pattern_detector *dpd, u16 freq, u16 radar_type)
|
||||
static struct pri_detector *pri_detector_get(struct dfs_pattern_detector *dpd,
|
||||
u16 freq, u16 radar_type)
|
||||
{
|
||||
struct pri_detector *pde, *cur = NULL;
|
||||
list_for_each_entry(pde, &dpd->detectors[radar_type], head) {
|
||||
list_for_each_entry (pde, &dpd->detectors[radar_type], head) {
|
||||
if (pde->freq == freq) {
|
||||
if (pde->count)
|
||||
return pde;
|
||||
@@ -1005,7 +987,6 @@ pri_detector_get(struct dfs_pattern_detector *dpd, u16 freq, u16 radar_type)
|
||||
return pri_detector_init(dpd, radar_type, freq);
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* DFS Pattern Detector
|
||||
*****************************************************************************/
|
||||
@@ -1021,7 +1002,7 @@ static void dfs_pattern_detector_reset(struct dfs_pattern_detector *dpd)
|
||||
|
||||
for (i = 0; i < dpd->num_radar_types; i++) {
|
||||
if (!list_empty(&dpd->detectors[i]))
|
||||
list_for_each_entry(pde, &dpd->detectors[i], head)
|
||||
list_for_each_entry (pde, &dpd->detectors[i], head)
|
||||
pri_detector_reset(pde, dpd->last_pulse_ts);
|
||||
}
|
||||
|
||||
@@ -1041,7 +1022,8 @@ static void dfs_pattern_detector_exit(struct dfs_pattern_detector *dpd)
|
||||
|
||||
for (i = 0; i < dpd->num_radar_types; i++) {
|
||||
if (!list_empty(&dpd->detectors[i]))
|
||||
list_for_each_entry_safe(pde, pde0, &dpd->detectors[i], head)
|
||||
list_for_each_entry_safe (pde, pde0, &dpd->detectors[i],
|
||||
head)
|
||||
pri_detector_exit(pde);
|
||||
}
|
||||
|
||||
@@ -1060,9 +1042,10 @@ static void dfs_pattern_detector_pri_overflow(struct dfs_pattern_detector *dpd)
|
||||
|
||||
for (i = 0; i < dpd->num_radar_types; i++) {
|
||||
if (!list_empty(&dpd->detectors[i]))
|
||||
list_for_each_entry(pde, &dpd->detectors[i], head)
|
||||
list_for_each_entry (pde, &dpd->detectors[i], head)
|
||||
if (pde->ops->reset_on_pri_overflow)
|
||||
pri_detector_reset(pde, dpd->last_pulse_ts);
|
||||
pri_detector_reset(pde,
|
||||
dpd->last_pulse_ts);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1083,8 +1066,8 @@ static void dfs_pattern_detector_pri_overflow(struct dfs_pattern_detector *dpd)
|
||||
* @return True is the pulse complete a radar pattern, false otherwise
|
||||
*/
|
||||
static bool dfs_pattern_detector_add_pulse(struct dfs_pattern_detector *dpd,
|
||||
enum rwnx_radar_chain chain,
|
||||
u16 freq, u16 pri, u16 len, u32 now)
|
||||
enum rwnx_radar_chain chain,
|
||||
u16 freq, u16 pri, u16 len, u32 now)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
@@ -1116,8 +1099,7 @@ static bool dfs_pattern_detector_add_pulse(struct dfs_pattern_detector *dpd,
|
||||
const struct radar_detector_specs *rs = &dpd->radar_spec[i];
|
||||
|
||||
/* no need to look up for pde if len is not within range */
|
||||
if ((rs->width_min > len) ||
|
||||
(rs->width_max < len)) {
|
||||
if ((rs->width_min > len) || (rs->width_max < len)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
@@ -1126,7 +1108,8 @@ static bool dfs_pattern_detector_add_pulse(struct dfs_pattern_detector *dpd,
|
||||
|
||||
if (ps != NULL) {
|
||||
#ifdef CREATE_TRACE_POINTS
|
||||
trace_radar_detected(chain, dpd->region, pde->freq, i, ps->pri);
|
||||
trace_radar_detected(chain, dpd->region, pde->freq, i,
|
||||
ps->pri);
|
||||
#endif
|
||||
// reset everything instead of just the channel detector
|
||||
dfs_pattern_detector_reset(dpd);
|
||||
@@ -1176,9 +1159,9 @@ static u16 get_dfs_max_radar_types(void)
|
||||
*
|
||||
* set DFS domain, resets detector lines upon domain changes
|
||||
*/
|
||||
static
|
||||
bool dfs_pattern_detector_set_domain(struct dfs_pattern_detector *dpd,
|
||||
enum nl80211_dfs_regions region, u8 chain)
|
||||
static bool dfs_pattern_detector_set_domain(struct dfs_pattern_detector *dpd,
|
||||
enum nl80211_dfs_regions region,
|
||||
u8 chain)
|
||||
{
|
||||
const struct radar_types *rt;
|
||||
struct pri_detector *pde, *pde0;
|
||||
@@ -1196,7 +1179,8 @@ bool dfs_pattern_detector_set_domain(struct dfs_pattern_detector *dpd,
|
||||
/* delete all pri detectors for previous DFS domain */
|
||||
for (i = 0; i < dpd->num_radar_types; i++) {
|
||||
if (!list_empty(&dpd->detectors[i]))
|
||||
list_for_each_entry_safe(pde, pde0, &dpd->detectors[i], head)
|
||||
list_for_each_entry_safe (pde, pde0, &dpd->detectors[i],
|
||||
head)
|
||||
pri_detector_exit(pde);
|
||||
}
|
||||
|
||||
@@ -1207,6 +1191,8 @@ bool dfs_pattern_detector_set_domain(struct dfs_pattern_detector *dpd,
|
||||
dpd->num_radar_types = rt->num_radar_types;
|
||||
|
||||
dpd->region = region;
|
||||
|
||||
AICWFDBG(LOGINFO, "set_region %d \n", region);
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -1224,7 +1210,7 @@ dfs_pattern_detector_init(enum nl80211_dfs_regions region, u8 chain)
|
||||
u16 i, max_radar_type = get_dfs_max_radar_types();
|
||||
|
||||
dpd = kmalloc(sizeof(*dpd) + max_radar_type * sizeof(dpd->detectors[0]),
|
||||
GFP_KERNEL);
|
||||
GFP_KERNEL);
|
||||
if (dpd == NULL)
|
||||
return NULL;
|
||||
|
||||
@@ -1243,7 +1229,6 @@ dfs_pattern_detector_init(enum nl80211_dfs_regions region, u8 chain)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* driver interface
|
||||
*****************************************************************************/
|
||||
@@ -1257,7 +1242,8 @@ static u16 rwnx_radar_get_center_freq(struct rwnx_hw *rwnx_hw, u8 chain)
|
||||
if (!rwnx_chanctx_valid(rwnx_hw, rwnx_hw->cur_chanctx)) {
|
||||
WARN(1, "Radar pulse without channel information");
|
||||
} else
|
||||
return rwnx_hw->chanctx_table[rwnx_hw->cur_chanctx].chan_def.center_freq1;
|
||||
return rwnx_hw->chanctx_table[rwnx_hw->cur_chanctx]
|
||||
.chan_def.center_freq1;
|
||||
#endif /* CONFIG_RWNX_FULLMAC */
|
||||
}
|
||||
|
||||
@@ -1269,6 +1255,8 @@ static void rwnx_radar_detected(struct rwnx_hw *rwnx_hw)
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
struct cfg80211_chan_def chan_def;
|
||||
|
||||
RWNX_DBG(RWNX_FN_ENTRY_STR);
|
||||
|
||||
if (!rwnx_chanctx_valid(rwnx_hw, rwnx_hw->cur_chanctx)) {
|
||||
WARN(1, "Radar detected without channel information");
|
||||
return;
|
||||
@@ -1289,13 +1277,14 @@ static void rwnx_radar_detected(struct rwnx_hw *rwnx_hw)
|
||||
|
||||
static void rwnx_radar_process_pulse(struct work_struct *ws)
|
||||
{
|
||||
struct rwnx_radar *radar = container_of(ws, struct rwnx_radar,
|
||||
detection_work);
|
||||
struct rwnx_radar *radar =
|
||||
container_of(ws, struct rwnx_radar, detection_work);
|
||||
struct rwnx_hw *rwnx_hw = container_of(radar, struct rwnx_hw, radar);
|
||||
int chain;
|
||||
u32 pulses[RWNX_RADAR_LAST][RWNX_RADAR_PULSE_MAX];
|
||||
u16 pulses_count[RWNX_RADAR_LAST];
|
||||
u32 now = jiffies; /* would be better to store jiffies value in IT handler */
|
||||
u32 now =
|
||||
jiffies; /* would be better to store jiffies value in IT handler */
|
||||
|
||||
/* recopy pulses locally to avoid too long spin_lock */
|
||||
spin_lock_bh(&radar->lock);
|
||||
@@ -1314,21 +1303,20 @@ static void rwnx_radar_process_pulse(struct work_struct *ws)
|
||||
if ((start + count) > RWNX_RADAR_PULSE_MAX) {
|
||||
u16 count1 = (RWNX_RADAR_PULSE_MAX - start);
|
||||
memcpy(&(pulses[chain][0]),
|
||||
&(radar->pulses[chain].buffer[start]),
|
||||
count1 * sizeof(struct radar_pulse));
|
||||
&(radar->pulses[chain].buffer[start]),
|
||||
count1 * sizeof(struct radar_pulse));
|
||||
memcpy(&(pulses[chain][count1]),
|
||||
&(radar->pulses[chain].buffer[0]),
|
||||
(count - count1) * sizeof(struct radar_pulse));
|
||||
&(radar->pulses[chain].buffer[0]),
|
||||
(count - count1) * sizeof(struct radar_pulse));
|
||||
} else {
|
||||
memcpy(&(pulses[chain][0]),
|
||||
&(radar->pulses[chain].buffer[start]),
|
||||
count * sizeof(struct radar_pulse));
|
||||
&(radar->pulses[chain].buffer[start]),
|
||||
count * sizeof(struct radar_pulse));
|
||||
}
|
||||
radar->pulses[chain].count = 0;
|
||||
}
|
||||
spin_unlock_bh(&radar->lock);
|
||||
|
||||
|
||||
/* now process pulses */
|
||||
for (chain = RWNX_RADAR_RIU; chain < RWNX_RADAR_LAST; chain++) {
|
||||
int i;
|
||||
@@ -1339,26 +1327,30 @@ static void rwnx_radar_process_pulse(struct work_struct *ws)
|
||||
|
||||
freq = rwnx_radar_get_center_freq(rwnx_hw, chain);
|
||||
|
||||
for (i = 0; i < pulses_count[chain] ; i++) {
|
||||
struct radar_pulse *p = (struct radar_pulse *)&pulses[chain][i];
|
||||
for (i = 0; i < pulses_count[chain]; i++) {
|
||||
struct radar_pulse *p =
|
||||
(struct radar_pulse *)&pulses[chain][i];
|
||||
#ifdef CREATE_TRACE_POINTS
|
||||
trace_radar_pulse(chain, p);
|
||||
#endif
|
||||
if (dfs_pattern_detector_add_pulse(radar->dpd[chain], chain,
|
||||
(s16)freq + (2 * p->freq),
|
||||
p->rep, (p->len * 2), now)) {
|
||||
if (dfs_pattern_detector_add_pulse(
|
||||
radar->dpd[chain], chain,
|
||||
(s16)freq + (2 * p->freq), p->rep,
|
||||
(p->len * 2), now)) {
|
||||
u16 idx = radar->detected[chain].index;
|
||||
|
||||
if (chain == RWNX_RADAR_RIU) {
|
||||
/* operating chain, inform upper layer to change channel */
|
||||
if (radar->dpd[chain]->enabled == RWNX_RADAR_DETECT_REPORT) {
|
||||
if (radar->dpd[chain]->enabled ==
|
||||
RWNX_RADAR_DETECT_REPORT) {
|
||||
rwnx_radar_detected(rwnx_hw);
|
||||
/* no need to report new radar until upper layer set a
|
||||
new channel. This prevent warning if a new radar is
|
||||
detected while mac80211 is changing channel */
|
||||
rwnx_radar_detection_enable(radar,
|
||||
RWNX_RADAR_DETECT_DISABLE,
|
||||
chain);
|
||||
rwnx_radar_detection_enable(
|
||||
radar,
|
||||
RWNX_RADAR_DETECT_DISABLE,
|
||||
chain);
|
||||
/* purge any event received since the beginning of the
|
||||
function (we are sure not to interfer with tasklet
|
||||
as we disable detection just before) */
|
||||
@@ -1369,14 +1361,16 @@ static void rwnx_radar_process_pulse(struct work_struct *ws)
|
||||
debugfs for now */
|
||||
}
|
||||
|
||||
radar->detected[chain].freq[idx] = (s16)freq + (2 * p->freq);
|
||||
radar->detected[chain].time[idx] = ktime_get_real_seconds();
|
||||
radar->detected[chain].index = ((idx + 1) %
|
||||
NX_NB_RADAR_DETECTED);
|
||||
radar->detected[chain].freq[idx] =
|
||||
(s16)freq + (2 * p->freq);
|
||||
radar->detected[chain].time[idx] =
|
||||
ktime_get_real_seconds();
|
||||
radar->detected[chain].index =
|
||||
((idx + 1) % NX_NB_RADAR_DETECTED);
|
||||
radar->detected[chain].count++;
|
||||
/* no need to process next pulses for this chain */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1385,7 +1379,8 @@ static void rwnx_radar_process_pulse(struct work_struct *ws)
|
||||
static void rwnx_radar_cac_work(struct work_struct *ws)
|
||||
{
|
||||
struct delayed_work *dw = container_of(ws, struct delayed_work, work);
|
||||
struct rwnx_radar *radar = container_of(dw, struct rwnx_radar, cac_work);
|
||||
struct rwnx_radar *radar =
|
||||
container_of(dw, struct rwnx_radar, cac_work);
|
||||
struct rwnx_hw *rwnx_hw = container_of(radar, struct rwnx_hw, radar);
|
||||
struct rwnx_chanctx *ctxt;
|
||||
|
||||
@@ -1396,10 +1391,10 @@ static void rwnx_radar_cac_work(struct work_struct *ws)
|
||||
|
||||
ctxt = &rwnx_hw->chanctx_table[radar->cac_vif->ch_index];
|
||||
cfg80211_cac_event(radar->cac_vif->ndev,
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
|
||||
&ctxt->chan_def,
|
||||
#endif
|
||||
NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
|
||||
&ctxt->chan_def,
|
||||
#endif
|
||||
NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
|
||||
rwnx_send_apm_stop_cac_req(rwnx_hw, radar->cac_vif);
|
||||
rwnx_chanctx_unlink(radar->cac_vif);
|
||||
|
||||
@@ -1411,13 +1406,13 @@ bool rwnx_radar_detection_init(struct rwnx_radar *radar)
|
||||
{
|
||||
spin_lock_init(&radar->lock);
|
||||
|
||||
radar->dpd[RWNX_RADAR_RIU] = dfs_pattern_detector_init(NL80211_DFS_UNSET,
|
||||
RWNX_RADAR_RIU);
|
||||
radar->dpd[RWNX_RADAR_RIU] =
|
||||
dfs_pattern_detector_init(NL80211_DFS_UNSET, RWNX_RADAR_RIU);
|
||||
if (radar->dpd[RWNX_RADAR_RIU] == NULL)
|
||||
return false;
|
||||
|
||||
radar->dpd[RWNX_RADAR_FCU] = dfs_pattern_detector_init(NL80211_DFS_UNSET,
|
||||
RWNX_RADAR_FCU);
|
||||
radar->dpd[RWNX_RADAR_FCU] =
|
||||
dfs_pattern_detector_init(NL80211_DFS_UNSET, RWNX_RADAR_FCU);
|
||||
if (radar->dpd[RWNX_RADAR_FCU] == NULL) {
|
||||
rwnx_radar_detection_deinit(radar);
|
||||
return false;
|
||||
@@ -1444,7 +1439,7 @@ void rwnx_radar_detection_deinit(struct rwnx_radar *radar)
|
||||
}
|
||||
|
||||
bool rwnx_radar_set_domain(struct rwnx_radar *radar,
|
||||
enum nl80211_dfs_regions region)
|
||||
enum nl80211_dfs_regions region)
|
||||
{
|
||||
if (radar->dpd[0] == NULL)
|
||||
return false;
|
||||
@@ -1452,16 +1447,17 @@ bool rwnx_radar_set_domain(struct rwnx_radar *radar,
|
||||
trace_radar_set_region(region);
|
||||
#endif
|
||||
return (dfs_pattern_detector_set_domain(radar->dpd[RWNX_RADAR_RIU],
|
||||
region, RWNX_RADAR_RIU) &&
|
||||
dfs_pattern_detector_set_domain(radar->dpd[RWNX_RADAR_FCU],
|
||||
region, RWNX_RADAR_FCU));
|
||||
region, RWNX_RADAR_RIU) &&
|
||||
dfs_pattern_detector_set_domain(radar->dpd[RWNX_RADAR_FCU],
|
||||
region, RWNX_RADAR_FCU));
|
||||
}
|
||||
|
||||
void rwnx_radar_detection_enable(struct rwnx_radar *radar, u8 enable, u8 chain)
|
||||
{
|
||||
if (chain < RWNX_RADAR_LAST) {
|
||||
#ifdef CREATE_TRACE_POINTS
|
||||
trace_radar_enable_detection(radar->dpd[chain]->region, enable, chain);
|
||||
trace_radar_enable_detection(radar->dpd[chain]->region, enable,
|
||||
chain);
|
||||
#endif
|
||||
spin_lock_bh(&radar->lock);
|
||||
radar->dpd[chain]->enabled = enable;
|
||||
@@ -1476,7 +1472,7 @@ bool rwnx_radar_detection_is_enable(struct rwnx_radar *radar, u8 chain)
|
||||
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
void rwnx_radar_start_cac(struct rwnx_radar *radar, u32 cac_time_ms,
|
||||
struct rwnx_vif *vif)
|
||||
struct rwnx_vif *vif)
|
||||
{
|
||||
WARN(radar->cac_vif != NULL, "CAC already in progress");
|
||||
radar->cac_vif = vif;
|
||||
@@ -1496,10 +1492,10 @@ void rwnx_radar_cancel_cac(struct rwnx_radar *radar)
|
||||
ctxt = &rwnx_hw->chanctx_table[radar->cac_vif->ch_index];
|
||||
rwnx_send_apm_stop_cac_req(rwnx_hw, radar->cac_vif);
|
||||
cfg80211_cac_event(radar->cac_vif->ndev,
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
|
||||
&ctxt->chan_def,
|
||||
#endif
|
||||
NL80211_RADAR_CAC_ABORTED, GFP_KERNEL);
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
|
||||
&ctxt->chan_def,
|
||||
#endif
|
||||
NL80211_RADAR_CAC_ABORTED, GFP_KERNEL);
|
||||
rwnx_chanctx_unlink(radar->cac_vif);
|
||||
}
|
||||
|
||||
@@ -1517,12 +1513,12 @@ void rwnx_radar_detection_enable_on_cur_channel(struct rwnx_hw *rwnx_hw)
|
||||
ctxt = &rwnx_hw->chanctx_table[rwnx_hw->cur_chanctx];
|
||||
if (ctxt->chan_def.chan->flags & IEEE80211_CHAN_RADAR) {
|
||||
rwnx_radar_detection_enable(&rwnx_hw->radar,
|
||||
RWNX_RADAR_DETECT_REPORT,
|
||||
RWNX_RADAR_RIU);
|
||||
RWNX_RADAR_DETECT_REPORT,
|
||||
RWNX_RADAR_RIU);
|
||||
} else {
|
||||
rwnx_radar_detection_enable(&rwnx_hw->radar,
|
||||
RWNX_RADAR_DETECT_DISABLE,
|
||||
RWNX_RADAR_RIU);
|
||||
RWNX_RADAR_DETECT_DISABLE,
|
||||
RWNX_RADAR_RIU);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_RWNX_FULLMAC */
|
||||
@@ -1530,9 +1526,8 @@ void rwnx_radar_detection_enable_on_cur_channel(struct rwnx_hw *rwnx_hw)
|
||||
/*****************************************************************************
|
||||
* Debug functions
|
||||
*****************************************************************************/
|
||||
static
|
||||
int rwnx_radar_dump_pri_detector(char *buf, size_t len,
|
||||
struct pri_detector *pde)
|
||||
static int rwnx_radar_dump_pri_detector(char *buf, size_t len,
|
||||
struct pri_detector *pde)
|
||||
{
|
||||
char freq_info[] = "Freq = %3.dMhz\n";
|
||||
char seq_info[] = " pri | count | false \n";
|
||||
@@ -1545,7 +1540,7 @@ int rwnx_radar_dump_pri_detector(char *buf, size_t len,
|
||||
|
||||
if (buf == NULL) {
|
||||
int nb_seq = 1;
|
||||
list_for_each_entry(seq, &pde->sequences, head) {
|
||||
list_for_each_entry (seq, &pde->sequences, head) {
|
||||
nb_seq++;
|
||||
}
|
||||
|
||||
@@ -1560,9 +1555,10 @@ int rwnx_radar_dump_pri_detector(char *buf, size_t len,
|
||||
write += res;
|
||||
len -= res;
|
||||
|
||||
list_for_each_entry(seq, &pde->sequences, head) {
|
||||
res = scnprintf(&buf[write], len, " %6.d | %2.d | %.2d \n",
|
||||
seq->pri, seq->count, seq->count_falses);
|
||||
list_for_each_entry (seq, &pde->sequences, head) {
|
||||
res = scnprintf(&buf[write], len,
|
||||
" %6.d | %2.d | %.2d \n", seq->pri,
|
||||
seq->count, seq->count_falses);
|
||||
write += res;
|
||||
len -= res;
|
||||
}
|
||||
@@ -1571,7 +1567,7 @@ int rwnx_radar_dump_pri_detector(char *buf, size_t len,
|
||||
}
|
||||
|
||||
int rwnx_radar_dump_pattern_detector(char *buf, size_t len,
|
||||
struct rwnx_radar *radar, u8 chain)
|
||||
struct rwnx_radar *radar, u8 chain)
|
||||
{
|
||||
struct dfs_pattern_detector *dpd = radar->dpd[chain];
|
||||
char info[] = "Type = %3.d\n";
|
||||
@@ -1583,12 +1579,13 @@ int rwnx_radar_dump_pattern_detector(char *buf, size_t len,
|
||||
int size_needed = 0;
|
||||
|
||||
for (i = 0; i < dpd->num_radar_types; i++) {
|
||||
list_for_each_entry(pde, &dpd->detectors[i], head) {
|
||||
size_needed += rwnx_radar_dump_pri_detector(NULL, 0, pde);
|
||||
list_for_each_entry (pde, &dpd->detectors[i], head) {
|
||||
size_needed += rwnx_radar_dump_pri_detector(
|
||||
NULL, 0, pde);
|
||||
}
|
||||
size_needed += sizeof(info);
|
||||
|
||||
return size_needed;
|
||||
return size_needed;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1598,8 +1595,9 @@ int rwnx_radar_dump_pattern_detector(char *buf, size_t len,
|
||||
|
||||
write += res;
|
||||
len -= res;
|
||||
list_for_each_entry(pde, &dpd->detectors[i], head) {
|
||||
res = rwnx_radar_dump_pri_detector(&buf[write], len, pde);
|
||||
list_for_each_entry (pde, &dpd->detectors[i], head) {
|
||||
res = rwnx_radar_dump_pri_detector(&buf[write], len,
|
||||
pde);
|
||||
write += res;
|
||||
len -= res;
|
||||
}
|
||||
@@ -1608,9 +1606,8 @@ int rwnx_radar_dump_pattern_detector(char *buf, size_t len,
|
||||
return write;
|
||||
}
|
||||
|
||||
|
||||
int rwnx_radar_dump_radar_detected(char *buf, size_t len,
|
||||
struct rwnx_radar *radar, u8 chain)
|
||||
struct rwnx_radar *radar, u8 chain)
|
||||
{
|
||||
struct rwnx_radar_detected *detect = &(radar->detected[chain]);
|
||||
char info[] = "2001/02/02 - 02:20 5126MHz\n";
|
||||
@@ -1622,7 +1619,7 @@ int rwnx_radar_dump_radar_detected(char *buf, size_t len,
|
||||
|
||||
if (buf == NULL) {
|
||||
return (count * sizeof(info)) + 1;
|
||||
}
|
||||
}
|
||||
|
||||
idx = (detect->index - detect->count) % NX_NB_RADAR_DETECTED;
|
||||
|
||||
@@ -1631,9 +1628,10 @@ int rwnx_radar_dump_radar_detected(char *buf, size_t len,
|
||||
time64_to_tm(detect->time[idx], 0, &tm);
|
||||
|
||||
res = scnprintf(&buf[write], len,
|
||||
"%.4d/%.2d/%.2d - %.2d:%.2d %4.4dMHz\n",
|
||||
(int)tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
|
||||
tm.tm_hour, tm.tm_min, detect->freq[idx]);
|
||||
"%.4d/%.2d/%.2d - %.2d:%.2d %4.4dMHz\n",
|
||||
(int)tm.tm_year + 1900, tm.tm_mon + 1,
|
||||
tm.tm_mday, tm.tm_hour, tm.tm_min,
|
||||
detect->freq[idx]);
|
||||
write += res;
|
||||
len -= res;
|
||||
|
||||
|
||||
@@ -18,17 +18,13 @@
|
||||
struct rwnx_vif;
|
||||
struct rwnx_hw;
|
||||
|
||||
enum rwnx_radar_chain {
|
||||
RWNX_RADAR_RIU = 0,
|
||||
RWNX_RADAR_FCU,
|
||||
RWNX_RADAR_LAST
|
||||
};
|
||||
enum rwnx_radar_chain { RWNX_RADAR_RIU = 0, RWNX_RADAR_FCU, RWNX_RADAR_LAST };
|
||||
|
||||
enum rwnx_radar_detector {
|
||||
RWNX_RADAR_DETECT_DISABLE = 0, /* Ignore radar pulses */
|
||||
RWNX_RADAR_DETECT_ENABLE = 1, /* Process pattern detection but do not
|
||||
RWNX_RADAR_DETECT_ENABLE = 1, /* Process pattern detection but do not
|
||||
report radar to upper layer (for test) */
|
||||
RWNX_RADAR_DETECT_REPORT = 2 /* Process pattern detection and report
|
||||
RWNX_RADAR_DETECT_REPORT = 2 /* Process pattern detection and report
|
||||
radar to upper layer. */
|
||||
};
|
||||
|
||||
@@ -36,7 +32,7 @@ enum rwnx_radar_detector {
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define RWNX_RADAR_PULSE_MAX 32
|
||||
#define RWNX_RADAR_PULSE_MAX 32
|
||||
|
||||
/**
|
||||
* struct rwnx_radar_pulses - List of pulses reported by HW
|
||||
@@ -82,78 +78,92 @@ struct rwnx_radar_detected {
|
||||
s16 freq[NX_NB_RADAR_DETECTED];
|
||||
};
|
||||
|
||||
|
||||
struct rwnx_radar {
|
||||
struct rwnx_radar_pulses pulses[RWNX_RADAR_LAST];
|
||||
struct dfs_pattern_detector *dpd[RWNX_RADAR_LAST];
|
||||
struct rwnx_radar_detected detected[RWNX_RADAR_LAST];
|
||||
struct work_struct detection_work; /* Work used to process radar pulses */
|
||||
spinlock_t lock; /* lock for pulses processing */
|
||||
struct work_struct detection_work; /* Work used to process radar pulses */
|
||||
spinlock_t lock; /* lock for pulses processing */
|
||||
|
||||
/* In softmac cac is handled by mac80211 */
|
||||
#ifdef CONFIG_RWNX_FULLMAC
|
||||
struct delayed_work cac_work; /* Work used to handle CAC */
|
||||
struct rwnx_vif *cac_vif; /* vif on which we started CAC */
|
||||
struct delayed_work cac_work; /* Work used to handle CAC */
|
||||
struct rwnx_vif *cac_vif; /* vif on which we started CAC */
|
||||
#endif
|
||||
};
|
||||
|
||||
bool rwnx_radar_detection_init(struct rwnx_radar *radar);
|
||||
void rwnx_radar_detection_deinit(struct rwnx_radar *radar);
|
||||
bool rwnx_radar_set_domain(struct rwnx_radar *radar,
|
||||
enum nl80211_dfs_regions region);
|
||||
enum nl80211_dfs_regions region);
|
||||
void rwnx_radar_detection_enable(struct rwnx_radar *radar, u8 enable, u8 chain);
|
||||
bool rwnx_radar_detection_is_enable(struct rwnx_radar *radar, u8 chain);
|
||||
void rwnx_radar_start_cac(struct rwnx_radar *radar, u32 cac_time_ms,
|
||||
struct rwnx_vif *vif);
|
||||
struct rwnx_vif *vif);
|
||||
void rwnx_radar_cancel_cac(struct rwnx_radar *radar);
|
||||
void rwnx_radar_detection_enable_on_cur_channel(struct rwnx_hw *rwnx_hw);
|
||||
int rwnx_radar_dump_pattern_detector(char *buf, size_t len,
|
||||
struct rwnx_radar *radar, u8 chain);
|
||||
int rwnx_radar_dump_radar_detected(char *buf, size_t len,
|
||||
struct rwnx_radar *radar, u8 chain);
|
||||
int rwnx_radar_dump_pattern_detector(char *buf, size_t len,
|
||||
struct rwnx_radar *radar, u8 chain);
|
||||
int rwnx_radar_dump_radar_detected(char *buf, size_t len,
|
||||
struct rwnx_radar *radar, u8 chain);
|
||||
|
||||
#else
|
||||
|
||||
struct rwnx_radar {
|
||||
};
|
||||
struct rwnx_radar {};
|
||||
|
||||
static inline bool rwnx_radar_detection_init(struct rwnx_radar *radar)
|
||||
{return true; }
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline void rwnx_radar_detection_deinit(struct rwnx_radar *radar)
|
||||
{}
|
||||
{
|
||||
}
|
||||
|
||||
static inline bool rwnx_radar_set_domain(struct rwnx_radar *radar,
|
||||
enum nl80211_dfs_regions region)
|
||||
{return true; }
|
||||
enum nl80211_dfs_regions region)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline void rwnx_radar_detection_enable(struct rwnx_radar *radar,
|
||||
u8 enable, u8 chain)
|
||||
{}
|
||||
u8 enable, u8 chain)
|
||||
{
|
||||
}
|
||||
|
||||
static inline bool rwnx_radar_detection_is_enable(struct rwnx_radar *radar,
|
||||
u8 chain)
|
||||
{return false; }
|
||||
u8 chain)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline void rwnx_radar_start_cac(struct rwnx_radar *radar,
|
||||
u32 cac_time_ms, struct rwnx_vif *vif)
|
||||
{}
|
||||
u32 cac_time_ms, struct rwnx_vif *vif)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void rwnx_radar_cancel_cac(struct rwnx_radar *radar)
|
||||
{}
|
||||
{
|
||||
}
|
||||
|
||||
static inline void rwnx_radar_detection_enable_on_cur_channel(struct rwnx_hw *rwnx_hw)
|
||||
{}
|
||||
static inline void
|
||||
rwnx_radar_detection_enable_on_cur_channel(struct rwnx_hw *rwnx_hw)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int rwnx_radar_dump_pattern_detector(char *buf, size_t len,
|
||||
struct rwnx_radar *radar,
|
||||
u8 chain)
|
||||
{return 0; }
|
||||
struct rwnx_radar *radar,
|
||||
u8 chain)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int rwnx_radar_dump_radar_detected(char *buf, size_t len,
|
||||
struct rwnx_radar *radar,
|
||||
u8 chain)
|
||||
{return 0; }
|
||||
struct rwnx_radar *radar,
|
||||
u8 chain)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RWNX_RADAR */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -12,10 +12,10 @@
|
||||
|
||||
#include "aicwf_txrxif.h"
|
||||
|
||||
#define SERVER_PORT 67
|
||||
#define CLIENT_PORT 68
|
||||
#define DHCP_MAGIC 0x63825363
|
||||
#define DHCP_ACK 5
|
||||
#define SERVER_PORT 67
|
||||
#define CLIENT_PORT 68
|
||||
#define DHCP_MAGIC 0x63825363
|
||||
#define DHCP_ACK 5
|
||||
#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
|
||||
#define DHCP_OPTION_END 255
|
||||
|
||||
@@ -38,147 +38,146 @@ enum rx_status_bits {
|
||||
RX_STAT_MONITOR = 1 << 7,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Decryption status subfields.
|
||||
* {
|
||||
*/
|
||||
#define RWNX_RX_HD_DECR_UNENC 0 // ENCRYPTION TYPE NONE
|
||||
#define RWNX_RX_HD_DECR_WEP 1 // ENCRYPTION TYPE WEP
|
||||
#define RWNX_RX_HD_DECR_TKIP 2 // ENCRYPTION TYPE TKIP
|
||||
#define RWNX_RX_HD_DECR_CCMP128 3 // ENCRYPTION TYPE CCMP128
|
||||
#define RWNX_RX_HD_DECR_CCMP256 4 // ENCRYPTION TYPE CCMP256
|
||||
#define RWNX_RX_HD_DECR_GCMP128 5 // ENCRYPTION TYPE GCMP128
|
||||
#define RWNX_RX_HD_DECR_GCMP256 6 // ENCRYPTION TYPE GCMP256
|
||||
#define RWNX_RX_HD_DECR_WAPI 7 // ENCRYPTION TYPE WAPI
|
||||
#define RWNX_RX_HD_DECR_UNENC 0 // ENCRYPTION TYPE NONE
|
||||
#define RWNX_RX_HD_DECR_WEP 1 // ENCRYPTION TYPE WEP
|
||||
#define RWNX_RX_HD_DECR_TKIP 2 // ENCRYPTION TYPE TKIP
|
||||
#define RWNX_RX_HD_DECR_CCMP128 3 // ENCRYPTION TYPE CCMP128
|
||||
#define RWNX_RX_HD_DECR_CCMP256 4 // ENCRYPTION TYPE CCMP256
|
||||
#define RWNX_RX_HD_DECR_GCMP128 5 // ENCRYPTION TYPE GCMP128
|
||||
#define RWNX_RX_HD_DECR_GCMP256 6 // ENCRYPTION TYPE GCMP256
|
||||
#define RWNX_RX_HD_DECR_WAPI 7 // ENCRYPTION TYPE WAPI
|
||||
// @}
|
||||
|
||||
//#ifdef CONFIG_RWNX_MON_DATA
|
||||
#if 0
|
||||
#define RX_MACHDR_BACKUP_LEN 64
|
||||
#define RX_MACHDR_BACKUP_LEN 64
|
||||
#endif
|
||||
|
||||
struct rx_vector_1_old {
|
||||
/** Receive Vector 1a */
|
||||
u32 leg_length :12;
|
||||
u32 leg_rate : 4;
|
||||
u32 ht_length :16;
|
||||
u32 leg_length : 12;
|
||||
u32 leg_rate : 4;
|
||||
u32 ht_length : 16;
|
||||
|
||||
/** Receive Vector 1b */
|
||||
u32 _ht_length : 4; // FIXME
|
||||
u32 short_gi : 1;
|
||||
u32 stbc : 2;
|
||||
u32 smoothing : 1;
|
||||
u32 mcs : 7;
|
||||
u32 pre_type : 1;
|
||||
u32 format_mod : 3;
|
||||
u32 ch_bw : 2;
|
||||
u32 n_sts : 3;
|
||||
u32 lsig_valid : 1;
|
||||
u32 sounding : 1;
|
||||
u32 num_extn_ss : 2;
|
||||
u32 aggregation : 1;
|
||||
u32 fec_coding : 1;
|
||||
u32 dyn_bw : 1;
|
||||
u32 doze_not_allowed : 1;
|
||||
u32 _ht_length : 4; // FIXME
|
||||
u32 short_gi : 1;
|
||||
u32 stbc : 2;
|
||||
u32 smoothing : 1;
|
||||
u32 mcs : 7;
|
||||
u32 pre_type : 1;
|
||||
u32 format_mod : 3;
|
||||
u32 ch_bw : 2;
|
||||
u32 n_sts : 3;
|
||||
u32 lsig_valid : 1;
|
||||
u32 sounding : 1;
|
||||
u32 num_extn_ss : 2;
|
||||
u32 aggregation : 1;
|
||||
u32 fec_coding : 1;
|
||||
u32 dyn_bw : 1;
|
||||
u32 doze_not_allowed : 1;
|
||||
|
||||
/** Receive Vector 1c */
|
||||
u32 antenna_set : 8;
|
||||
u32 partial_aid : 9;
|
||||
u32 group_id : 6;
|
||||
u32 first_user : 1;
|
||||
s32 rssi1 : 8;
|
||||
u32 antenna_set : 8;
|
||||
u32 partial_aid : 9;
|
||||
u32 group_id : 6;
|
||||
u32 first_user : 1;
|
||||
s32 rssi1 : 8;
|
||||
|
||||
/** Receive Vector 1d */
|
||||
s32 rssi2 : 8;
|
||||
s32 rssi3 : 8;
|
||||
s32 rssi4 : 8;
|
||||
u32 reserved_1d : 8;
|
||||
s32 rssi2 : 8;
|
||||
s32 rssi3 : 8;
|
||||
s32 rssi4 : 8;
|
||||
u32 reserved_1d : 8;
|
||||
};
|
||||
|
||||
struct rx_leg_vect {
|
||||
u8 dyn_bw_in_non_ht : 1;
|
||||
u8 chn_bw_in_non_ht : 2;
|
||||
u8 rsvd_nht : 4;
|
||||
u8 lsig_valid : 1;
|
||||
u8 dyn_bw_in_non_ht : 1;
|
||||
u8 chn_bw_in_non_ht : 2;
|
||||
u8 rsvd_nht : 4;
|
||||
u8 lsig_valid : 1;
|
||||
} __packed;
|
||||
|
||||
struct rx_ht_vect {
|
||||
u16 sounding : 1;
|
||||
u16 smoothing : 1;
|
||||
u16 short_gi : 1;
|
||||
u16 aggregation : 1;
|
||||
u16 stbc : 1;
|
||||
u16 num_extn_ss : 2;
|
||||
u16 lsig_valid : 1;
|
||||
u16 mcs : 7;
|
||||
u16 fec : 1;
|
||||
u16 length :16;
|
||||
u16 sounding : 1;
|
||||
u16 smoothing : 1;
|
||||
u16 short_gi : 1;
|
||||
u16 aggregation : 1;
|
||||
u16 stbc : 1;
|
||||
u16 num_extn_ss : 2;
|
||||
u16 lsig_valid : 1;
|
||||
u16 mcs : 7;
|
||||
u16 fec : 1;
|
||||
u16 length : 16;
|
||||
} __packed;
|
||||
|
||||
struct rx_vht_vect {
|
||||
u8 sounding : 1;
|
||||
u8 beamformed : 1;
|
||||
u8 short_gi : 1;
|
||||
u8 rsvd_vht1 : 1;
|
||||
u8 stbc : 1;
|
||||
u8 doze_not_allowed : 1;
|
||||
u8 first_user : 1;
|
||||
u8 rsvd_vht2 : 1;
|
||||
u16 partial_aid : 9;
|
||||
u16 group_id : 6;
|
||||
u16 rsvd_vht3 : 1;
|
||||
u32 mcs : 4;
|
||||
u32 nss : 3;
|
||||
u32 fec : 1;
|
||||
u32 length :20;
|
||||
u32 rsvd_vht4 : 4;
|
||||
u8 sounding : 1;
|
||||
u8 beamformed : 1;
|
||||
u8 short_gi : 1;
|
||||
u8 rsvd_vht1 : 1;
|
||||
u8 stbc : 1;
|
||||
u8 doze_not_allowed : 1;
|
||||
u8 first_user : 1;
|
||||
u8 rsvd_vht2 : 1;
|
||||
u16 partial_aid : 9;
|
||||
u16 group_id : 6;
|
||||
u16 rsvd_vht3 : 1;
|
||||
u32 mcs : 4;
|
||||
u32 nss : 3;
|
||||
u32 fec : 1;
|
||||
u32 length : 20;
|
||||
u32 rsvd_vht4 : 4;
|
||||
} __packed;
|
||||
|
||||
struct rx_he_vect {
|
||||
u8 sounding : 1;
|
||||
u8 beamformed : 1;
|
||||
u8 gi_type : 2;
|
||||
u8 stbc : 1;
|
||||
u8 rsvd_he1 : 3;
|
||||
u8 sounding : 1;
|
||||
u8 beamformed : 1;
|
||||
u8 gi_type : 2;
|
||||
u8 stbc : 1;
|
||||
u8 rsvd_he1 : 3;
|
||||
|
||||
u8 uplink_flag : 1;
|
||||
u8 beam_change : 1;
|
||||
u8 dcm : 1;
|
||||
u8 he_ltf_type : 2;
|
||||
u8 doppler : 1;
|
||||
u8 rsvd_he2 : 2;
|
||||
u8 uplink_flag : 1;
|
||||
u8 beam_change : 1;
|
||||
u8 dcm : 1;
|
||||
u8 he_ltf_type : 2;
|
||||
u8 doppler : 1;
|
||||
u8 rsvd_he2 : 2;
|
||||
|
||||
u8 bss_color : 6;
|
||||
u8 rsvd_he3 : 2;
|
||||
u8 bss_color : 6;
|
||||
u8 rsvd_he3 : 2;
|
||||
|
||||
u8 txop_duration : 7;
|
||||
u8 rsvd_he4 : 1;
|
||||
u8 txop_duration : 7;
|
||||
u8 rsvd_he4 : 1;
|
||||
|
||||
u8 pe_duration : 4;
|
||||
u8 spatial_reuse : 4;
|
||||
u8 pe_duration : 4;
|
||||
u8 spatial_reuse : 4;
|
||||
|
||||
u8 sig_b_comp_mode : 1;
|
||||
u8 dcm_sig_b : 1;
|
||||
u8 mcs_sig_b : 3;
|
||||
u8 ru_size : 3;
|
||||
u8 sig_b_comp_mode : 1;
|
||||
u8 dcm_sig_b : 1;
|
||||
u8 mcs_sig_b : 3;
|
||||
u8 ru_size : 3;
|
||||
|
||||
u32 mcs : 4;
|
||||
u32 nss : 3;
|
||||
u32 fec : 1;
|
||||
u32 length :20;
|
||||
u32 rsvd_he6 : 4;
|
||||
u32 mcs : 4;
|
||||
u32 nss : 3;
|
||||
u32 fec : 1;
|
||||
u32 length : 20;
|
||||
u32 rsvd_he6 : 4;
|
||||
} __packed;
|
||||
|
||||
struct rx_vector_1 {
|
||||
u8 format_mod : 4;
|
||||
u8 ch_bw : 3;
|
||||
u8 pre_type : 1;
|
||||
u8 antenna_set : 8;
|
||||
s32 rssi_leg : 8;
|
||||
u32 leg_length :12;
|
||||
u32 leg_rate : 4;
|
||||
s32 rssi1 : 8;
|
||||
u8 format_mod : 4;
|
||||
u8 ch_bw : 3;
|
||||
u8 pre_type : 1;
|
||||
u8 antenna_set : 8;
|
||||
s32 rssi_leg : 8;
|
||||
u32 leg_length : 12;
|
||||
u32 leg_rate : 4;
|
||||
s32 rssi1 : 8;
|
||||
|
||||
union {
|
||||
struct rx_leg_vect leg;
|
||||
@@ -190,51 +189,50 @@ struct rx_vector_1 {
|
||||
|
||||
struct rx_vector_2_old {
|
||||
/** Receive Vector 2a */
|
||||
u32 rcpi : 8;
|
||||
u32 evm1 : 8;
|
||||
u32 evm2 : 8;
|
||||
u32 evm3 : 8;
|
||||
u32 rcpi : 8;
|
||||
u32 evm1 : 8;
|
||||
u32 evm2 : 8;
|
||||
u32 evm3 : 8;
|
||||
|
||||
/** Receive Vector 2b */
|
||||
u32 evm4 : 8;
|
||||
u32 reserved2b_1 : 8;
|
||||
u32 reserved2b_2 : 8;
|
||||
u32 reserved2b_3 : 8;
|
||||
|
||||
u32 evm4 : 8;
|
||||
u32 reserved2b_1 : 8;
|
||||
u32 reserved2b_2 : 8;
|
||||
u32 reserved2b_3 : 8;
|
||||
};
|
||||
|
||||
struct rx_vector_2 {
|
||||
/** Receive Vector 2a */
|
||||
u32 rcpi1 : 8;
|
||||
u32 rcpi2 : 8;
|
||||
u32 rcpi3 : 8;
|
||||
u32 rcpi4 : 8;
|
||||
u32 rcpi1 : 8;
|
||||
u32 rcpi2 : 8;
|
||||
u32 rcpi3 : 8;
|
||||
u32 rcpi4 : 8;
|
||||
|
||||
/** Receive Vector 2b */
|
||||
u32 evm1 : 8;
|
||||
u32 evm2 : 8;
|
||||
u32 evm3 : 8;
|
||||
u32 evm4 : 8;
|
||||
u32 evm1 : 8;
|
||||
u32 evm2 : 8;
|
||||
u32 evm3 : 8;
|
||||
u32 evm4 : 8;
|
||||
};
|
||||
|
||||
struct phy_channel_info_desc {
|
||||
/** PHY channel information 1 */
|
||||
u32 phy_band : 8;
|
||||
u32 phy_channel_type : 8;
|
||||
u32 phy_prim20_freq : 16;
|
||||
u32 phy_band : 8;
|
||||
u32 phy_channel_type : 8;
|
||||
u32 phy_prim20_freq : 16;
|
||||
/** PHY channel information 2 */
|
||||
u32 phy_center1_freq : 16;
|
||||
u32 phy_center2_freq : 16;
|
||||
u32 phy_center1_freq : 16;
|
||||
u32 phy_center2_freq : 16;
|
||||
};
|
||||
|
||||
struct hw_vect {
|
||||
/** Total length for the MPDU transfer */
|
||||
u32 len :16;
|
||||
u32 len : 16;
|
||||
|
||||
u32 reserved : 8;//data type is included
|
||||
u32 reserved : 8; //data type is included
|
||||
/** AMPDU Status Information */
|
||||
u32 mpdu_cnt : 6;
|
||||
u32 ampdu_cnt : 2;
|
||||
u32 mpdu_cnt : 6;
|
||||
u32 ampdu_cnt : 2;
|
||||
|
||||
/** TSF Low */
|
||||
__le32 tsf_lo;
|
||||
@@ -247,29 +245,29 @@ struct hw_vect {
|
||||
struct rx_vector_2 rx_vect2;
|
||||
|
||||
/** Status **/
|
||||
u32 rx_vect2_valid : 1;
|
||||
u32 resp_frame : 1;
|
||||
u32 rx_vect2_valid : 1;
|
||||
u32 resp_frame : 1;
|
||||
/** Decryption Status */
|
||||
u32 decr_status : 3;
|
||||
u32 rx_fifo_oflow : 1;
|
||||
u32 decr_status : 3;
|
||||
u32 rx_fifo_oflow : 1;
|
||||
|
||||
/** Frame Unsuccessful */
|
||||
u32 undef_err : 1;
|
||||
u32 phy_err : 1;
|
||||
u32 fcs_err : 1;
|
||||
u32 addr_mismatch : 1;
|
||||
u32 ga_frame : 1;
|
||||
u32 current_ac : 2;
|
||||
u32 undef_err : 1;
|
||||
u32 phy_err : 1;
|
||||
u32 fcs_err : 1;
|
||||
u32 addr_mismatch : 1;
|
||||
u32 ga_frame : 1;
|
||||
u32 current_ac : 2;
|
||||
|
||||
u32 frm_successful_rx : 1;
|
||||
u32 frm_successful_rx : 1;
|
||||
/** Descriptor Done */
|
||||
u32 desc_done_rx : 1;
|
||||
u32 desc_done_rx : 1;
|
||||
/** Key Storage RAM Index */
|
||||
u32 key_sram_index : 10;
|
||||
u32 key_sram_index : 10;
|
||||
/** Key Storage RAM Index Valid */
|
||||
u32 key_sram_v : 1;
|
||||
u32 type : 2;
|
||||
u32 subtype : 4;
|
||||
u32 key_sram_v : 1;
|
||||
u32 type : 2;
|
||||
u32 subtype : 4;
|
||||
};
|
||||
|
||||
//#ifdef CONFIG_RWNX_MON_DATA
|
||||
@@ -291,36 +289,40 @@ struct hw_rxhdr {
|
||||
struct phy_channel_info_desc phy_info;
|
||||
|
||||
/** RX flags */
|
||||
u32 flags_is_amsdu : 1;
|
||||
u32 flags_is_80211_mpdu: 1;
|
||||
u32 flags_is_4addr : 1;
|
||||
u32 flags_new_peer : 1;
|
||||
u32 flags_is_amsdu : 1;
|
||||
u32 flags_is_80211_mpdu : 1;
|
||||
u32 flags_is_4addr : 1;
|
||||
u32 flags_new_peer : 1;
|
||||
#if defined(AICWF_SDIO_SUPPORT) || defined(AICWF_USB_SUPPORT)
|
||||
u32 flags_user_prio : 1; // aic: fw not fill any more
|
||||
u32 flags_need_reord : 1;
|
||||
u32 flags_upload : 1;
|
||||
u32 flags_user_prio : 1; // aic: fw not fill any more
|
||||
u32 flags_need_reord : 1;
|
||||
u32 flags_upload : 1;
|
||||
#else
|
||||
u32 flags_user_prio : 3;
|
||||
u32 flags_user_prio : 3;
|
||||
#endif
|
||||
#ifndef AICWF_RX_REORDER
|
||||
u32 flags_rsvd0 : 1;
|
||||
u32 flags_rsvd0 : 1;
|
||||
#else
|
||||
u32 is_monitor_vif : 1;
|
||||
u32 is_monitor_vif : 1;
|
||||
#endif
|
||||
u32 flags_vif_idx : 8; // 0xFF if invalid VIF index
|
||||
u32 flags_sta_idx : 8; // 0xFF if invalid STA index
|
||||
u32 flags_dst_idx : 8; // 0xFF if unknown destination STA
|
||||
u32 flags_vif_idx : 8; // 0xFF if invalid VIF index
|
||||
u32 flags_sta_idx : 8; // 0xFF if invalid STA index
|
||||
u32 flags_dst_idx : 8; // 0xFF if unknown destination STA
|
||||
//#ifdef CONFIG_RWNX_MON_DATA
|
||||
#if 0
|
||||
/// MAC header backup descriptor (used only for MSDU when there is a monitor and a data interface)
|
||||
struct mon_machdrdesc mac_hdr_backup;
|
||||
#endif
|
||||
/** Pattern indicating if the buffer is available for the driver */
|
||||
u32 pattern;
|
||||
u32 pattern;
|
||||
};
|
||||
|
||||
extern const u8 legrates_lut[];
|
||||
extern u16 legrates_lut_rate[];
|
||||
struct rwnx_legrate {
|
||||
int idx;
|
||||
int rate;
|
||||
};
|
||||
|
||||
extern struct rwnx_legrate legrates_lut[];
|
||||
extern u16 tx_legrates_lut_rate[];
|
||||
|
||||
struct DHCPInfo {
|
||||
@@ -350,41 +352,46 @@ void arpoffload_proc(struct sk_buff *skb, struct rwnx_vif *rwnx_vif);
|
||||
#endif
|
||||
#ifdef AICWF_RX_REORDER
|
||||
struct recv_msdu *reord_rxframe_alloc(spinlock_t *lock, struct list_head *q);
|
||||
void reord_rxframe_free(spinlock_t *lock, struct list_head *q, struct list_head *list);
|
||||
struct reord_ctrl_info *reord_init_sta(struct aicwf_rx_priv *rx_priv, const u8 *mac_addr);
|
||||
void reord_deinit_sta(struct aicwf_rx_priv *rx_priv, struct reord_ctrl_info *reord_info);
|
||||
void reord_rxframe_free(spinlock_t *lock, struct list_head *q,
|
||||
struct list_head *list);
|
||||
struct reord_ctrl_info *reord_init_sta(struct aicwf_rx_priv *rx_priv,
|
||||
const u8 *mac_addr);
|
||||
void reord_deinit_sta(struct aicwf_rx_priv *rx_priv,
|
||||
struct reord_ctrl_info *reord_info);
|
||||
int reord_need_check(struct reord_ctrl *preorder_ctrl, u16 seq_num);
|
||||
int reord_rxframe_enqueue(struct reord_ctrl *preorder_ctrl, struct recv_msdu *prframe);
|
||||
int reord_rxframe_enqueue(struct reord_ctrl *preorder_ctrl,
|
||||
struct recv_msdu *prframe);
|
||||
void reord_timeout_worker(struct work_struct *work);
|
||||
int reord_single_frame_ind(struct aicwf_rx_priv *rx_priv, struct recv_msdu *prframe);
|
||||
int reord_single_frame_ind(struct aicwf_rx_priv *rx_priv,
|
||||
struct recv_msdu *prframe);
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
|
||||
void reord_timeout_handler (ulong data);
|
||||
void reord_timeout_handler(ulong data);
|
||||
#else
|
||||
void reord_timeout_handler (struct timer_list *t);
|
||||
void reord_timeout_handler(struct timer_list *t);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
void rwnx_rxdata_process_amsdu(struct rwnx_hw *rwnx_hw, struct sk_buff *skb, u8 vif_idx,
|
||||
struct sk_buff_head *list);
|
||||
void rwnx_rxdata_process_amsdu(struct rwnx_hw *rwnx_hw, struct sk_buff *skb,
|
||||
u8 vif_idx, struct sk_buff_head *list);
|
||||
|
||||
#ifdef CONFIG_HE_FOR_OLD_KERNEL
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 197)
|
||||
struct element {
|
||||
u8 id;
|
||||
u8 datalen;
|
||||
u8 data[];
|
||||
u8 id;
|
||||
u8 datalen;
|
||||
u8 data[];
|
||||
};
|
||||
/* element iteration helpers */
|
||||
#define for_each_element(_elem, _data, _datalen) \
|
||||
for (_elem = (const struct element *)(_data); \
|
||||
(const u8 *)(_data) + (_datalen) - (const u8 *)_elem >= \
|
||||
(int)sizeof(*_elem) && \
|
||||
(const u8 *)(_data) + (_datalen) - (const u8 *)_elem >= \
|
||||
(int)sizeof(*_elem) + _elem->datalen; \
|
||||
#define for_each_element(_elem, _data, _datalen) \
|
||||
for (_elem = (const struct element *)(_data); \
|
||||
(const u8 *)(_data) + (_datalen) - (const u8 *)_elem >= \
|
||||
(int)sizeof(*_elem) && \
|
||||
(const u8 *)(_data) + (_datalen) - (const u8 *)_elem >= \
|
||||
(int)sizeof(*_elem) + _elem->datalen; \
|
||||
_elem = (const struct element *)(_elem->data + _elem->datalen))
|
||||
|
||||
#define for_each_element_id(element, _id, data, datalen) \
|
||||
for_each_element(element, data, datalen) \
|
||||
#define for_each_element_id(element, _id, data, datalen) \
|
||||
for_each_element (element, data, datalen) \
|
||||
if (element->id == (_id))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user